operands.isa (4687:db7ca06d6e6a) operands.isa (4712:79b4c64296ce)
1// Copyright (c) 2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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97
98def operands {{
99 'DestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 1),
100 'SrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 2),
101 'SrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 3),
102 'Base': ('IntReg', 'uqw', 'base', 'IsInteger', 4),
103 'Index': ('IntReg', 'uqw', 'index', 'IsInteger', 5),
104 'Data': ('IntReg', 'uqw', 'data', 'IsInteger', 6),
1// Copyright (c) 2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 88 unchanged lines hidden (view full) ---

97
98def operands {{
99 'DestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 1),
100 'SrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 2),
101 'SrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 3),
102 'Base': ('IntReg', 'uqw', 'base', 'IsInteger', 4),
103 'Index': ('IntReg', 'uqw', 'index', 'IsInteger', 5),
104 'Data': ('IntReg', 'uqw', 'data', 'IsInteger', 6),
105 'rax': ('IntReg', 'uqw', 'INTREG_RAX', 'IsInteger', 7),
105 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
106 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
107 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
108}};
106 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
107 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
108 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
109}};