operands.isa (4587:2c9a2534a489) | operands.isa (4687:db7ca06d6e6a) |
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1// Copyright (c) 2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 89 unchanged lines hidden (view full) --- 98def operands {{ 99 'DestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 1), 100 'SrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 2), 101 'SrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 3), 102 'Base': ('IntReg', 'uqw', 'base', 'IsInteger', 4), 103 'Index': ('IntReg', 'uqw', 'index', 'IsInteger', 5), 104 'Data': ('IntReg', 'uqw', 'data', 'IsInteger', 6), 105 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10), | 1// Copyright (c) 2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 89 unchanged lines hidden (view full) --- 98def operands {{ 99 'DestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 1), 100 'SrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 2), 101 'SrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 3), 102 'Base': ('IntReg', 'uqw', 'base', 'IsInteger', 4), 103 'Index': ('IntReg', 'uqw', 'index', 'IsInteger', 5), 104 'Data': ('IntReg', 'uqw', 'data', 'IsInteger', 6), 105 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10), |
106 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20), |
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106 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 107}}; | 107 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 108}}; |