operands.isa (4338:24d31b35bcf9) | operands.isa (4519:f8da6b45573f) |
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1// Copyright (c) 2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 82 unchanged lines hidden (view full) --- 91 'sqw' : ('signed int', 64), 92 'uqw' : ('unsigned int', 64), 93 'sf' : ('float', 32), 94 'df' : ('float', 64), 95 'qf' : ('float', 128) 96}}; 97 98def operands {{ | 1// Copyright (c) 2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 82 unchanged lines hidden (view full) --- 91 'sqw' : ('signed int', 64), 92 'uqw' : ('unsigned int', 64), 93 'sf' : ('float', 32), 94 'df' : ('float', 64), 95 'qf' : ('float', 128) 96}}; 97 98def operands {{ |
99 'DestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 1), 100 'SrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 2), 101 'SrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 3), |
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99 'IntRegOp0': ('IntReg', 'udw', 'param0', 'IsInteger', 1), 100 'IntRegOp1': ('IntReg', 'udw', 'param1', 'IsInteger', 2), 101 'IntRegOp2': ('IntReg', 'udw', 'param2', 'IsInteger', 2), 102}}; | 102 'IntRegOp0': ('IntReg', 'udw', 'param0', 'IsInteger', 1), 103 'IntRegOp1': ('IntReg', 'udw', 'param1', 'IsInteger', 2), 104 'IntRegOp2': ('IntReg', 'udw', 'param2', 'IsInteger', 2), 105}}; |