operands.isa (4279:acc38276ca1d) operands.isa (4298:a92aab35e34e)
1// Copyright (c) 2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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91 'sqw' : ('signed int', 64),
92 'uqw' : ('unsigned int', 64),
93 'sf' : ('float', 32),
94 'df' : ('float', 64),
95 'qf' : ('float', 128)
96}};
97
98def operands {{
1// Copyright (c) 2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 82 unchanged lines hidden (view full) ---

91 'sqw' : ('signed int', 64),
92 'uqw' : ('unsigned int', 64),
93 'sf' : ('float', 32),
94 'df' : ('float', 64),
95 'qf' : ('float', 128)
96}};
97
98def operands {{
99 # This is just copied from SPARC, because having no operands confuses
100 # the parser.
101 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1)
99 'IntRegOp0': ('IntReg', 'udw', 'regIndex0', 'IsInteger', 1),
100 'IntRegOp1': ('IntReg', 'udw', 'regIndex1', 'IsInteger', 2),
101 'IntRegOp2': ('IntReg', 'udw', 'regIndex2', 'IsInteger', 2),
102}};
102}};