1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Copyright (c) 2007 The Regents of The University of Michigan
| 1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Copyright (c) 2007 The Regents of The University of Michigan
|
| 14// Copyright (c) 2012 Mark D. Hill and David A. Wood
15// Copyright (c) 2012-2013 Advanced Micro Devices, Inc.
|
14// All rights reserved.
15//
16// Redistribution and use in source and binary forms, with or without
17// modification, are permitted provided that the following conditions are
18// met: redistributions of source code must retain the above copyright
19// notice, this list of conditions and the following disclaimer;
20// redistributions in binary form must reproduce the above copyright
21// notice, this list of conditions and the following disclaimer in the
22// documentation and/or other materials provided with the distribution;
23// neither the name of the copyright holders nor the names of its
24// contributors may be used to endorse or promote products derived from
25// this software without specific prior written permission.
26//
27// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38//
39// Authors: Gabe Black
40
41def operand_types {{
42 'sb' : 'int8_t',
43 'ub' : 'uint8_t',
44 'sw' : 'int16_t',
45 'uw' : 'uint16_t',
46 'sdw' : 'int32_t',
47 'udw' : 'uint32_t',
48 'sqw' : 'int64_t',
49 'uqw' : 'uint64_t',
50 'sf' : 'float',
51 'df' : 'double',
52}};
53
54let {{
55 def foldInt(idx, foldBit, id):
56 return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit),
57 'IsInteger', id)
58 def intReg(idx, id):
59 return ('IntReg', 'uqw', idx, 'IsInteger', id)
60 def impIntReg(idx, id):
61 return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id)
62 def floatReg(idx, id):
63 return ('FloatReg', 'df', idx, 'IsFloating', id)
| 16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Gabe Black
42
43def operand_types {{
44 'sb' : 'int8_t',
45 'ub' : 'uint8_t',
46 'sw' : 'int16_t',
47 'uw' : 'uint16_t',
48 'sdw' : 'int32_t',
49 'udw' : 'uint32_t',
50 'sqw' : 'int64_t',
51 'uqw' : 'uint64_t',
52 'sf' : 'float',
53 'df' : 'double',
54}};
55
56let {{
57 def foldInt(idx, foldBit, id):
58 return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit),
59 'IsInteger', id)
60 def intReg(idx, id):
61 return ('IntReg', 'uqw', idx, 'IsInteger', id)
62 def impIntReg(idx, id):
63 return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id)
64 def floatReg(idx, id):
65 return ('FloatReg', 'df', idx, 'IsFloating', id)
|
| 66 def ccReg(idx, id):
67 return ('CCReg', 'uqw', idx, 'IsCC', id)
|
64 def controlReg(idx, id, ctype = 'uqw'):
65 return ('ControlReg', ctype, idx,
66 (None, None, ['IsSerializeAfter',
67 'IsSerializing',
68 'IsNonSpeculative']),
69 id)
70 def squashCheckReg(idx, id, check, ctype = 'uqw'):
71 return ('ControlReg', ctype, idx,
72 (None, None, ['((%s) ? ' % check+ \
73 'IsSquashAfter : IsSerializeAfter)',
74 'IsSerializing',
75 'IsNonSpeculative']),
76 id)
77 def squashCReg(idx, id, ctype = 'uqw'):
78 return squashCheckReg(idx, id, 'true', ctype)
79 def squashCSReg(idx, id, ctype = 'uqw'):
80 return squashCheckReg(idx, id, 'dest == SEGMENT_REG_CS', ctype)
81 def squashCR0Reg(idx, id, ctype = 'uqw'):
82 return squashCheckReg(idx, id, 'dest == 0', ctype)
83}};
84
85def operands {{
86 'SrcReg1': foldInt('src1', 'foldOBit', 1),
87 'SSrcReg1': intReg('src1', 1),
88 'SrcReg2': foldInt('src2', 'foldOBit', 2),
89 'SSrcReg2': intReg('src2', 1),
90 'Index': foldInt('index', 'foldABit', 3),
91 'Base': foldInt('base', 'foldABit', 4),
92 'DestReg': foldInt('dest', 'foldOBit', 5),
93 'SDestReg': intReg('dest', 5),
94 'Data': foldInt('data', 'foldOBit', 6),
95 'ProdLow': impIntReg(0, 7),
96 'ProdHi': impIntReg(1, 8),
97 'Quotient': impIntReg(2, 9),
98 'Remainder': impIntReg(3, 10),
99 'Divisor': impIntReg(4, 11),
100 'DoubleBits': impIntReg(5, 11),
101 'Rax': intReg('(INTREG_RAX)', 12),
102 'Rbx': intReg('(INTREG_RBX)', 13),
103 'Rcx': intReg('(INTREG_RCX)', 14),
104 'Rdx': intReg('(INTREG_RDX)', 15),
105 'Rsp': intReg('(INTREG_RSP)', 16),
106 'Rbp': intReg('(INTREG_RBP)', 17),
107 'Rsi': intReg('(INTREG_RSI)', 18),
108 'Rdi': intReg('(INTREG_RDI)', 19),
109 'FpSrcReg1': floatReg('src1', 20),
110 'FpSrcReg2': floatReg('src2', 21),
111 'FpDestReg': floatReg('dest', 22),
112 'FpData': floatReg('data', 23),
113 'RIP': ('PCState', 'uqw', 'pc',
114 (None, None, 'IsControl'), 50),
115 'NRIP': ('PCState', 'uqw', 'npc',
116 (None, None, 'IsControl'), 50),
117 'nuIP': ('PCState', 'uqw', 'nupc',
118 (None, None, 'IsControl'), 50),
119 # These registers hold the condition code portion of the flag
120 # register. The nccFlagBits version holds the rest.
| 68 def controlReg(idx, id, ctype = 'uqw'):
69 return ('ControlReg', ctype, idx,
70 (None, None, ['IsSerializeAfter',
71 'IsSerializing',
72 'IsNonSpeculative']),
73 id)
74 def squashCheckReg(idx, id, check, ctype = 'uqw'):
75 return ('ControlReg', ctype, idx,
76 (None, None, ['((%s) ? ' % check+ \
77 'IsSquashAfter : IsSerializeAfter)',
78 'IsSerializing',
79 'IsNonSpeculative']),
80 id)
81 def squashCReg(idx, id, ctype = 'uqw'):
82 return squashCheckReg(idx, id, 'true', ctype)
83 def squashCSReg(idx, id, ctype = 'uqw'):
84 return squashCheckReg(idx, id, 'dest == SEGMENT_REG_CS', ctype)
85 def squashCR0Reg(idx, id, ctype = 'uqw'):
86 return squashCheckReg(idx, id, 'dest == 0', ctype)
87}};
88
89def operands {{
90 'SrcReg1': foldInt('src1', 'foldOBit', 1),
91 'SSrcReg1': intReg('src1', 1),
92 'SrcReg2': foldInt('src2', 'foldOBit', 2),
93 'SSrcReg2': intReg('src2', 1),
94 'Index': foldInt('index', 'foldABit', 3),
95 'Base': foldInt('base', 'foldABit', 4),
96 'DestReg': foldInt('dest', 'foldOBit', 5),
97 'SDestReg': intReg('dest', 5),
98 'Data': foldInt('data', 'foldOBit', 6),
99 'ProdLow': impIntReg(0, 7),
100 'ProdHi': impIntReg(1, 8),
101 'Quotient': impIntReg(2, 9),
102 'Remainder': impIntReg(3, 10),
103 'Divisor': impIntReg(4, 11),
104 'DoubleBits': impIntReg(5, 11),
105 'Rax': intReg('(INTREG_RAX)', 12),
106 'Rbx': intReg('(INTREG_RBX)', 13),
107 'Rcx': intReg('(INTREG_RCX)', 14),
108 'Rdx': intReg('(INTREG_RDX)', 15),
109 'Rsp': intReg('(INTREG_RSP)', 16),
110 'Rbp': intReg('(INTREG_RBP)', 17),
111 'Rsi': intReg('(INTREG_RSI)', 18),
112 'Rdi': intReg('(INTREG_RDI)', 19),
113 'FpSrcReg1': floatReg('src1', 20),
114 'FpSrcReg2': floatReg('src2', 21),
115 'FpDestReg': floatReg('dest', 22),
116 'FpData': floatReg('data', 23),
117 'RIP': ('PCState', 'uqw', 'pc',
118 (None, None, 'IsControl'), 50),
119 'NRIP': ('PCState', 'uqw', 'npc',
120 (None, None, 'IsControl'), 50),
121 'nuIP': ('PCState', 'uqw', 'nupc',
122 (None, None, 'IsControl'), 50),
123 # These registers hold the condition code portion of the flag
124 # register. The nccFlagBits version holds the rest.
|
121 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60),
122 'cfofBits': intReg('INTREG_PSEUDO(1)', 61),
123 'dfBit': intReg('INTREG_PSEUDO(2)', 62),
124 'ecfBit': intReg('INTREG_PSEUDO(3)', 63),
125 'ezfBit': intReg('INTREG_PSEUDO(4)', 64),
| 125 'ccFlagBits': ccReg('(CCREG_ZAPS)', 60),
126 'cfofBits': ccReg('(CCREG_CFOF)', 61),
127 'dfBit': ccReg('(CCREG_DF)', 62),
128 'ecfBit': ccReg('(CCREG_ECF)', 63),
129 'ezfBit': ccReg('(CCREG_EZF)', 64),
|
126
127 # These Pred registers are to be used where reading the portions of
128 # condition code registers is possibly optional, depending on how the
129 # check evaluates. There are two checks being specified, one tests if
130 # a register needs to be read, the other tests whether the register
131 # needs to be written to. It is unlikely that these would need to be
132 # used in the actual operation of the instruction. It is expected
133 # that these are used only in the flag code.
134
135 # Rationale behind the checks: at times, we need to partially update
136 # the condition code bits in a register. So we read the register even
137 # in the case when the all the bits will be written, or none of the
138 # bits will be written. The read predicate checks if any of the bits
139 # would be retained, the write predicate checks if any of the bits
140 # are being written.
141
| 130
131 # These Pred registers are to be used where reading the portions of
132 # condition code registers is possibly optional, depending on how the
133 # check evaluates. There are two checks being specified, one tests if
134 # a register needs to be read, the other tests whether the register
135 # needs to be written to. It is unlikely that these would need to be
136 # used in the actual operation of the instruction. It is expected
137 # that these are used only in the flag code.
138
139 # Rationale behind the checks: at times, we need to partially update
140 # the condition code bits in a register. So we read the register even
141 # in the case when the all the bits will be written, or none of the
142 # bits will be written. The read predicate checks if any of the bits
143 # would be retained, the write predicate checks if any of the bits
144 # are being written.
145
|
142 'PredccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', 'IsInteger',
| 146 'PredccFlagBits': ('CCReg', 'uqw', '(CCREG_ZAPS)', 'IsCC',
|
143 60, None, None, '''(((ext & (PFBit | AFBit | ZFBit | SFBit
144 )) != (PFBit | AFBit | ZFBit | SFBit )) &&
145 ((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0))''',
146 '((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0)'),
| 147 60, None, None, '''(((ext & (PFBit | AFBit | ZFBit | SFBit
148 )) != (PFBit | AFBit | ZFBit | SFBit )) &&
149 ((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0))''',
150 '((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0)'),
|
147 'PredcfofBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(1)', 'IsInteger',
| 151 'PredcfofBits': ('CCReg', 'uqw', '(CCREG_CFOF)', 'IsCC',
|
148 61, None, None, '''(((ext & CFBit) == 0 ||
149 (ext & OFBit) == 0) && ((ext & (CFBit | OFBit)) != 0))''',
150 '((ext & (CFBit | OFBit)) != 0)'),
| 152 61, None, None, '''(((ext & CFBit) == 0 ||
153 (ext & OFBit) == 0) && ((ext & (CFBit | OFBit)) != 0))''',
154 '((ext & (CFBit | OFBit)) != 0)'),
|
151 'PreddfBit': ('IntReg', 'uqw', 'INTREG_PSEUDO(2)', 'IsInteger',
| 155 'PreddfBit': ('CCReg', 'uqw', '(CCREG_DF)', 'IsCC',
|
152 62, None, None, '(false)', '((ext & DFBit) != 0)'),
| 156 62, None, None, '(false)', '((ext & DFBit) != 0)'),
|
153 'PredecfBit': ('IntReg', 'uqw', 'INTREG_PSEUDO(3)', 'IsInteger',
| 157 'PredecfBit': ('CCReg', 'uqw', '(CCREG_ECF)', 'IsCC',
|
154 63, None, None, '(false)', '((ext & ECFBit) != 0)'),
| 158 63, None, None, '(false)', '((ext & ECFBit) != 0)'),
|
155 'PredezfBit': ('IntReg', 'uqw', 'INTREG_PSEUDO(4)', 'IsInteger',
| 159 'PredezfBit': ('CCReg', 'uqw', '(CCREG_EZF)', 'IsCC',
|
156 64, None, None, '(false)', '((ext & EZFBit) != 0)'),
157
158 # These register should needs to be more protected so that later
159 # instructions don't map their indexes with an old value.
160 'nccFlagBits': controlReg('MISCREG_RFLAGS', 65),
161
162 # Registers related to the state of x87 floating point unit.
163 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'),
164 'FSW': controlReg('MISCREG_FSW', 67, ctype='uw'),
165 'FTW': controlReg('MISCREG_FTW', 68, ctype='uw'),
166 'FCW': controlReg('MISCREG_FCW', 69, ctype='uw'),
167
168 # The segment base as used by memory instructions.
169 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),
170
171 # Operands to get and set registers indexed by the operands of the
172 # original instruction.
173 'ControlDest': squashCR0Reg('MISCREG_CR(dest)', 100),
174 'ControlSrc1': controlReg('MISCREG_CR(src1)', 101),
175 'DebugDest': controlReg('MISCREG_DR(dest)', 102),
176 'DebugSrc1': controlReg('MISCREG_DR(src1)', 103),
177 'SegBaseDest': squashCSReg('MISCREG_SEG_BASE(dest)', 104),
178 'SegBaseSrc1': controlReg('MISCREG_SEG_BASE(src1)', 105),
179 'SegLimitDest': squashCSReg('MISCREG_SEG_LIMIT(dest)', 106),
180 'SegLimitSrc1': controlReg('MISCREG_SEG_LIMIT(src1)', 107),
181 'SegSelDest': controlReg('MISCREG_SEG_SEL(dest)', 108),
182 'SegSelSrc1': controlReg('MISCREG_SEG_SEL(src1)', 109),
183 'SegAttrDest': squashCSReg('MISCREG_SEG_ATTR(dest)', 110),
184 'SegAttrSrc1': controlReg('MISCREG_SEG_ATTR(src1)', 111),
185
186 # Operands to access specific control registers directly.
187 'EferOp': squashCReg('MISCREG_EFER', 200),
188 'CR4Op': controlReg('MISCREG_CR4', 201),
189 'DR7Op': controlReg('MISCREG_DR7', 202),
190 'LDTRBase': controlReg('MISCREG_TSL_BASE', 203),
191 'LDTRLimit': controlReg('MISCREG_TSL_LIMIT', 204),
192 'LDTRSel': controlReg('MISCREG_TSL', 205),
193 'GDTRBase': controlReg('MISCREG_TSG_BASE', 206),
194 'GDTRLimit': controlReg('MISCREG_TSG_LIMIT', 207),
195 'CSBase': squashCReg('MISCREG_CS_EFF_BASE', 208),
196 'CSAttr': squashCReg('MISCREG_CS_ATTR', 209),
197 'MiscRegDest': controlReg('dest', 210),
198 'MiscRegSrc1': controlReg('src1', 211),
199 'TscOp': controlReg('MISCREG_TSC', 212),
200 'M5Reg': squashCReg('MISCREG_M5_REG', 213),
201 'Mem': ('Mem', 'uqw', None, \
202 ('IsMemRef', 'IsLoad', 'IsStore'), 300)
203}};
| 160 64, None, None, '(false)', '((ext & EZFBit) != 0)'),
161
162 # These register should needs to be more protected so that later
163 # instructions don't map their indexes with an old value.
164 'nccFlagBits': controlReg('MISCREG_RFLAGS', 65),
165
166 # Registers related to the state of x87 floating point unit.
167 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'),
168 'FSW': controlReg('MISCREG_FSW', 67, ctype='uw'),
169 'FTW': controlReg('MISCREG_FTW', 68, ctype='uw'),
170 'FCW': controlReg('MISCREG_FCW', 69, ctype='uw'),
171
172 # The segment base as used by memory instructions.
173 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),
174
175 # Operands to get and set registers indexed by the operands of the
176 # original instruction.
177 'ControlDest': squashCR0Reg('MISCREG_CR(dest)', 100),
178 'ControlSrc1': controlReg('MISCREG_CR(src1)', 101),
179 'DebugDest': controlReg('MISCREG_DR(dest)', 102),
180 'DebugSrc1': controlReg('MISCREG_DR(src1)', 103),
181 'SegBaseDest': squashCSReg('MISCREG_SEG_BASE(dest)', 104),
182 'SegBaseSrc1': controlReg('MISCREG_SEG_BASE(src1)', 105),
183 'SegLimitDest': squashCSReg('MISCREG_SEG_LIMIT(dest)', 106),
184 'SegLimitSrc1': controlReg('MISCREG_SEG_LIMIT(src1)', 107),
185 'SegSelDest': controlReg('MISCREG_SEG_SEL(dest)', 108),
186 'SegSelSrc1': controlReg('MISCREG_SEG_SEL(src1)', 109),
187 'SegAttrDest': squashCSReg('MISCREG_SEG_ATTR(dest)', 110),
188 'SegAttrSrc1': controlReg('MISCREG_SEG_ATTR(src1)', 111),
189
190 # Operands to access specific control registers directly.
191 'EferOp': squashCReg('MISCREG_EFER', 200),
192 'CR4Op': controlReg('MISCREG_CR4', 201),
193 'DR7Op': controlReg('MISCREG_DR7', 202),
194 'LDTRBase': controlReg('MISCREG_TSL_BASE', 203),
195 'LDTRLimit': controlReg('MISCREG_TSL_LIMIT', 204),
196 'LDTRSel': controlReg('MISCREG_TSL', 205),
197 'GDTRBase': controlReg('MISCREG_TSG_BASE', 206),
198 'GDTRLimit': controlReg('MISCREG_TSG_LIMIT', 207),
199 'CSBase': squashCReg('MISCREG_CS_EFF_BASE', 208),
200 'CSAttr': squashCReg('MISCREG_CS_ATTR', 209),
201 'MiscRegDest': controlReg('dest', 210),
202 'MiscRegSrc1': controlReg('src1', 211),
203 'TscOp': controlReg('MISCREG_TSC', 212),
204 'M5Reg': squashCReg('MISCREG_M5_REG', 213),
205 'Mem': ('Mem', 'uqw', None, \
206 ('IsMemRef', 'IsLoad', 'IsStore'), 300)
207}};
|