1// Copyright (c) 2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Gabe Black
28
29// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
30// All rights reserved.
31//
32// Redistribution and use of this software in source and binary forms,
33// with or without modification, are permitted provided that the
34// following conditions are met:
35//
36// The software must be used only for Non-Commercial Use which means any
37// use which is NOT directed to receiving any direct monetary
38// compensation for, or commercial advantage from such use. Illustrative
39// examples of non-commercial use are academic research, personal study,
40// teaching, education and corporate research & development.
41// Illustrative examples of commercial use are distributing products for
42// commercial advantage and providing services using the software for
43// commercial advantage.
44//
45// If you wish to use this software or functionality therein that may be
46// covered by patents for commercial use, please contact:
47// Director of Intellectual Property Licensing
48// Office of Strategy and Technology
49// Hewlett-Packard Company
50// 1501 Page Mill Road
51// Palo Alto, California 94304
52//
53// Redistributions of source code must retain the above copyright notice,
54// this list of conditions and the following disclaimer. Redistributions
55// in binary form must reproduce the above copyright notice, this list of
56// conditions and the following disclaimer in the documentation and/or
57// other materials provided with the distribution. Neither the name of
58// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
59// contributors may be used to endorse or promote products derived from
60// this software without specific prior written permission. No right of
61// sublicense is granted herewith. Derivatives of the software and
62// output created using the software may be prepared, but only for
63// Non-Commercial Uses. Derivatives of the software may be shared with
64// others provided: (i) the others agree to abide by the list of
65// conditions herein which includes the Non-Commercial Use restrictions;
66// and (ii) such Derivatives of the software include the above copyright
67// notice to acknowledge the contribution from this software where
68// applicable, this list of conditions and the disclaimer below.
69//
70// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
71// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
72// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
73// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
74// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
75// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
76// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
77// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
78// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
79// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81//
82// Authors: Gabe Black
83
84def operand_types {{
85 'sb' : ('signed int', 8),
86 'ub' : ('unsigned int', 8),
87 'sw' : ('signed int', 16),
88 'uw' : ('unsigned int', 16),
89 'sdw' : ('signed int', 32),
90 'udw' : ('unsigned int', 32),
91 'sqw' : ('signed int', 64),
92 'uqw' : ('unsigned int', 64),
93 'sf' : ('float', 32),
94 'df' : ('float', 64),
95}};
96
97let {{
98 def foldInt(idx, foldBit, id):
99 return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit),
100 'IsInteger', id)
101 def intReg(idx, id):
102 return ('IntReg', 'uqw', idx, 'IsInteger', id)
103 def impIntReg(idx, id):
104 return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id)
105 def floatReg(idx, id):
106 return ('FloatReg', 'df', idx, 'IsFloating', id)
107 def controlReg(idx, id, ctype = 'uqw'):
108 return ('ControlReg', ctype, idx,
109 (None, None, ['IsSerializeAfter',
110 'IsSerializing',
111 'IsNonSpeculative']),
112 id)
113}};
114
115def operands {{
116 'SrcReg1': foldInt('src1', 'foldOBit', 1),
117 'SSrcReg1': intReg('src1', 1),
118 'SrcReg2': foldInt('src2', 'foldOBit', 2),
119 'SSrcReg2': intReg('src2', 1),
120 'Index': foldInt('index', 'foldABit', 3),
121 'Base': foldInt('base', 'foldABit', 4),
122 'DestReg': foldInt('dest', 'foldOBit', 5),
123 'SDestReg': intReg('dest', 5),
124 'Data': foldInt('data', 'foldOBit', 6),
125 'ProdLow': impIntReg(0, 7),
126 'ProdHi': impIntReg(1, 8),
127 'Quotient': impIntReg(2, 9),
128 'Remainder': impIntReg(3, 10),
129 'Divisor': impIntReg(4, 11),
| 1// Copyright (c) 2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Gabe Black
28
29// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
30// All rights reserved.
31//
32// Redistribution and use of this software in source and binary forms,
33// with or without modification, are permitted provided that the
34// following conditions are met:
35//
36// The software must be used only for Non-Commercial Use which means any
37// use which is NOT directed to receiving any direct monetary
38// compensation for, or commercial advantage from such use. Illustrative
39// examples of non-commercial use are academic research, personal study,
40// teaching, education and corporate research & development.
41// Illustrative examples of commercial use are distributing products for
42// commercial advantage and providing services using the software for
43// commercial advantage.
44//
45// If you wish to use this software or functionality therein that may be
46// covered by patents for commercial use, please contact:
47// Director of Intellectual Property Licensing
48// Office of Strategy and Technology
49// Hewlett-Packard Company
50// 1501 Page Mill Road
51// Palo Alto, California 94304
52//
53// Redistributions of source code must retain the above copyright notice,
54// this list of conditions and the following disclaimer. Redistributions
55// in binary form must reproduce the above copyright notice, this list of
56// conditions and the following disclaimer in the documentation and/or
57// other materials provided with the distribution. Neither the name of
58// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
59// contributors may be used to endorse or promote products derived from
60// this software without specific prior written permission. No right of
61// sublicense is granted herewith. Derivatives of the software and
62// output created using the software may be prepared, but only for
63// Non-Commercial Uses. Derivatives of the software may be shared with
64// others provided: (i) the others agree to abide by the list of
65// conditions herein which includes the Non-Commercial Use restrictions;
66// and (ii) such Derivatives of the software include the above copyright
67// notice to acknowledge the contribution from this software where
68// applicable, this list of conditions and the disclaimer below.
69//
70// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
71// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
72// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
73// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
74// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
75// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
76// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
77// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
78// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
79// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81//
82// Authors: Gabe Black
83
84def operand_types {{
85 'sb' : ('signed int', 8),
86 'ub' : ('unsigned int', 8),
87 'sw' : ('signed int', 16),
88 'uw' : ('unsigned int', 16),
89 'sdw' : ('signed int', 32),
90 'udw' : ('unsigned int', 32),
91 'sqw' : ('signed int', 64),
92 'uqw' : ('unsigned int', 64),
93 'sf' : ('float', 32),
94 'df' : ('float', 64),
95}};
96
97let {{
98 def foldInt(idx, foldBit, id):
99 return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit),
100 'IsInteger', id)
101 def intReg(idx, id):
102 return ('IntReg', 'uqw', idx, 'IsInteger', id)
103 def impIntReg(idx, id):
104 return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id)
105 def floatReg(idx, id):
106 return ('FloatReg', 'df', idx, 'IsFloating', id)
107 def controlReg(idx, id, ctype = 'uqw'):
108 return ('ControlReg', ctype, idx,
109 (None, None, ['IsSerializeAfter',
110 'IsSerializing',
111 'IsNonSpeculative']),
112 id)
113}};
114
115def operands {{
116 'SrcReg1': foldInt('src1', 'foldOBit', 1),
117 'SSrcReg1': intReg('src1', 1),
118 'SrcReg2': foldInt('src2', 'foldOBit', 2),
119 'SSrcReg2': intReg('src2', 1),
120 'Index': foldInt('index', 'foldABit', 3),
121 'Base': foldInt('base', 'foldABit', 4),
122 'DestReg': foldInt('dest', 'foldOBit', 5),
123 'SDestReg': intReg('dest', 5),
124 'Data': foldInt('data', 'foldOBit', 6),
125 'ProdLow': impIntReg(0, 7),
126 'ProdHi': impIntReg(1, 8),
127 'Quotient': impIntReg(2, 9),
128 'Remainder': impIntReg(3, 10),
129 'Divisor': impIntReg(4, 11),
|
130 'Rax': intReg('(INTREG_RAX)', 12),
131 'Rbx': intReg('(INTREG_RBX)', 13),
132 'Rcx': intReg('(INTREG_RCX)', 14),
133 'Rdx': intReg('(INTREG_RDX)', 15),
134 'Rsp': intReg('(INTREG_RSP)', 16),
135 'Rbp': intReg('(INTREG_RBP)', 17),
136 'Rsi': intReg('(INTREG_RSI)', 18),
137 'Rdi': intReg('(INTREG_RDI)', 19),
138 'FpSrcReg1': floatReg('src1', 20),
139 'FpSrcReg2': floatReg('src2', 21),
140 'FpDestReg': floatReg('dest', 22),
141 'FpData': floatReg('data', 23),
142 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50),
143 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
144 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
145 # This holds the condition code portion of the flag register. The
146 # nccFlagBits version holds the rest.
147 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60),
148 # These register should needs to be more protected so that later
149 # instructions don't map their indexes with an old value.
150 'nccFlagBits': controlReg('MISCREG_RFLAGS', 61),
151 'TOP': controlReg('MISCREG_X87_TOP', 62, ctype='ub'),
152 # The segment base as used by memory instructions.
153 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),
154
155 # Operands to get and set registers indexed by the operands of the
156 # original instruction.
157 'ControlDest': controlReg('MISCREG_CR(dest)', 100),
158 'ControlSrc1': controlReg('MISCREG_CR(src1)', 101),
159 'DebugDest': controlReg('MISCREG_DR(dest)', 102),
160 'DebugSrc1': controlReg('MISCREG_DR(src1)', 103),
161 'SegBaseDest': controlReg('MISCREG_SEG_BASE(dest)', 104),
162 'SegBaseSrc1': controlReg('MISCREG_SEG_BASE(src1)', 105),
163 'SegLimitDest': controlReg('MISCREG_SEG_LIMIT(dest)', 106),
164 'SegLimitSrc1': controlReg('MISCREG_SEG_LIMIT(src1)', 107),
165 'SegSelDest': controlReg('MISCREG_SEG_SEL(dest)', 108),
166 'SegSelSrc1': controlReg('MISCREG_SEG_SEL(src1)', 109),
167 'SegAttrDest': controlReg('MISCREG_SEG_ATTR(dest)', 110),
168 'SegAttrSrc1': controlReg('MISCREG_SEG_ATTR(src1)', 111),
169
170 # Operands to access specific control registers directly.
171 'EferOp': controlReg('MISCREG_EFER', 200),
172 'CR4Op': controlReg('MISCREG_CR4', 201),
173 'DR7Op': controlReg('MISCREG_DR7', 202),
174 'LDTRBase': controlReg('MISCREG_TSL_BASE', 203),
175 'LDTRLimit': controlReg('MISCREG_TSL_LIMIT', 204),
176 'LDTRSel': controlReg('MISCREG_TSL', 205),
177 'GDTRBase': controlReg('MISCREG_TSG_BASE', 206),
178 'GDTRLimit': controlReg('MISCREG_TSG_LIMIT', 207),
179 'CSBase': controlReg('MISCREG_CS_EFF_BASE', 208),
180 'CSAttr': controlReg('MISCREG_CS_ATTR', 209),
181 'MiscRegDest': controlReg('dest', 210),
182 'MiscRegSrc1': controlReg('src1', 211),
183 'TscOp': controlReg('MISCREG_TSC', 212),
184 'M5Reg': controlReg('MISCREG_M5_REG', 213),
185 'Mem': ('Mem', 'uqw', None, \
186 ('IsMemRef', 'IsLoad', 'IsStore'), 300)
187}};
| 131 'Rax': intReg('(INTREG_RAX)', 12),
132 'Rbx': intReg('(INTREG_RBX)', 13),
133 'Rcx': intReg('(INTREG_RCX)', 14),
134 'Rdx': intReg('(INTREG_RDX)', 15),
135 'Rsp': intReg('(INTREG_RSP)', 16),
136 'Rbp': intReg('(INTREG_RBP)', 17),
137 'Rsi': intReg('(INTREG_RSI)', 18),
138 'Rdi': intReg('(INTREG_RDI)', 19),
139 'FpSrcReg1': floatReg('src1', 20),
140 'FpSrcReg2': floatReg('src2', 21),
141 'FpDestReg': floatReg('dest', 22),
142 'FpData': floatReg('data', 23),
143 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50),
144 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
145 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
146 # This holds the condition code portion of the flag register. The
147 # nccFlagBits version holds the rest.
148 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60),
149 # These register should needs to be more protected so that later
150 # instructions don't map their indexes with an old value.
151 'nccFlagBits': controlReg('MISCREG_RFLAGS', 61),
152 'TOP': controlReg('MISCREG_X87_TOP', 62, ctype='ub'),
153 # The segment base as used by memory instructions.
154 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),
155
156 # Operands to get and set registers indexed by the operands of the
157 # original instruction.
158 'ControlDest': controlReg('MISCREG_CR(dest)', 100),
159 'ControlSrc1': controlReg('MISCREG_CR(src1)', 101),
160 'DebugDest': controlReg('MISCREG_DR(dest)', 102),
161 'DebugSrc1': controlReg('MISCREG_DR(src1)', 103),
162 'SegBaseDest': controlReg('MISCREG_SEG_BASE(dest)', 104),
163 'SegBaseSrc1': controlReg('MISCREG_SEG_BASE(src1)', 105),
164 'SegLimitDest': controlReg('MISCREG_SEG_LIMIT(dest)', 106),
165 'SegLimitSrc1': controlReg('MISCREG_SEG_LIMIT(src1)', 107),
166 'SegSelDest': controlReg('MISCREG_SEG_SEL(dest)', 108),
167 'SegSelSrc1': controlReg('MISCREG_SEG_SEL(src1)', 109),
168 'SegAttrDest': controlReg('MISCREG_SEG_ATTR(dest)', 110),
169 'SegAttrSrc1': controlReg('MISCREG_SEG_ATTR(src1)', 111),
170
171 # Operands to access specific control registers directly.
172 'EferOp': controlReg('MISCREG_EFER', 200),
173 'CR4Op': controlReg('MISCREG_CR4', 201),
174 'DR7Op': controlReg('MISCREG_DR7', 202),
175 'LDTRBase': controlReg('MISCREG_TSL_BASE', 203),
176 'LDTRLimit': controlReg('MISCREG_TSL_LIMIT', 204),
177 'LDTRSel': controlReg('MISCREG_TSL', 205),
178 'GDTRBase': controlReg('MISCREG_TSG_BASE', 206),
179 'GDTRLimit': controlReg('MISCREG_TSG_LIMIT', 207),
180 'CSBase': controlReg('MISCREG_CS_EFF_BASE', 208),
181 'CSAttr': controlReg('MISCREG_CS_ATTR', 209),
182 'MiscRegDest': controlReg('dest', 210),
183 'MiscRegSrc1': controlReg('src1', 211),
184 'TscOp': controlReg('MISCREG_TSC', 212),
185 'M5Reg': controlReg('MISCREG_M5_REG', 213),
186 'Mem': ('Mem', 'uqw', None, \
187 ('IsMemRef', 'IsLoad', 'IsStore'), 300)
188}};
|