1// Copyright (c) 2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Gabe Black
28
29// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
30// All rights reserved.
31//
32// Redistribution and use of this software in source and binary forms,
33// with or without modification, are permitted provided that the
34// following conditions are met:
35//
36// The software must be used only for Non-Commercial Use which means any
37// use which is NOT directed to receiving any direct monetary
38// compensation for, or commercial advantage from such use. Illustrative
39// examples of non-commercial use are academic research, personal study,
40// teaching, education and corporate research & development.
41// Illustrative examples of commercial use are distributing products for
42// commercial advantage and providing services using the software for
43// commercial advantage.
44//
45// If you wish to use this software or functionality therein that may be
46// covered by patents for commercial use, please contact:
47// Director of Intellectual Property Licensing
48// Office of Strategy and Technology
49// Hewlett-Packard Company
50// 1501 Page Mill Road
51// Palo Alto, California 94304
52//
53// Redistributions of source code must retain the above copyright notice,
54// this list of conditions and the following disclaimer. Redistributions
55// in binary form must reproduce the above copyright notice, this list of
56// conditions and the following disclaimer in the documentation and/or
57// other materials provided with the distribution. Neither the name of
58// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
59// contributors may be used to endorse or promote products derived from
60// this software without specific prior written permission. No right of
61// sublicense is granted herewith. Derivatives of the software and
62// output created using the software may be prepared, but only for
63// Non-Commercial Uses. Derivatives of the software may be shared with
64// others provided: (i) the others agree to abide by the list of
65// conditions herein which includes the Non-Commercial Use restrictions;
66// and (ii) such Derivatives of the software include the above copyright
67// notice to acknowledge the contribution from this software where
68// applicable, this list of conditions and the disclaimer below.
69//
70// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
71// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
72// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
73// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
74// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
75// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
76// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
77// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
78// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
79// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81//
82// Authors: Gabe Black
83
84def operand_types {{
85 'sb' : ('signed int', 8),
86 'ub' : ('unsigned int', 8),
87 'sw' : ('signed int', 16),
88 'uw' : ('unsigned int', 16),
89 'sdw' : ('signed int', 32),
90 'udw' : ('unsigned int', 32),
91 'sqw' : ('signed int', 64),
92 'uqw' : ('unsigned int', 64),
93 'sf' : ('float', 32),
94 'df' : ('float', 64),
95}};
96
97def operands {{
98 'SrcReg1': ('IntReg', 'uqw', 'INTREG_FOLDED(src1, foldOBit)', 'IsInteger', 1),
99 'SSrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 1),
100 'SrcReg2': ('IntReg', 'uqw', 'INTREG_FOLDED(src2, foldOBit)', 'IsInteger', 2),
101 'SSrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 1),
102 'Index': ('IntReg', 'uqw', 'INTREG_FOLDED(index, foldABit)', 'IsInteger', 3),
103 'Base': ('IntReg', 'uqw', 'INTREG_FOLDED(base, foldABit)', 'IsInteger', 4),
104 'DestReg': ('IntReg', 'uqw', 'INTREG_FOLDED(dest, foldOBit)', 'IsInteger', 5),
105 'SDestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 5),
106 'Data': ('IntReg', 'uqw', 'INTREG_FOLDED(data, foldOBit)', 'IsInteger', 6),
107 'ProdLow': ('IntReg', 'uqw', 'INTREG_IMPLICIT(0)', 'IsInteger', 7),
108 'ProdHi': ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8),
109 'Quotient': ('IntReg', 'uqw', 'INTREG_IMPLICIT(2)', 'IsInteger', 9),
110 'Remainder': ('IntReg', 'uqw', 'INTREG_IMPLICIT(3)', 'IsInteger', 10),
111 'Divisor': ('IntReg', 'uqw', 'INTREG_IMPLICIT(4)', 'IsInteger', 11),
| 1// Copyright (c) 2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Gabe Black
28
29// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
30// All rights reserved.
31//
32// Redistribution and use of this software in source and binary forms,
33// with or without modification, are permitted provided that the
34// following conditions are met:
35//
36// The software must be used only for Non-Commercial Use which means any
37// use which is NOT directed to receiving any direct monetary
38// compensation for, or commercial advantage from such use. Illustrative
39// examples of non-commercial use are academic research, personal study,
40// teaching, education and corporate research & development.
41// Illustrative examples of commercial use are distributing products for
42// commercial advantage and providing services using the software for
43// commercial advantage.
44//
45// If you wish to use this software or functionality therein that may be
46// covered by patents for commercial use, please contact:
47// Director of Intellectual Property Licensing
48// Office of Strategy and Technology
49// Hewlett-Packard Company
50// 1501 Page Mill Road
51// Palo Alto, California 94304
52//
53// Redistributions of source code must retain the above copyright notice,
54// this list of conditions and the following disclaimer. Redistributions
55// in binary form must reproduce the above copyright notice, this list of
56// conditions and the following disclaimer in the documentation and/or
57// other materials provided with the distribution. Neither the name of
58// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
59// contributors may be used to endorse or promote products derived from
60// this software without specific prior written permission. No right of
61// sublicense is granted herewith. Derivatives of the software and
62// output created using the software may be prepared, but only for
63// Non-Commercial Uses. Derivatives of the software may be shared with
64// others provided: (i) the others agree to abide by the list of
65// conditions herein which includes the Non-Commercial Use restrictions;
66// and (ii) such Derivatives of the software include the above copyright
67// notice to acknowledge the contribution from this software where
68// applicable, this list of conditions and the disclaimer below.
69//
70// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
71// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
72// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
73// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
74// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
75// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
76// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
77// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
78// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
79// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81//
82// Authors: Gabe Black
83
84def operand_types {{
85 'sb' : ('signed int', 8),
86 'ub' : ('unsigned int', 8),
87 'sw' : ('signed int', 16),
88 'uw' : ('unsigned int', 16),
89 'sdw' : ('signed int', 32),
90 'udw' : ('unsigned int', 32),
91 'sqw' : ('signed int', 64),
92 'uqw' : ('unsigned int', 64),
93 'sf' : ('float', 32),
94 'df' : ('float', 64),
95}};
96
97def operands {{
98 'SrcReg1': ('IntReg', 'uqw', 'INTREG_FOLDED(src1, foldOBit)', 'IsInteger', 1),
99 'SSrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 1),
100 'SrcReg2': ('IntReg', 'uqw', 'INTREG_FOLDED(src2, foldOBit)', 'IsInteger', 2),
101 'SSrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 1),
102 'Index': ('IntReg', 'uqw', 'INTREG_FOLDED(index, foldABit)', 'IsInteger', 3),
103 'Base': ('IntReg', 'uqw', 'INTREG_FOLDED(base, foldABit)', 'IsInteger', 4),
104 'DestReg': ('IntReg', 'uqw', 'INTREG_FOLDED(dest, foldOBit)', 'IsInteger', 5),
105 'SDestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 5),
106 'Data': ('IntReg', 'uqw', 'INTREG_FOLDED(data, foldOBit)', 'IsInteger', 6),
107 'ProdLow': ('IntReg', 'uqw', 'INTREG_IMPLICIT(0)', 'IsInteger', 7),
108 'ProdHi': ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8),
109 'Quotient': ('IntReg', 'uqw', 'INTREG_IMPLICIT(2)', 'IsInteger', 9),
110 'Remainder': ('IntReg', 'uqw', 'INTREG_IMPLICIT(3)', 'IsInteger', 10),
111 'Divisor': ('IntReg', 'uqw', 'INTREG_IMPLICIT(4)', 'IsInteger', 11),
|
113 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20),
114 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21),
115 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22),
116 'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23),
117 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50),
118 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
119 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
120 # This holds the condition code portion of the flag register. The
121 # nccFlagBits version holds the rest.
122 'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60),
123 # These register should needs to be more protected so that later
124 # instructions don't map their indexes with an old value.
125 'nccFlagBits': ('ControlReg', 'uqw', 'MISCREG_RFLAGS', None, 61),
126 'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 62),
127 # The segment base as used by memory instructions.
128 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_EFF_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
129
130 # Operands to get and set registers indexed by the operands of the
131 # original instruction.
132 'ControlDest': ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 100),
133 'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 101),
134 'SegBaseDest': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 102),
135 'SegBaseSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 103),
136 'SegLimitDest': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 104),
137 'SegLimitSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 105),
138 'SegSelDest': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 106),
139 'SegSelSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 107),
140 'SegAttrDest': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 108),
141 'SegAttrSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 109),
142
143 # Operands to access specific control registers directly.
144 'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 200),
145 'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 201),
146 'LDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSL_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 202),
147 'LDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSL_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 203),
148 'LDTRSel': ('ControlReg', 'uqw', 'MISCREG_TSL', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 204),
149 'GDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSG_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 205),
150 'GDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206),
151 'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207),
152 'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208),
153 'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 209),
154 'M5Reg': ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None, None), 210),
155 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300)
156}};
| 116 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20),
117 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21),
118 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22),
119 'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23),
120 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50),
121 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
122 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
123 # This holds the condition code portion of the flag register. The
124 # nccFlagBits version holds the rest.
125 'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60),
126 # These register should needs to be more protected so that later
127 # instructions don't map their indexes with an old value.
128 'nccFlagBits': ('ControlReg', 'uqw', 'MISCREG_RFLAGS', None, 61),
129 'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 62),
130 # The segment base as used by memory instructions.
131 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_EFF_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
132
133 # Operands to get and set registers indexed by the operands of the
134 # original instruction.
135 'ControlDest': ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 100),
136 'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 101),
137 'SegBaseDest': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 102),
138 'SegBaseSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 103),
139 'SegLimitDest': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 104),
140 'SegLimitSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 105),
141 'SegSelDest': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 106),
142 'SegSelSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 107),
143 'SegAttrDest': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 108),
144 'SegAttrSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 109),
145
146 # Operands to access specific control registers directly.
147 'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 200),
148 'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 201),
149 'LDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSL_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 202),
150 'LDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSL_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 203),
151 'LDTRSel': ('ControlReg', 'uqw', 'MISCREG_TSL', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 204),
152 'GDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSG_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 205),
153 'GDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206),
154 'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207),
155 'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208),
156 'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 209),
157 'M5Reg': ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None, None), 210),
158 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300)
159}};
|