operands.isa (5429:52dbcf7f7328) | operands.isa (5659:f4b9c344d1ca) |
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1// Copyright (c) 2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 95 unchanged lines hidden (view full) --- 104 'DestReg': ('IntReg', 'uqw', 'INTREG_FOLDED(dest, foldOBit)', 'IsInteger', 5), 105 'SDestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 5), 106 'Data': ('IntReg', 'uqw', 'INTREG_FOLDED(data, foldOBit)', 'IsInteger', 6), 107 'ProdLow': ('IntReg', 'uqw', 'INTREG_IMPLICIT(0)', 'IsInteger', 7), 108 'ProdHi': ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8), 109 'Quotient': ('IntReg', 'uqw', 'INTREG_IMPLICIT(2)', 'IsInteger', 9), 110 'Remainder': ('IntReg', 'uqw', 'INTREG_IMPLICIT(3)', 'IsInteger', 10), 111 'Divisor': ('IntReg', 'uqw', 'INTREG_IMPLICIT(4)', 'IsInteger', 11), | 1// Copyright (c) 2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 95 unchanged lines hidden (view full) --- 104 'DestReg': ('IntReg', 'uqw', 'INTREG_FOLDED(dest, foldOBit)', 'IsInteger', 5), 105 'SDestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 5), 106 'Data': ('IntReg', 'uqw', 'INTREG_FOLDED(data, foldOBit)', 'IsInteger', 6), 107 'ProdLow': ('IntReg', 'uqw', 'INTREG_IMPLICIT(0)', 'IsInteger', 7), 108 'ProdHi': ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8), 109 'Quotient': ('IntReg', 'uqw', 'INTREG_IMPLICIT(2)', 'IsInteger', 9), 110 'Remainder': ('IntReg', 'uqw', 'INTREG_IMPLICIT(3)', 'IsInteger', 10), 111 'Divisor': ('IntReg', 'uqw', 'INTREG_IMPLICIT(4)', 'IsInteger', 11), |
112 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 12), | 112 'Rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 12), 113 'Rbx': ('IntReg', 'uqw', '(INTREG_RBX)', 'IsInteger', 13), 114 'Rcx': ('IntReg', 'uqw', '(INTREG_RCX)', 'IsInteger', 14), 115 'Rdx': ('IntReg', 'uqw', '(INTREG_RDX)', 'IsInteger', 15), |
113 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20), 114 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21), 115 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22), 116 'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23), 117 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50), 118 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51), 119 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52), 120 # This holds the condition code portion of the flag register. The --- 36 unchanged lines hidden --- | 116 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20), 117 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21), 118 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22), 119 'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23), 120 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50), 121 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51), 122 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52), 123 # This holds the condition code portion of the flag register. The --- 36 unchanged lines hidden --- |