seqop.isa (7789:f455790bcd47) | seqop.isa (7894:48d31b577847) |
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1// Copyright (c) 2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 87 unchanged lines hidden (view full) --- 96def template SeqOpConstructor {{ 97 inline %(class_name)s::%(class_name)s( 98 ExtMachInst machInst, const char * instMnem, 99 uint64_t setFlags, uint16_t _target, uint8_t _cc) : 100 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 101 setFlags, _target, _cc) 102 { 103 %(constructor)s; | 1// Copyright (c) 2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 87 unchanged lines hidden (view full) --- 96def template SeqOpConstructor {{ 97 inline %(class_name)s::%(class_name)s( 98 ExtMachInst machInst, const char * instMnem, 99 uint64_t setFlags, uint16_t _target, uint8_t _cc) : 100 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 101 setFlags, _target, _cc) 102 { 103 %(constructor)s; |
104 %(cond_control_flag_init)s; |
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104 } 105}}; 106 107output decoder {{ 108 std::string SeqOpBase::generateDisassembly(Addr pc, 109 const SymbolTable *symtab) const 110 { 111 std::stringstream response; --- 54 unchanged lines hidden (view full) --- 166 microFlags.append("IsLastMicroop") 167 if "IsDelayedCommit" in microFlags: 168 microFlags.remove("IsDelayedCommit") 169 return super(Eret, self).getAllocator(microFlags) 170 171 iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase", 172 {"code": "nuIP = target;", 173 "else_code": "nuIP = nuIP;", | 105 } 106}}; 107 108output decoder {{ 109 std::string SeqOpBase::generateDisassembly(Addr pc, 110 const SymbolTable *symtab) const 111 { 112 std::stringstream response; --- 54 unchanged lines hidden (view full) --- 167 microFlags.append("IsLastMicroop") 168 if "IsDelayedCommit" in microFlags: 169 microFlags.remove("IsDelayedCommit") 170 return super(Eret, self).getAllocator(microFlags) 171 172 iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase", 173 {"code": "nuIP = target;", 174 "else_code": "nuIP = nuIP;", |
174 "cond_test": "checkCondition(ccFlagBits, cc)"}) | 175 "cond_test": "checkCondition(ccFlagBits, cc)", 176 "cond_control_flag_init": "flags[IsCondControl] = true"}) |
175 exec_output += SeqOpExecute.subst(iop) 176 header_output += SeqOpDeclare.subst(iop) 177 decoder_output += SeqOpConstructor.subst(iop) 178 iop = InstObjParams("br", "MicroBranch", "SeqOpBase", 179 {"code": "nuIP = target;", 180 "else_code": "nuIP = nuIP;", | 177 exec_output += SeqOpExecute.subst(iop) 178 header_output += SeqOpDeclare.subst(iop) 179 decoder_output += SeqOpConstructor.subst(iop) 180 iop = InstObjParams("br", "MicroBranch", "SeqOpBase", 181 {"code": "nuIP = target;", 182 "else_code": "nuIP = nuIP;", |
181 "cond_test": "true"}) | 183 "cond_test": "true", 184 "cond_control_flag_init": ""}) |
182 exec_output += SeqOpExecute.subst(iop) 183 header_output += SeqOpDeclare.subst(iop) 184 decoder_output += SeqOpConstructor.subst(iop) 185 microopClasses["br"] = Br 186 187 iop = InstObjParams("eret", "EretFlags", "SeqOpBase", 188 {"code": "", "else_code": "", | 185 exec_output += SeqOpExecute.subst(iop) 186 header_output += SeqOpDeclare.subst(iop) 187 decoder_output += SeqOpConstructor.subst(iop) 188 microopClasses["br"] = Br 189 190 iop = InstObjParams("eret", "EretFlags", "SeqOpBase", 191 {"code": "", "else_code": "", |
189 "cond_test": "checkCondition(ccFlagBits, cc)"}) | 192 "cond_test": "checkCondition(ccFlagBits, cc)", 193 "cond_control_flag_init": ""}) |
190 exec_output += SeqOpExecute.subst(iop) 191 header_output += SeqOpDeclare.subst(iop) 192 decoder_output += SeqOpConstructor.subst(iop) 193 iop = InstObjParams("eret", "Eret", "SeqOpBase", 194 {"code": "", "else_code": "", | 194 exec_output += SeqOpExecute.subst(iop) 195 header_output += SeqOpDeclare.subst(iop) 196 decoder_output += SeqOpConstructor.subst(iop) 197 iop = InstObjParams("eret", "Eret", "SeqOpBase", 198 {"code": "", "else_code": "", |
195 "cond_test": "true"}) | 199 "cond_test": "true", 200 "cond_control_flag_init": ""}) |
196 exec_output += SeqOpExecute.subst(iop) 197 header_output += SeqOpDeclare.subst(iop) 198 decoder_output += SeqOpConstructor.subst(iop) 199 microopClasses["eret"] = Eret 200}}; | 201 exec_output += SeqOpExecute.subst(iop) 202 header_output += SeqOpDeclare.subst(iop) 203 decoder_output += SeqOpConstructor.subst(iop) 204 microopClasses["eret"] = Eret 205}}; |