regop.isa (9211:46c3a74952ec) regop.isa (9212:dc386ccc1db9)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 424 unchanged lines hidden (view full) ---

433 "ext" : self.ext}
434 return allocator
435
436 class LogicRegOp(RegOp):
437 abstract = True
438 flag_code = '''
439 //Don't have genFlags handle the OF or CF bits
440 uint64_t mask = CFBit | ECFBit | OFBit;
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

--- 424 unchanged lines hidden (view full) ---

433 "ext" : self.ext}
434 return allocator
435
436 class LogicRegOp(RegOp):
437 abstract = True
438 flag_code = '''
439 //Don't have genFlags handle the OF or CF bits
440 uint64_t mask = CFBit | ECFBit | OFBit;
441 uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
442 ext & ~mask, result, psrc1, op2);
443 ezfBit = newFlags & EZFBit;
444 dfBit = newFlags & DFBit;
445 ccFlagBits = newFlags & ccFlagMask;
441 uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
442 PredezfBit, ext & ~mask, result, psrc1, op2);
443 PredezfBit = newFlags & EZFBit;
444 PreddfBit = newFlags & DFBit;
445 PredccFlagBits = newFlags & ccFlagMask;
446
447 //If a logic microop wants to set these, it wants to set them to 0.
446
447 //If a logic microop wants to set these, it wants to set them to 0.
448 cfofBits = cfofBits & ~((CFBit | OFBit) & ext);
449 ecfBit = ecfBit & ~(ECFBit & ext);
448 PredcfofBits = PredcfofBits & ~((CFBit | OFBit) & ext);
449 PredecfBit = PredecfBit & ~(ECFBit & ext);
450 '''
451
452 class FlagRegOp(RegOp):
453 abstract = True
454 flag_code = '''
450 '''
451
452 class FlagRegOp(RegOp):
453 abstract = True
454 flag_code = '''
455 uint64_t newFlags = genFlags(ccFlagBits | cfofBits | dfBit |
456 ecfBit | ezfBit, ext, result, psrc1, op2);
457 cfofBits = newFlags & cfofMask;
458 ecfBit = newFlags & ECFBit;
459 ezfBit = newFlags & EZFBit;
460 dfBit = newFlags & DFBit;
461 ccFlagBits = newFlags & ccFlagMask;
455 uint64_t newFlags = genFlags(PredccFlagBits | PredcfofBits |
456 PreddfBit | PredecfBit | PredezfBit,
457 ext, result, psrc1, op2);
458
459 PredcfofBits = newFlags & cfofMask;
460 PredecfBit = newFlags & ECFBit;
461 PredezfBit = newFlags & EZFBit;
462 PreddfBit = newFlags & DFBit;
463 PredccFlagBits = newFlags & ccFlagMask;
462 '''
463
464 class SubRegOp(RegOp):
465 abstract = True
466 flag_code = '''
464 '''
465
466 class SubRegOp(RegOp):
467 abstract = True
468 flag_code = '''
467 uint64_t newFlags = genFlags(ccFlagBits | cfofBits | dfBit |
468 ecfBit | ezfBit, ext, result, psrc1,
469 ~op2, true);
470 cfofBits = newFlags & cfofMask;
471 ecfBit = newFlags & ECFBit;
472 ezfBit = newFlags & EZFBit;
473 dfBit = newFlags & DFBit;
474 ccFlagBits = newFlags & ccFlagMask;
469 uint64_t newFlags = genFlags(PredccFlagBits | PredcfofBits |
470 PreddfBit | PredecfBit | PredezfBit,
471 ext, result, psrc1, ~op2, true);
472
473 PredcfofBits = newFlags & cfofMask;
474 PredecfBit = newFlags & ECFBit;
475 PredezfBit = newFlags & EZFBit;
476 PreddfBit = newFlags & DFBit;
477 PredccFlagBits = newFlags & ccFlagMask;
475 '''
476
477 class CondRegOp(RegOp):
478 abstract = True
479 cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | ecfBit | \
480 ezfBit, ext)"
481 cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];"
482

--- 68 unchanged lines hidden (view full) ---

551 hiResult -= op2;
552 if (bits(op2, dataSize * 8 - 1))
553 hiResult -= psrc1;
554 ProdHi = hiResult;
555 '''
556 flag_code = '''
557 if ((-ProdHi & mask(dataSize * 8)) !=
558 bits(ProdLow, dataSize * 8 - 1)) {
478 '''
479
480 class CondRegOp(RegOp):
481 abstract = True
482 cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | ecfBit | \
483 ezfBit, ext)"
484 cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];"
485

--- 68 unchanged lines hidden (view full) ---

554 hiResult -= op2;
555 if (bits(op2, dataSize * 8 - 1))
556 hiResult -= psrc1;
557 ProdHi = hiResult;
558 '''
559 flag_code = '''
560 if ((-ProdHi & mask(dataSize * 8)) !=
561 bits(ProdLow, dataSize * 8 - 1)) {
559 cfofBits = cfofBits | (ext & (CFBit | OFBit));
560 ecfBit = ecfBit | (ext & ECFBit);
562 PredcfofBits = PredcfofBits | (ext & (CFBit | OFBit));
563 PredecfBit = PredecfBit | (ext & ECFBit);
561 } else {
564 } else {
562 cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
563 ecfBit = ecfBit & ~(ext & ECFBit);
565 PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit));
566 PredecfBit = PredecfBit & ~(ext & ECFBit);
564 }
565 '''
566
567 class Mul1u(WrRegOp):
568 code = '''
569 ProdLow = psrc1 * op2;
570 int halfSize = (dataSize * 8) / 2;
571 uint64_t shifter = (ULL(1) << halfSize);
572 uint64_t psrc1_h = psrc1 / shifter;
573 uint64_t psrc1_l = psrc1 & mask(halfSize);
574 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
575 uint64_t psrc2_l = op2 & mask(halfSize);
576 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
577 ((psrc1_l * psrc2_l) / shifter)) / shifter) +
578 psrc1_h * psrc2_h;
579 '''
580 flag_code = '''
581 if (ProdHi) {
567 }
568 '''
569
570 class Mul1u(WrRegOp):
571 code = '''
572 ProdLow = psrc1 * op2;
573 int halfSize = (dataSize * 8) / 2;
574 uint64_t shifter = (ULL(1) << halfSize);
575 uint64_t psrc1_h = psrc1 / shifter;
576 uint64_t psrc1_l = psrc1 & mask(halfSize);
577 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
578 uint64_t psrc2_l = op2 & mask(halfSize);
579 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
580 ((psrc1_l * psrc2_l) / shifter)) / shifter) +
581 psrc1_h * psrc2_h;
582 '''
583 flag_code = '''
584 if (ProdHi) {
582 cfofBits = cfofBits | (ext & (CFBit | OFBit));
583 ecfBit = ecfBit | (ext & ECFBit);
585 PredcfofBits = PredcfofBits | (ext & (CFBit | OFBit));
586 PredecfBit = PredecfBit | (ext & ECFBit);
584 } else {
587 } else {
585 cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
586 ecfBit = ecfBit & ~(ext & ECFBit);
588 PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit));
589 PredecfBit = PredecfBit & ~(ext & ECFBit);
587 }
588 '''
589
590 class Mulel(RdRegOp):
591 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
592 big_code = 'DestReg = ProdLow & mask(dataSize * 8);'
593
594 class Muleh(RdRegOp):

--- 82 unchanged lines hidden (view full) ---

677 //Record the final results
678 Remainder = remainder;
679 Quotient = quotient;
680 '''
681 code = divCode % "DestReg = merge(DestReg, remaining, dataSize);"
682 big_code = divCode % "DestReg = remaining & mask(dataSize * 8);"
683 flag_code = '''
684 if (remaining == 0)
590 }
591 '''
592
593 class Mulel(RdRegOp):
594 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
595 big_code = 'DestReg = ProdLow & mask(dataSize * 8);'
596
597 class Muleh(RdRegOp):

--- 82 unchanged lines hidden (view full) ---

680 //Record the final results
681 Remainder = remainder;
682 Quotient = quotient;
683 '''
684 code = divCode % "DestReg = merge(DestReg, remaining, dataSize);"
685 big_code = divCode % "DestReg = remaining & mask(dataSize * 8);"
686 flag_code = '''
687 if (remaining == 0)
685 ezfBit = ezfBit | (ext & EZFBit);
688 PredezfBit = PredezfBit | (ext & EZFBit);
686 else
689 else
687 ezfBit = ezfBit & ~(ext & EZFBit);
690 PredezfBit = PredezfBit & ~(ext & EZFBit);
688 '''
689
690 class Divq(RdRegOp):
691 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
692 big_code = 'DestReg = Quotient & mask(dataSize * 8);'
693
694 class Divr(RdRegOp):
695 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'

--- 14 unchanged lines hidden (view full) ---

710 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
711 DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8);
712 '''
713 flag_code = '''
714 // If the shift amount is zero, no flags should be modified.
715 if (shiftAmt) {
716 //Zero out any flags we might modify. This way we only have to
717 //worry about setting them.
691 '''
692
693 class Divq(RdRegOp):
694 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
695 big_code = 'DestReg = Quotient & mask(dataSize * 8);'
696
697 class Divr(RdRegOp):
698 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'

--- 14 unchanged lines hidden (view full) ---

713 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
714 DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8);
715 '''
716 flag_code = '''
717 // If the shift amount is zero, no flags should be modified.
718 if (shiftAmt) {
719 //Zero out any flags we might modify. This way we only have to
720 //worry about setting them.
718 cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
719 ecfBit = ecfBit & ~(ext & ECFBit);
721 PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit));
722 PredecfBit = PredecfBit & ~(ext & ECFBit);
720
721 int CFBits = 0;
722 //Figure out if we -would- set the CF bits if requested.
723 if (shiftAmt <= dataSize * 8 &&
724 bits(SrcReg1, dataSize * 8 - shiftAmt)) {
725 CFBits = 1;
726 }
727
728 //If some combination of the CF bits need to be set, set them.
729 if ((ext & (CFBit | ECFBit)) && CFBits) {
723
724 int CFBits = 0;
725 //Figure out if we -would- set the CF bits if requested.
726 if (shiftAmt <= dataSize * 8 &&
727 bits(SrcReg1, dataSize * 8 - shiftAmt)) {
728 CFBits = 1;
729 }
730
731 //If some combination of the CF bits need to be set, set them.
732 if ((ext & (CFBit | ECFBit)) && CFBits) {
730 cfofBits = cfofBits | (ext & CFBit);
731 ecfBit = ecfBit | (ext & ECFBit);
733 PredcfofBits = PredcfofBits | (ext & CFBit);
734 PredecfBit = PredecfBit | (ext & ECFBit);
732 }
733
734 //Figure out what the OF bit should be.
735 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
735 }
736
737 //Figure out what the OF bit should be.
738 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
736 cfofBits = cfofBits | OFBit;
739 PredcfofBits = PredcfofBits | OFBit;
737
738 //Use the regular mechanisms to calculate the other flags.
740
741 //Use the regular mechanisms to calculate the other flags.
739 uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
740 ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
741 ezfBit = newFlags & EZFBit;
742 dfBit = newFlags & DFBit;
743 ccFlagBits = newFlags & ccFlagMask;
742 uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
743 PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
744 DestReg, psrc1, op2);
745
746 PredezfBit = newFlags & EZFBit;
747 PreddfBit = newFlags & DFBit;
748 PredccFlagBits = newFlags & ccFlagMask;
744 }
745 '''
746
747 class Srl(RegOp):
748 # Because what happens to the bits shift -in- on a right shift
749 # is not defined in the C/C++ standard, we have to mask them out
750 # to be sure they're zero.
751 code = '''

--- 6 unchanged lines hidden (view full) ---

758 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
759 DestReg = (psrc1 >> shiftAmt) & logicalMask;
760 '''
761 flag_code = '''
762 // If the shift amount is zero, no flags should be modified.
763 if (shiftAmt) {
764 //Zero out any flags we might modify. This way we only have to
765 //worry about setting them.
749 }
750 '''
751
752 class Srl(RegOp):
753 # Because what happens to the bits shift -in- on a right shift
754 # is not defined in the C/C++ standard, we have to mask them out
755 # to be sure they're zero.
756 code = '''

--- 6 unchanged lines hidden (view full) ---

763 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
764 DestReg = (psrc1 >> shiftAmt) & logicalMask;
765 '''
766 flag_code = '''
767 // If the shift amount is zero, no flags should be modified.
768 if (shiftAmt) {
769 //Zero out any flags we might modify. This way we only have to
770 //worry about setting them.
766 cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
767 ecfBit = ecfBit & ~(ext & ECFBit);
771 PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit));
772 PredecfBit = PredecfBit & ~(ext & ECFBit);
768
769 //If some combination of the CF bits need to be set, set them.
770 if ((ext & (CFBit | ECFBit)) &&
771 shiftAmt <= dataSize * 8 &&
772 bits(SrcReg1, shiftAmt - 1)) {
773
774 //If some combination of the CF bits need to be set, set them.
775 if ((ext & (CFBit | ECFBit)) &&
776 shiftAmt <= dataSize * 8 &&
777 bits(SrcReg1, shiftAmt - 1)) {
773 cfofBits = cfofBits | (ext & CFBit);
774 ecfBit = ecfBit | (ext & ECFBit);
778 PredcfofBits = PredcfofBits | (ext & CFBit);
779 PredecfBit = PredecfBit | (ext & ECFBit);
775 }
776
777 //Figure out what the OF bit should be.
778 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
780 }
781
782 //Figure out what the OF bit should be.
783 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
779 cfofBits = cfofBits | OFBit;
784 PredcfofBits = PredcfofBits | OFBit;
780
781 //Use the regular mechanisms to calculate the other flags.
785
786 //Use the regular mechanisms to calculate the other flags.
782 uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
783 ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
784 ezfBit = newFlags & EZFBit;
785 dfBit = newFlags & DFBit;
786 ccFlagBits = newFlags & ccFlagMask;
787 uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
788 PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
789 DestReg, psrc1, op2);
790
791 PredezfBit = newFlags & EZFBit;
792 PreddfBit = newFlags & DFBit;
793 PredccFlagBits = newFlags & ccFlagMask;
787 }
788 '''
789
790 class Sra(RegOp):
791 # Because what happens to the bits shift -in- on a right shift
792 # is not defined in the C/C++ standard, we have to sign extend
793 # them manually to be sure.
794 code = '''

--- 8 unchanged lines hidden (view full) ---

803 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
804 DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8);
805 '''
806 flag_code = '''
807 // If the shift amount is zero, no flags should be modified.
808 if (shiftAmt) {
809 //Zero out any flags we might modify. This way we only have to
810 //worry about setting them.
794 }
795 '''
796
797 class Sra(RegOp):
798 # Because what happens to the bits shift -in- on a right shift
799 # is not defined in the C/C++ standard, we have to sign extend
800 # them manually to be sure.
801 code = '''

--- 8 unchanged lines hidden (view full) ---

810 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
811 DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8);
812 '''
813 flag_code = '''
814 // If the shift amount is zero, no flags should be modified.
815 if (shiftAmt) {
816 //Zero out any flags we might modify. This way we only have to
817 //worry about setting them.
811 cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
812 ecfBit = ecfBit & ~(ext & ECFBit);
818 PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit));
819 PredecfBit = PredecfBit & ~(ext & ECFBit);
813
814 //If some combination of the CF bits need to be set, set them.
815 uint8_t effectiveShift =
816 (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8);
817 if ((ext & (CFBit | ECFBit)) &&
818 bits(SrcReg1, effectiveShift - 1)) {
820
821 //If some combination of the CF bits need to be set, set them.
822 uint8_t effectiveShift =
823 (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8);
824 if ((ext & (CFBit | ECFBit)) &&
825 bits(SrcReg1, effectiveShift - 1)) {
819 cfofBits = cfofBits | (ext & CFBit);
820 ecfBit = ecfBit | (ext & ECFBit);
826 PredcfofBits = PredcfofBits | (ext & CFBit);
827 PredecfBit = PredecfBit | (ext & ECFBit);
821 }
822
823 //Use the regular mechanisms to calculate the other flags.
828 }
829
830 //Use the regular mechanisms to calculate the other flags.
824 uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
825 ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
826 ezfBit = newFlags & EZFBit;
827 dfBit = newFlags & DFBit;
828 ccFlagBits = newFlags & ccFlagMask;
831 uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
832 PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
833 DestReg, psrc1, op2);
834
835 PredezfBit = newFlags & EZFBit;
836 PreddfBit = newFlags & DFBit;
837 PredccFlagBits = newFlags & ccFlagMask;
829 }
830 '''
831
832 class Ror(RegOp):
833 code = '''
834 uint8_t shiftAmt =
835 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
836 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);

--- 4 unchanged lines hidden (view full) ---

841 } else
842 DestReg = merge(DestReg, DestReg, dataSize);
843 '''
844 flag_code = '''
845 // If the shift amount is zero, no flags should be modified.
846 if (shiftAmt) {
847 //Zero out any flags we might modify. This way we only have to
848 //worry about setting them.
838 }
839 '''
840
841 class Ror(RegOp):
842 code = '''
843 uint8_t shiftAmt =
844 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
845 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);

--- 4 unchanged lines hidden (view full) ---

850 } else
851 DestReg = merge(DestReg, DestReg, dataSize);
852 '''
853 flag_code = '''
854 // If the shift amount is zero, no flags should be modified.
855 if (shiftAmt) {
856 //Zero out any flags we might modify. This way we only have to
857 //worry about setting them.
849 cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
850 ecfBit = ecfBit & ~(ext & ECFBit);
858 PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit));
859 PredecfBit = PredecfBit & ~(ext & ECFBit);
851
852 //Find the most and second most significant bits of the result.
853 int msb = bits(DestReg, dataSize * 8 - 1);
854 int smsb = bits(DestReg, dataSize * 8 - 2);
855 //If some combination of the CF bits need to be set, set them.
856 if ((ext & (CFBit | ECFBit)) && msb) {
860
861 //Find the most and second most significant bits of the result.
862 int msb = bits(DestReg, dataSize * 8 - 1);
863 int smsb = bits(DestReg, dataSize * 8 - 2);
864 //If some combination of the CF bits need to be set, set them.
865 if ((ext & (CFBit | ECFBit)) && msb) {
857 cfofBits = cfofBits | (ext & CFBit);
858 ecfBit = ecfBit | (ext & ECFBit);
866 PredcfofBits = PredcfofBits | (ext & CFBit);
867 PredecfBit = PredecfBit | (ext & ECFBit);
859 }
860
861 //Figure out what the OF bit should be.
862 if ((ext & OFBit) && (msb ^ smsb))
868 }
869
870 //Figure out what the OF bit should be.
871 if ((ext & OFBit) && (msb ^ smsb))
863 cfofBits = cfofBits | OFBit;
872 PredcfofBits = PredcfofBits | OFBit;
864
865 //Use the regular mechanisms to calculate the other flags.
873
874 //Use the regular mechanisms to calculate the other flags.
866 uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
867 ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
868 ezfBit = newFlags & EZFBit;
869 dfBit = newFlags & DFBit;
870 ccFlagBits = newFlags & ccFlagMask;
875 uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
876 PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
877 DestReg, psrc1, op2);
878
879 PredezfBit = newFlags & EZFBit;
880 PreddfBit = newFlags & DFBit;
881 PredccFlagBits = newFlags & ccFlagMask;
871 }
872 '''
873
874 class Rcr(RegOp):
875 code = '''
876 uint8_t shiftAmt =
877 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
878 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);

--- 8 unchanged lines hidden (view full) ---

887 DestReg = merge(DestReg, DestReg, dataSize);
888 '''
889 flag_code = '''
890 // If the shift amount is zero, no flags should be modified.
891 if (shiftAmt) {
892 int origCFBit = (cfofBits & CFBit) ? 1 : 0;
893 //Zero out any flags we might modify. This way we only have to
894 //worry about setting them.
882 }
883 '''
884
885 class Rcr(RegOp):
886 code = '''
887 uint8_t shiftAmt =
888 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
889 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);

--- 8 unchanged lines hidden (view full) ---

898 DestReg = merge(DestReg, DestReg, dataSize);
899 '''
900 flag_code = '''
901 // If the shift amount is zero, no flags should be modified.
902 if (shiftAmt) {
903 int origCFBit = (cfofBits & CFBit) ? 1 : 0;
904 //Zero out any flags we might modify. This way we only have to
905 //worry about setting them.
895 cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
896 ecfBit = ecfBit & ~(ext & ECFBit);
906 PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit));
907 PredecfBit = PredecfBit & ~(ext & ECFBit);
897
898 //Figure out what the OF bit should be.
899 if ((ext & OFBit) && (origCFBit ^
900 bits(SrcReg1, dataSize * 8 - 1))) {
908
909 //Figure out what the OF bit should be.
910 if ((ext & OFBit) && (origCFBit ^
911 bits(SrcReg1, dataSize * 8 - 1))) {
901 cfofBits = cfofBits | OFBit;
912 PredcfofBits = PredcfofBits | OFBit;
902 }
903 //If some combination of the CF bits need to be set, set them.
904 if ((ext & (CFBit | ECFBit)) &&
905 (realShiftAmt == 0) ? origCFBit :
906 bits(SrcReg1, realShiftAmt - 1)) {
913 }
914 //If some combination of the CF bits need to be set, set them.
915 if ((ext & (CFBit | ECFBit)) &&
916 (realShiftAmt == 0) ? origCFBit :
917 bits(SrcReg1, realShiftAmt - 1)) {
907 cfofBits = cfofBits | (ext & CFBit);
908 ecfBit = ecfBit | (ext & ECFBit);
918 PredcfofBits = PredcfofBits | (ext & CFBit);
919 PredecfBit = PredecfBit | (ext & ECFBit);
909 }
910
911 //Use the regular mechanisms to calculate the other flags.
920 }
921
922 //Use the regular mechanisms to calculate the other flags.
912 uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
913 ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
914 ezfBit = newFlags & EZFBit;
915 dfBit = newFlags & DFBit;
916 ccFlagBits = newFlags & ccFlagMask;
923 uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
924 PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
925 DestReg, psrc1, op2);
926
927 PredezfBit = newFlags & EZFBit;
928 PreddfBit = newFlags & DFBit;
929 PredccFlagBits = newFlags & ccFlagMask;
917 }
918 '''
919
920 class Rol(RegOp):
921 code = '''
922 uint8_t shiftAmt =
923 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
924 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);

--- 5 unchanged lines hidden (view full) ---

930 } else
931 DestReg = merge(DestReg, DestReg, dataSize);
932 '''
933 flag_code = '''
934 // If the shift amount is zero, no flags should be modified.
935 if (shiftAmt) {
936 //Zero out any flags we might modify. This way we only have to
937 //worry about setting them.
930 }
931 '''
932
933 class Rol(RegOp):
934 code = '''
935 uint8_t shiftAmt =
936 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
937 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);

--- 5 unchanged lines hidden (view full) ---

943 } else
944 DestReg = merge(DestReg, DestReg, dataSize);
945 '''
946 flag_code = '''
947 // If the shift amount is zero, no flags should be modified.
948 if (shiftAmt) {
949 //Zero out any flags we might modify. This way we only have to
950 //worry about setting them.
938 cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
939 ecfBit = ecfBit & ~(ext & ECFBit);
951 PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit));
952 PredecfBit = PredecfBit & ~(ext & ECFBit);
940
941 //The CF bits, if set, would be set to the lsb of the result.
942 int lsb = DestReg & 0x1;
943 int msb = bits(DestReg, dataSize * 8 - 1);
944 //If some combination of the CF bits need to be set, set them.
945 if ((ext & (CFBit | ECFBit)) && lsb) {
953
954 //The CF bits, if set, would be set to the lsb of the result.
955 int lsb = DestReg & 0x1;
956 int msb = bits(DestReg, dataSize * 8 - 1);
957 //If some combination of the CF bits need to be set, set them.
958 if ((ext & (CFBit | ECFBit)) && lsb) {
946 cfofBits = cfofBits | (ext & CFBit);
947 ecfBit = ecfBit | (ext & ECFBit);
959 PredcfofBits = PredcfofBits | (ext & CFBit);
960 PredecfBit = PredecfBit | (ext & ECFBit);
948 }
949
950 //Figure out what the OF bit should be.
951 if ((ext & OFBit) && (msb ^ lsb))
961 }
962
963 //Figure out what the OF bit should be.
964 if ((ext & OFBit) && (msb ^ lsb))
952 cfofBits = cfofBits | OFBit;
965 PredcfofBits = PredcfofBits | OFBit;
953
954 //Use the regular mechanisms to calculate the other flags.
966
967 //Use the regular mechanisms to calculate the other flags.
955 uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
956 ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
957 ezfBit = newFlags & EZFBit;
958 dfBit = newFlags & DFBit;
959 ccFlagBits = newFlags & ccFlagMask;
968 uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
969 PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
970 DestReg, psrc1, op2);
971
972 PredezfBit = newFlags & EZFBit;
973 PreddfBit = newFlags & DFBit;
974 PredccFlagBits = newFlags & ccFlagMask;
960 }
961 '''
962
963 class Rcl(RegOp):
964 code = '''
965 uint8_t shiftAmt =
966 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
967 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);

--- 10 unchanged lines hidden (view full) ---

978 DestReg = merge(DestReg, DestReg, dataSize);
979 '''
980 flag_code = '''
981 // If the shift amount is zero, no flags should be modified.
982 if (shiftAmt) {
983 int origCFBit = (cfofBits & CFBit) ? 1 : 0;
984 //Zero out any flags we might modify. This way we only have to
985 //worry about setting them.
975 }
976 '''
977
978 class Rcl(RegOp):
979 code = '''
980 uint8_t shiftAmt =
981 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
982 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);

--- 10 unchanged lines hidden (view full) ---

993 DestReg = merge(DestReg, DestReg, dataSize);
994 '''
995 flag_code = '''
996 // If the shift amount is zero, no flags should be modified.
997 if (shiftAmt) {
998 int origCFBit = (cfofBits & CFBit) ? 1 : 0;
999 //Zero out any flags we might modify. This way we only have to
1000 //worry about setting them.
986 cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
987 ecfBit = ecfBit & ~(ext & ECFBit);
1001 PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit));
1002 PredecfBit = PredecfBit & ~(ext & ECFBit);
988
989 int msb = bits(DestReg, dataSize * 8 - 1);
990 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt);
991 //If some combination of the CF bits need to be set, set them.
992 if ((ext & (CFBit | ECFBit)) &&
993 (realShiftAmt == 0) ? origCFBit : CFBits) {
1003
1004 int msb = bits(DestReg, dataSize * 8 - 1);
1005 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt);
1006 //If some combination of the CF bits need to be set, set them.
1007 if ((ext & (CFBit | ECFBit)) &&
1008 (realShiftAmt == 0) ? origCFBit : CFBits) {
994 cfofBits = cfofBits | (ext & CFBit);
995 ecfBit = ecfBit | (ext & ECFBit);
1009 PredcfofBits = PredcfofBits | (ext & CFBit);
1010 PredecfBit = PredecfBit | (ext & ECFBit);
996 }
997
998 //Figure out what the OF bit should be.
999 if ((ext & OFBit) && (msb ^ CFBits))
1011 }
1012
1013 //Figure out what the OF bit should be.
1014 if ((ext & OFBit) && (msb ^ CFBits))
1000 cfofBits = cfofBits | OFBit;
1015 PredcfofBits = PredcfofBits | OFBit;
1001
1002 //Use the regular mechanisms to calculate the other flags.
1016
1017 //Use the regular mechanisms to calculate the other flags.
1003 uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
1004 ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
1005 ezfBit = newFlags & EZFBit;
1006 dfBit = newFlags & DFBit;
1007 ccFlagBits = newFlags & ccFlagMask;
1018 uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
1019 PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
1020 DestReg, psrc1, op2);
1021
1022 PredezfBit = newFlags & EZFBit;
1023 PreddfBit = newFlags & DFBit;
1024 PredccFlagBits = newFlags & ccFlagMask;
1008 }
1009 '''
1010
1011 class Sld(RegOp):
1012 sldCode = '''
1013 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
1014 uint8_t dataBits = dataSize * 8;
1015 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);

--- 11 unchanged lines hidden (view full) ---

1027 '''
1028 code = sldCode % "DestReg = merge(DestReg, result, dataSize);"
1029 big_code = sldCode % "DestReg = result & mask(dataSize * 8);"
1030 flag_code = '''
1031 // If the shift amount is zero, no flags should be modified.
1032 if (shiftAmt) {
1033 //Zero out any flags we might modify. This way we only have to
1034 //worry about setting them.
1025 }
1026 '''
1027
1028 class Sld(RegOp):
1029 sldCode = '''
1030 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
1031 uint8_t dataBits = dataSize * 8;
1032 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);

--- 11 unchanged lines hidden (view full) ---

1044 '''
1045 code = sldCode % "DestReg = merge(DestReg, result, dataSize);"
1046 big_code = sldCode % "DestReg = result & mask(dataSize * 8);"
1047 flag_code = '''
1048 // If the shift amount is zero, no flags should be modified.
1049 if (shiftAmt) {
1050 //Zero out any flags we might modify. This way we only have to
1051 //worry about setting them.
1035 cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
1036 ecfBit = ecfBit & ~(ext & ECFBit);
1052 PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit));
1053 PredecfBit = PredecfBit & ~(ext & ECFBit);
1037 int CFBits = 0;
1038
1039 //Figure out if we -would- set the CF bits if requested.
1040 if ((realShiftAmt == 0 &&
1041 bits(DoubleBits, 0)) ||
1042 (realShiftAmt <= dataBits &&
1043 bits(SrcReg1, dataBits - realShiftAmt)) ||
1044 (realShiftAmt > dataBits &&
1045 bits(DoubleBits, 2 * dataBits - realShiftAmt))) {
1046 CFBits = 1;
1047 }
1048
1049 //If some combination of the CF bits need to be set, set them.
1050 if ((ext & (CFBit | ECFBit)) && CFBits) {
1054 int CFBits = 0;
1055
1056 //Figure out if we -would- set the CF bits if requested.
1057 if ((realShiftAmt == 0 &&
1058 bits(DoubleBits, 0)) ||
1059 (realShiftAmt <= dataBits &&
1060 bits(SrcReg1, dataBits - realShiftAmt)) ||
1061 (realShiftAmt > dataBits &&
1062 bits(DoubleBits, 2 * dataBits - realShiftAmt))) {
1063 CFBits = 1;
1064 }
1065
1066 //If some combination of the CF bits need to be set, set them.
1067 if ((ext & (CFBit | ECFBit)) && CFBits) {
1051 cfofBits = cfofBits | (ext & CFBit);
1052 ecfBit = ecfBit | (ext & ECFBit);
1068 PredcfofBits = PredcfofBits | (ext & CFBit);
1069 PredecfBit = PredecfBit | (ext & ECFBit);
1053 }
1054
1055 //Figure out what the OF bit should be.
1056 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
1057 bits(result, dataBits - 1)))
1070 }
1071
1072 //Figure out what the OF bit should be.
1073 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
1074 bits(result, dataBits - 1)))
1058 cfofBits = cfofBits | OFBit;
1075 PredcfofBits = PredcfofBits | OFBit;
1059
1060 //Use the regular mechanisms to calculate the other flags.
1076
1077 //Use the regular mechanisms to calculate the other flags.
1061 uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
1062 ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
1063 ezfBit = newFlags & EZFBit;
1064 dfBit = newFlags & DFBit;
1065 ccFlagBits = newFlags & ccFlagMask;
1078 uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
1079 PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
1080 DestReg, psrc1, op2);
1081
1082 PredezfBit = newFlags & EZFBit;
1083 PreddfBit = newFlags & DFBit;
1084 PredccFlagBits = newFlags & ccFlagMask;
1066 }
1067 '''
1068
1069 class Srd(RegOp):
1070 srdCode = '''
1071 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
1072 uint8_t dataBits = dataSize * 8;
1073 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);

--- 17 unchanged lines hidden (view full) ---

1091 '''
1092 code = srdCode % "DestReg = merge(DestReg, result, dataSize);"
1093 big_code = srdCode % "DestReg = result & mask(dataSize * 8);"
1094 flag_code = '''
1095 // If the shift amount is zero, no flags should be modified.
1096 if (shiftAmt) {
1097 //Zero out any flags we might modify. This way we only have to
1098 //worry about setting them.
1085 }
1086 '''
1087
1088 class Srd(RegOp):
1089 srdCode = '''
1090 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
1091 uint8_t dataBits = dataSize * 8;
1092 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);

--- 17 unchanged lines hidden (view full) ---

1110 '''
1111 code = srdCode % "DestReg = merge(DestReg, result, dataSize);"
1112 big_code = srdCode % "DestReg = result & mask(dataSize * 8);"
1113 flag_code = '''
1114 // If the shift amount is zero, no flags should be modified.
1115 if (shiftAmt) {
1116 //Zero out any flags we might modify. This way we only have to
1117 //worry about setting them.
1099 cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
1100 ecfBit = ecfBit & ~(ext & ECFBit);
1118 PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit));
1119 PredecfBit = PredecfBit & ~(ext & ECFBit);
1101 int CFBits = 0;
1102
1103 //If some combination of the CF bits need to be set, set them.
1104 if ((realShiftAmt == 0 &&
1105 bits(DoubleBits, dataBits - 1)) ||
1106 (realShiftAmt <= dataBits &&
1107 bits(SrcReg1, realShiftAmt - 1)) ||
1108 (realShiftAmt > dataBits &&
1109 bits(DoubleBits, realShiftAmt - dataBits - 1))) {
1110 CFBits = 1;
1111 }
1112
1113 //If some combination of the CF bits need to be set, set them.
1114 if ((ext & (CFBit | ECFBit)) && CFBits) {
1120 int CFBits = 0;
1121
1122 //If some combination of the CF bits need to be set, set them.
1123 if ((realShiftAmt == 0 &&
1124 bits(DoubleBits, dataBits - 1)) ||
1125 (realShiftAmt <= dataBits &&
1126 bits(SrcReg1, realShiftAmt - 1)) ||
1127 (realShiftAmt > dataBits &&
1128 bits(DoubleBits, realShiftAmt - dataBits - 1))) {
1129 CFBits = 1;
1130 }
1131
1132 //If some combination of the CF bits need to be set, set them.
1133 if ((ext & (CFBit | ECFBit)) && CFBits) {
1115 cfofBits = cfofBits | (ext & CFBit);
1116 ecfBit = ecfBit | (ext & ECFBit);
1134 PredcfofBits = PredcfofBits | (ext & CFBit);
1135 PredecfBit = PredecfBit | (ext & ECFBit);
1117 }
1118
1119 //Figure out what the OF bit should be.
1120 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
1121 bits(result, dataBits - 1)))
1136 }
1137
1138 //Figure out what the OF bit should be.
1139 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
1140 bits(result, dataBits - 1)))
1122 cfofBits = cfofBits | OFBit;
1141 PredcfofBits = PredcfofBits | OFBit;
1123
1124 //Use the regular mechanisms to calculate the other flags.
1142
1143 //Use the regular mechanisms to calculate the other flags.
1125 uint64_t newFlags = genFlags(ccFlagBits | dfBit | ezfBit,
1126 ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
1127 ezfBit = newFlags & EZFBit;
1128 dfBit = newFlags & DFBit;
1129 ccFlagBits = newFlags & ccFlagMask;
1144 uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
1145 PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
1146 DestReg, psrc1, op2);
1147
1148 PredezfBit = newFlags & EZFBit;
1149 PreddfBit = newFlags & DFBit;
1150 PredccFlagBits = newFlags & ccFlagMask;
1130 }
1131 '''
1132
1133 class Mdb(WrRegOp):
1134 code = 'DoubleBits = psrc1 ^ op2;'
1135
1136 class Wrip(WrRegOp, CondRegOp):
1137 code = 'NRIP = psrc1 + sop2 + CSBase;'

--- 101 unchanged lines hidden (view full) ---

1239 int sign_bit = bits(val, bitPos, bitPos);
1240 uint64_t maskVal = mask(bitPos+1);
1241 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1242 DestReg = val & mask(dataSize * 8);
1243 '''
1244
1245 flag_code = '''
1246 if (!sign_bit) {
1151 }
1152 '''
1153
1154 class Mdb(WrRegOp):
1155 code = 'DoubleBits = psrc1 ^ op2;'
1156
1157 class Wrip(WrRegOp, CondRegOp):
1158 code = 'NRIP = psrc1 + sop2 + CSBase;'

--- 101 unchanged lines hidden (view full) ---

1260 int sign_bit = bits(val, bitPos, bitPos);
1261 uint64_t maskVal = mask(bitPos+1);
1262 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1263 DestReg = val & mask(dataSize * 8);
1264 '''
1265
1266 flag_code = '''
1267 if (!sign_bit) {
1247 ccFlagBits = ccFlagBits & ~(ext & (ZFBit));
1248 cfofBits = cfofBits & ~(ext & (CFBit));
1249 ecfBit = ecfBit & ~(ext & ECFBit);
1250 ezfBit = ezfBit & ~(ext & EZFBit);
1268 PredccFlagBits = PredccFlagBits & ~(ext & (ZFBit));
1269 PredcfofBits = PredcfofBits & ~(ext & (CFBit));
1270 PredecfBit = PredecfBit & ~(ext & ECFBit);
1271 PredezfBit = PredezfBit & ~(ext & EZFBit);
1251 } else {
1272 } else {
1252 ccFlagBits = ccFlagBits | (ext & (ZFBit));
1253 cfofBits = cfofBits | (ext & (CFBit));
1254 ecfBit = ecfBit | (ext & ECFBit);
1255 ezfBit = ezfBit | (ext & EZFBit);
1273 PredccFlagBits = PredccFlagBits | (ext & (ZFBit));
1274 PredcfofBits = PredcfofBits | (ext & (CFBit));
1275 PredecfBit = PredecfBit | (ext & ECFBit);
1276 PredezfBit = PredezfBit | (ext & EZFBit);
1256 }
1257 '''
1258
1259 class Zext(RegOp):
1260 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
1261 big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);'
1262
1263 class Rddr(RegOp):

--- 266 unchanged lines hidden (view full) ---

1530 break;
1531 default:
1532 fault = new GenericISA::M5PanicFault(
1533 "Undefined segment check type.\\n");
1534 }
1535 '''
1536 flag_code = '''
1537 // Check for a NULL selector and set ZF,EZF appropriately.
1277 }
1278 '''
1279
1280 class Zext(RegOp):
1281 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
1282 big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);'
1283
1284 class Rddr(RegOp):

--- 266 unchanged lines hidden (view full) ---

1551 break;
1552 default:
1553 fault = new GenericISA::M5PanicFault(
1554 "Undefined segment check type.\\n");
1555 }
1556 '''
1557 flag_code = '''
1558 // Check for a NULL selector and set ZF,EZF appropriately.
1538 ccFlagBits = ccFlagBits & ~(ext & ZFBit);
1539 ezfBit = ezfBit & ~(ext & EZFBit);
1559 PredccFlagBits = PredccFlagBits & ~(ext & ZFBit);
1560 PredezfBit = PredezfBit & ~(ext & EZFBit);
1540
1541 if (!selector.si && !selector.ti) {
1561
1562 if (!selector.si && !selector.ti) {
1542 ccFlagBits = ccFlagBits | (ext & ZFBit);
1543 ezfBit = ezfBit | (ext & EZFBit);
1563 PredccFlagBits = PredccFlagBits | (ext & ZFBit);
1564 PredezfBit = PredezfBit | (ext & EZFBit);
1544 }
1545 '''
1546
1547 class Wrdh(RegOp):
1548 code = '''
1549 SegDescriptor desc = SrcReg1;
1550
1551 uint64_t target = bits(SrcReg2, 31, 0) << 32;

--- 96 unchanged lines hidden --- 		1565 }
1566 '''
1567
1568 class Wrdh(RegOp):
1569 code = '''
1570 SegDescriptor desc = SrcReg1;
1571
1572 uint64_t target = bits(SrcReg2, 31, 0) << 32;

--- 96 unchanged lines hidden ---