regop.isa (8626:19eed0015983) regop.isa (8857:120adc5a4345)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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1220 }
1221 break;
1222 case 8:
1223 {
1224 if (bits(newVal, 63, 4))
1225 fault = new GeneralProtection(0);
1226 }
1227 default:
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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1220 }
1221 break;
1222 case 8:
1223 {
1224 if (bits(newVal, 63, 4))
1225 fault = new GeneralProtection(0);
1226 }
1227 default:
1228 panic("Unrecognized control register %d.\\n", dest);
1228 fault = new GenericISA::M5PanicFault(
1229 "Unrecognized control register %d.\\n", dest);
1229 }
1230 ControlDest = newVal;
1231 }
1232 '''
1233
1234 # Microops for manipulating segmentation registers
1235 class SegOp(CondRegOp):
1236 abstract = True

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1309 // Make sure it's the right type
1310 if (desc.s == 0 || desc.type.codeOrData != 1) {
1311 fault = new GeneralProtection(0);
1312 } else if (m5reg.cpl != desc.dpl) {
1313 fault = new GeneralProtection(0);
1314 }
1315 break;
1316 case SegCallGateCheck:
1230 }
1231 ControlDest = newVal;
1232 }
1233 '''
1234
1235 # Microops for manipulating segmentation registers
1236 class SegOp(CondRegOp):
1237 abstract = True

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1310 // Make sure it's the right type
1311 if (desc.s == 0 || desc.type.codeOrData != 1) {
1312 fault = new GeneralProtection(0);
1313 } else if (m5reg.cpl != desc.dpl) {
1314 fault = new GeneralProtection(0);
1315 }
1316 break;
1317 case SegCallGateCheck:
1317 panic("CS checks for far calls/jumps through call gates"
1318 "not implemented.\\n");
1318 fault = new GenericISA::M5PanicFault("CS checks for far "
1319 "calls/jumps through call gates not implemented.\\n");
1319 break;
1320 case SegSoftIntGateCheck:
1321 // Check permissions.
1322 if (desc.dpl < m5reg.cpl) {
1323 fault = new GeneralProtection(selector);
1324 break;
1325 }
1326 // Fall through on purpose

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1360 break;
1361 }
1362 case SegIntCSCheck:
1363 if (m5reg.mode == LongMode) {
1364 if (desc.l != 1 || desc.d != 0) {
1365 fault = new GeneralProtection(selector);
1366 }
1367 } else {
1320 break;
1321 case SegSoftIntGateCheck:
1322 // Check permissions.
1323 if (desc.dpl < m5reg.cpl) {
1324 fault = new GeneralProtection(selector);
1325 break;
1326 }
1327 // Fall through on purpose

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1361 break;
1362 }
1363 case SegIntCSCheck:
1364 if (m5reg.mode == LongMode) {
1365 if (desc.l != 1 || desc.d != 0) {
1366 fault = new GeneralProtection(selector);
1367 }
1368 } else {
1368 panic("Interrupt CS checks not implemented "
1369 "in legacy mode.\\n");
1369 fault = new GenericISA::M5PanicFault("Interrupt CS "
1370 "checks not implemented in legacy mode.\\n");
1370 }
1371 break;
1372 case SegTRCheck:
1373 if (!selector.si || selector.ti) {
1374 fault = new GeneralProtection(selector);
1375 }
1376 break;
1377 case SegTSSCheck:

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1391 case SegLDTCheck:
1392 if (!desc.p) {
1393 fault = new SegmentNotPresent(selector);
1394 } else if (desc.type != 0x2) {
1395 fault = new GeneralProtection(selector);
1396 }
1397 break;
1398 default:
1371 }
1372 break;
1373 case SegTRCheck:
1374 if (!selector.si || selector.ti) {
1375 fault = new GeneralProtection(selector);
1376 }
1377 break;
1378 case SegTSSCheck:

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1392 case SegLDTCheck:
1393 if (!desc.p) {
1394 fault = new SegmentNotPresent(selector);
1395 } else if (desc.type != 0x2) {
1396 fault = new GeneralProtection(selector);
1397 }
1398 break;
1399 default:
1399 panic("Undefined segment check type.\\n");
1400 fault = new GenericISA::M5PanicFault(
1401 "Undefined segment check type.\\n");
1400 }
1401 '''
1402 flag_code = '''
1403 // Check for a NULL selector and set ZF,EZF appropriately.
1404 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit));
1405 if (!selector.si && !selector.ti)
1406 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit));
1407 '''

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1420 break;
1421 case CallGate64:
1422 case IntGate64:
1423 case TrapGate64:
1424 replaceBits(target, 15, 0, bits(desc, 15, 0));
1425 replaceBits(target, 31, 16, bits(desc, 63, 48));
1426 break;
1427 default:
1402 }
1403 '''
1404 flag_code = '''
1405 // Check for a NULL selector and set ZF,EZF appropriately.
1406 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit));
1407 if (!selector.si && !selector.ti)
1408 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit));
1409 '''

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1422 break;
1423 case CallGate64:
1424 case IntGate64:
1425 case TrapGate64:
1426 replaceBits(target, 15, 0, bits(desc, 15, 0));
1427 replaceBits(target, 31, 16, bits(desc, 63, 48));
1428 break;
1429 default:
1428 panic("Wrdh used with wrong descriptor type!\\n");
1430 fault = new GenericISA::M5PanicFault(
1431 "Wrdh used with wrong descriptor type!\\n");
1429 }
1430 DestReg = target;
1431 '''
1432
1433 class Wrtsc(WrRegOp):
1434 code = '''
1435 TscOp = psrc1;
1436 '''

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1444 code = '''
1445 DestReg = M5Reg;
1446 '''
1447
1448 class Wrdl(RegOp):
1449 code = '''
1450 SegDescriptor desc = SrcReg1;
1451 SegSelector selector = SrcReg2;
1432 }
1433 DestReg = target;
1434 '''
1435
1436 class Wrtsc(WrRegOp):
1437 code = '''
1438 TscOp = psrc1;
1439 '''

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1447 code = '''
1448 DestReg = M5Reg;
1449 '''
1450
1451 class Wrdl(RegOp):
1452 code = '''
1453 SegDescriptor desc = SrcReg1;
1454 SegSelector selector = SrcReg2;
1452 if (selector.si || selector.ti) {
1453 if (!desc.p)
1454 panic("Segment not present.\\n");
1455 SegAttr attr = 0;
1456 attr.dpl = desc.dpl;
1457 attr.unusable = 0;
1458 attr.defaultSize = desc.d;
1459 attr.longMode = desc.l;
1460 attr.avl = desc.avl;
1461 attr.granularity = desc.g;
1462 attr.present = desc.p;
1463 attr.system = desc.s;
1464 attr.type = desc.type;
1465 if (!desc.s) {
1466 // The expand down bit happens to be set for gates.
1467 if (desc.type.e) {
1468 panic("Gate descriptor encountered.\\n");
1455 // This while loop is so we can use break statements in the code
1456 // below to skip the rest of this section without a bunch of
1457 // nesting.
1458 while (true) {
1459 if (selector.si || selector.ti) {
1460 if (!desc.p) {
1461 fault = new GenericISA::M5PanicFault(
1462 "Segment not present.\\n");
1463 break;
1469 }
1464 }
1470 attr.readable = 1;
1471 attr.writable = 1;
1472 attr.expandDown = 0;
1473 } else {
1474 if (desc.type.codeOrData) {
1465 SegAttr attr = 0;
1466 attr.dpl = desc.dpl;
1467 attr.unusable = 0;
1468 attr.defaultSize = desc.d;
1469 attr.longMode = desc.l;
1470 attr.avl = desc.avl;
1471 attr.granularity = desc.g;
1472 attr.present = desc.p;
1473 attr.system = desc.s;
1474 attr.type = desc.type;
1475 if (!desc.s) {
1476 // The expand down bit happens to be set for gates.
1477 if (desc.type.e) {
1478 fault = new GenericISA::M5PanicFault(
1479 "Gate descriptor encountered.\\n");
1480 break;
1481 }
1482 attr.readable = 1;
1483 attr.writable = 1;
1475 attr.expandDown = 0;
1484 attr.expandDown = 0;
1476 attr.readable = desc.type.r;
1477 attr.writable = 0;
1478 } else {
1485 } else {
1479 attr.expandDown = desc.type.e;
1480 attr.readable = 1;
1481 attr.writable = desc.type.w;
1486 if (desc.type.codeOrData) {
1487 attr.expandDown = 0;
1488 attr.readable = desc.type.r;
1489 attr.writable = 0;
1490 } else {
1491 attr.expandDown = desc.type.e;
1492 attr.readable = 1;
1493 attr.writable = desc.type.w;
1494 }
1482 }
1495 }
1496 Addr base = desc.baseLow | (desc.baseHigh << 24);
1497 Addr limit = desc.limitLow | (desc.limitHigh << 16);
1498 if (desc.g)
1499 limit = (limit << 12) | mask(12);
1500 SegBaseDest = base;
1501 SegLimitDest = limit;
1502 SegAttrDest = attr;
1503 } else {
1504 SegBaseDest = SegBaseDest;
1505 SegLimitDest = SegLimitDest;
1506 SegAttrDest = SegAttrDest;
1483 }
1507 }
1484 Addr base = desc.baseLow | (desc.baseHigh << 24);
1485 Addr limit = desc.limitLow | (desc.limitHigh << 16);
1486 if (desc.g)
1487 limit = (limit << 12) | mask(12);
1488 SegBaseDest = base;
1489 SegLimitDest = limit;
1490 SegAttrDest = attr;
1491 } else {
1492 SegBaseDest = SegBaseDest;
1493 SegLimitDest = SegLimitDest;
1494 SegAttrDest = SegAttrDest;
1508 break;
1495 }
1496 '''
1497}};
1509 }
1510 '''
1511}};