regop.isa (7967:b243dc8cec8b) regop.isa (7969:068f061e57a8)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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46 Trace::InstRecord *traceData) const
47 {
48 Fault fault = NoFault;
49
50 DPRINTF(X86, "The data size is %d\n", dataSize);
51 %(op_decl)s;
52 %(op_rd)s;
53
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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46 Trace::InstRecord *traceData) const
47 {
48 Fault fault = NoFault;
49
50 DPRINTF(X86, "The data size is %d\n", dataSize);
51 %(op_decl)s;
52 %(op_rd)s;
53
54 IntReg result M5_VAR_USED;
55
54 if(%(cond_check)s)
55 {
56 %(code)s;
57 %(flag_code)s;
58 }
59 else
60 {
61 %(else_code)s;

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74 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
75 Trace::InstRecord *traceData) const
76 {
77 Fault fault = NoFault;
78
79 %(op_decl)s;
80 %(op_rd)s;
81
56 if(%(cond_check)s)
57 {
58 %(code)s;
59 %(flag_code)s;
60 }
61 else
62 {
63 %(else_code)s;

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76 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
77 Trace::InstRecord *traceData) const
78 {
79 Fault fault = NoFault;
80
81 %(op_decl)s;
82 %(op_rd)s;
83
84 IntReg result M5_VAR_USED;
85
82 if(%(cond_check)s)
83 {
84 %(code)s;
85 %(flag_code)s;
86 }
87 else
88 {
89 %(else_code)s;

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429 "ext" : self.ext}
430 return allocator
431
432 class LogicRegOp(RegOp):
433 abstract = True
434 flag_code = '''
435 //Don't have genFlags handle the OF or CF bits
436 uint64_t mask = CFBit | ECFBit | OFBit;
86 if(%(cond_check)s)
87 {
88 %(code)s;
89 %(flag_code)s;
90 }
91 else
92 {
93 %(else_code)s;

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433 "ext" : self.ext}
434 return allocator
435
436 class LogicRegOp(RegOp):
437 abstract = True
438 flag_code = '''
439 //Don't have genFlags handle the OF or CF bits
440 uint64_t mask = CFBit | ECFBit | OFBit;
437 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
441 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, result, psrc1, op2);
438 //If a logic microop wants to set these, it wants to set them to 0.
439 ccFlagBits &= ~(CFBit & ext);
440 ccFlagBits &= ~(ECFBit & ext);
441 ccFlagBits &= ~(OFBit & ext);
442 '''
443
444 class FlagRegOp(RegOp):
445 abstract = True
446 flag_code = \
442 //If a logic microop wants to set these, it wants to set them to 0.
443 ccFlagBits &= ~(CFBit & ext);
444 ccFlagBits &= ~(ECFBit & ext);
445 ccFlagBits &= ~(OFBit & ext);
446 '''
447
448 class FlagRegOp(RegOp):
449 abstract = True
450 flag_code = \
447 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
451 "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);"
448
449 class SubRegOp(RegOp):
450 abstract = True
451 flag_code = \
452
453 class SubRegOp(RegOp):
454 abstract = True
455 flag_code = \
452 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
456 "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);"
453
454 class CondRegOp(RegOp):
455 abstract = True
456 cond_check = "checkCondition(ccFlagBits, ext)"
457 cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];"
458
459 class RdRegOp(RegOp):
460 abstract = True

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466
467 class WrRegOp(RegOp):
468 abstract = True
469 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
470 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
471 src1, src2, flags, dataSize)
472
473 class Add(FlagRegOp):
457
458 class CondRegOp(RegOp):
459 abstract = True
460 cond_check = "checkCondition(ccFlagBits, ext)"
461 cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];"
462
463 class RdRegOp(RegOp):
464 abstract = True

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470
471 class WrRegOp(RegOp):
472 abstract = True
473 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
474 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
475 src1, src2, flags, dataSize)
476
477 class Add(FlagRegOp):
474 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
475 big_code = 'DestReg = (psrc1 + op2) & mask(dataSize * 8);'
478 code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);'
479 big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);'
476
477 class Or(LogicRegOp):
480
481 class Or(LogicRegOp):
478 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
479 big_code = 'DestReg = (psrc1 | op2) & mask(dataSize * 8);'
482 code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);'
483 big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);'
480
481 class Adc(FlagRegOp):
482 code = '''
483 CCFlagBits flags = ccFlagBits;
484
485 class Adc(FlagRegOp):
486 code = '''
487 CCFlagBits flags = ccFlagBits;
484 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
488 DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize);
485 '''
486 big_code = '''
487 CCFlagBits flags = ccFlagBits;
489 '''
490 big_code = '''
491 CCFlagBits flags = ccFlagBits;
488 DestReg = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
492 DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
489 '''
490
491 class Sbb(SubRegOp):
492 code = '''
493 CCFlagBits flags = ccFlagBits;
493 '''
494
495 class Sbb(SubRegOp):
496 code = '''
497 CCFlagBits flags = ccFlagBits;
494 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
498 DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize);
495 '''
496 big_code = '''
497 CCFlagBits flags = ccFlagBits;
499 '''
500 big_code = '''
501 CCFlagBits flags = ccFlagBits;
498 DestReg = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
502 DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
499 '''
500
501 class And(LogicRegOp):
503 '''
504
505 class And(LogicRegOp):
502 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
503 big_code = 'DestReg = (psrc1 & op2) & mask(dataSize * 8)'
506 code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)'
507 big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)'
504
505 class Sub(SubRegOp):
508
509 class Sub(SubRegOp):
506 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
507 big_code = 'DestReg = (psrc1 - op2) & mask(dataSize * 8)'
510 code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)'
511 big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)'
508
509 class Xor(LogicRegOp):
512
513 class Xor(LogicRegOp):
510 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
511 big_code = 'DestReg = (psrc1 ^ op2) & mask(dataSize * 8)'
514 code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)'
515 big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)'
512
513 class Mul1s(WrRegOp):
514 code = '''
515 ProdLow = psrc1 * op2;
516 int halfSize = (dataSize * 8) / 2;
517 uint64_t shifter = (ULL(1) << halfSize);
518 uint64_t hiResult;
519 uint64_t psrc1_h = psrc1 / shifter;

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517 class Mul1s(WrRegOp):
518 code = '''
519 ProdLow = psrc1 * op2;
520 int halfSize = (dataSize * 8) / 2;
521 uint64_t shifter = (ULL(1) << halfSize);
522 uint64_t hiResult;
523 uint64_t psrc1_h = psrc1 / shifter;

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