regop.isa (7894:48d31b577847) regop.isa (7967:b243dc8cec8b)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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219 MicroRegOpImmExecute)
220
221 regTemplates = (
222 MicroRegOpDeclare,
223 MicroRegOpConstructor,
224 MicroRegOpExecute)
225
226 class RegOpMeta(type):
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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219 MicroRegOpImmExecute)
220
221 regTemplates = (
222 MicroRegOpDeclare,
223 MicroRegOpConstructor,
224 MicroRegOpExecute)
225
226 class RegOpMeta(type):
227 def buildCppClasses(self, name, Name, suffix, \
228 code, flag_code, cond_check, else_code, cond_control_flag_init):
227 def buildCppClasses(self, name, Name, suffix, code, big_code, \
228 flag_code, cond_check, else_code, cond_control_flag_init):
229
230 # Globals to stick the output in
231 global header_output
232 global decoder_output
233 global exec_output
234
235 # Stick all the code together so it can be searched at once
236 allCode = "|".join((code, flag_code, cond_check, else_code,
237 cond_control_flag_init))
229
230 # Globals to stick the output in
231 global header_output
232 global decoder_output
233 global exec_output
234
235 # Stick all the code together so it can be searched at once
236 allCode = "|".join((code, flag_code, cond_check, else_code,
237 cond_control_flag_init))
238 allBigCode = "|".join((big_code, flag_code, cond_check, else_code,
239 cond_control_flag_init))
238
239 # If op2 is used anywhere, make register and immediate versions
240 # of this code.
241 matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?")
240
241 # If op2 is used anywhere, make register and immediate versions
242 # of this code.
243 matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?")
242 match = matcher.search(allCode)
244 match = matcher.search(allCode + allBigCode)
243 if match:
244 typeQual = ""
245 if match.group("typeQual"):
246 typeQual = match.group("typeQual")
247 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
248 self.buildCppClasses(name, Name, suffix,
249 matcher.sub(src2_name, code),
245 if match:
246 typeQual = ""
247 if match.group("typeQual"):
248 typeQual = match.group("typeQual")
249 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
250 self.buildCppClasses(name, Name, suffix,
251 matcher.sub(src2_name, code),
252 matcher.sub(src2_name, big_code),
250 matcher.sub(src2_name, flag_code),
251 matcher.sub(src2_name, cond_check),
252 matcher.sub(src2_name, else_code),
253 matcher.sub(src2_name, cond_control_flag_init))
254 imm_name = "%simm8" % match.group("prefix")
255 self.buildCppClasses(name + "i", Name, suffix + "Imm",
256 matcher.sub(imm_name, code),
253 matcher.sub(src2_name, flag_code),
254 matcher.sub(src2_name, cond_check),
255 matcher.sub(src2_name, else_code),
256 matcher.sub(src2_name, cond_control_flag_init))
257 imm_name = "%simm8" % match.group("prefix")
258 self.buildCppClasses(name + "i", Name, suffix + "Imm",
259 matcher.sub(imm_name, code),
260 matcher.sub(imm_name, big_code),
257 matcher.sub(imm_name, flag_code),
258 matcher.sub(imm_name, cond_check),
259 matcher.sub(imm_name, else_code),
260 matcher.sub(imm_name, cond_control_flag_init))
261 return
262
263 # If there's something optional to do with flags, generate
264 # a version without it and fix up this version to use it.
265 if flag_code != "" or cond_check != "true":
266 self.buildCppClasses(name, Name, suffix,
261 matcher.sub(imm_name, flag_code),
262 matcher.sub(imm_name, cond_check),
263 matcher.sub(imm_name, else_code),
264 matcher.sub(imm_name, cond_control_flag_init))
265 return
266
267 # If there's something optional to do with flags, generate
268 # a version without it and fix up this version to use it.
269 if flag_code != "" or cond_check != "true":
270 self.buildCppClasses(name, Name, suffix,
267 code, "", "true", else_code, "")
271 code, big_code, "", "true", else_code, "")
268 suffix = "Flags" + suffix
269
270 # If psrc1 or psrc2 is used, we need to actually insert code to
271 # compute it.
272 suffix = "Flags" + suffix
273
274 # If psrc1 or psrc2 is used, we need to actually insert code to
275 # compute it.
272 matcher = re.compile("(?<!\w)psrc1(?!\w)")
273 if matcher.search(allCode):
274 code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code
275 matcher = re.compile("(?<!\w)psrc2(?!\w)")
276 if matcher.search(allCode):
277 code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code
278 # Also make available versions which do sign extension
279 matcher = re.compile("(?<!\w)spsrc1(?!\w)")
280 if matcher.search(allCode):
281 code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code
282 matcher = re.compile("(?<!\w)spsrc2(?!\w)")
283 if matcher.search(allCode):
284 code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
285 matcher = re.compile("(?<!\w)simm8(?!\w)")
286 if matcher.search(allCode):
287 code = "int8_t simm8 = imm8;" + code
276 for (big, all) in ((False, allCode), (True, allBigCode)):
277 prefix = ""
278 for (rex, decl) in (
279 ("(?<!\w)psrc1(?!\w)",
280 "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"),
281 ("(?<!\w)psrc2(?!\w)",
282 "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"),
283 ("(?<!\w)spsrc1(?!\w)",
284 "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"),
285 ("(?<!\w)spsrc2(?!\w)",
286 "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"),
287 ("(?<!\w)simm8(?!\w)",
288 "int8_t simm8 = imm8;")):
289 matcher = re.compile(rex)
290 if matcher.search(all):
291 prefix += decl + "\n"
292 if big:
293 if big_code != "":
294 big_code = prefix + big_code
295 else:
296 code = prefix + code
288
289 base = "X86ISA::RegOp"
290
291 # If imm8 shows up in the code, use the immediate templates, if
292 # not, hopefully the register ones will be correct.
293 templates = regTemplates
294 matcher = re.compile("(?<!\w)s?imm8(?!\w)")
295 if matcher.search(allCode):
296 base += "Imm"
297 templates = immTemplates
298
299 # Get everything ready for the substitution
297
298 base = "X86ISA::RegOp"
299
300 # If imm8 shows up in the code, use the immediate templates, if
301 # not, hopefully the register ones will be correct.
302 templates = regTemplates
303 matcher = re.compile("(?<!\w)s?imm8(?!\w)")
304 if matcher.search(allCode):
305 base += "Imm"
306 templates = immTemplates
307
308 # Get everything ready for the substitution
300 iop = InstObjParams(name, Name + suffix, base,
309 iops = [InstObjParams(name, Name + suffix, base,
301 {"code" : code,
302 "flag_code" : flag_code,
303 "cond_check" : cond_check,
304 "else_code" : else_code,
310 {"code" : code,
311 "flag_code" : flag_code,
312 "cond_check" : cond_check,
313 "else_code" : else_code,
305 "cond_control_flag_init": cond_control_flag_init})
314 "cond_control_flag_init" : cond_control_flag_init})]
315 if big_code != "":
316 iops += [InstObjParams(name, Name + suffix + "Big", base,
317 {"code" : big_code,
318 "flag_code" : flag_code,
319 "cond_check" : cond_check,
320 "else_code" : else_code,
321 "cond_control_flag_init" :
322 cond_control_flag_init})]
306
307 # Generate the actual code (finally!)
323
324 # Generate the actual code (finally!)
308 header_output += templates[0].subst(iop)
309 decoder_output += templates[1].subst(iop)
310 exec_output += templates[2].subst(iop)
325 for iop in iops:
326 header_output += templates[0].subst(iop)
327 decoder_output += templates[1].subst(iop)
328 exec_output += templates[2].subst(iop)
311
312
313 def __new__(mcls, Name, bases, dict):
314 abstract = False
315 name = Name.lower()
316 if "abstract" in dict:
317 abstract = dict['abstract']
318 del dict['abstract']
319
320 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
321 if not abstract:
322 cls.className = Name
323 cls.base_mnemonic = name
324 code = cls.code
329
330
331 def __new__(mcls, Name, bases, dict):
332 abstract = False
333 name = Name.lower()
334 if "abstract" in dict:
335 abstract = dict['abstract']
336 del dict['abstract']
337
338 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
339 if not abstract:
340 cls.className = Name
341 cls.base_mnemonic = name
342 code = cls.code
343 big_code = cls.big_code
325 flag_code = cls.flag_code
326 cond_check = cls.cond_check
327 else_code = cls.else_code
328 cond_control_flag_init = cls.cond_control_flag_init
329
330 # Set up the C++ classes
344 flag_code = cls.flag_code
345 cond_check = cls.cond_check
346 else_code = cls.else_code
347 cond_control_flag_init = cls.cond_control_flag_init
348
349 # Set up the C++ classes
331 mcls.buildCppClasses(cls, name, Name, "", code, flag_code,
332 cond_check, else_code, cond_control_flag_init)
350 mcls.buildCppClasses(cls, name, Name, "", code, big_code,
351 flag_code, cond_check, else_code,
352 cond_control_flag_init)
333
334 # Hook into the microassembler dict
335 global microopClasses
336 microopClasses[name] = cls
337
338 allCode = "|".join((code, flag_code, cond_check, else_code,
339 cond_control_flag_init))
340

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347
348
349 class RegOp(X86Microop):
350 __metaclass__ = RegOpMeta
351 # This class itself doesn't act as a microop
352 abstract = True
353
354 # Default template parameter values
353
354 # Hook into the microassembler dict
355 global microopClasses
356 microopClasses[name] = cls
357
358 allCode = "|".join((code, flag_code, cond_check, else_code,
359 cond_control_flag_init))
360

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367
368
369 class RegOp(X86Microop):
370 __metaclass__ = RegOpMeta
371 # This class itself doesn't act as a microop
372 abstract = True
373
374 # Default template parameter values
375 big_code = ""
355 flag_code = ""
356 cond_check = "true"
357 else_code = ";"
358 cond_control_flag_init = ""
359
360 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
361 self.dest = dest
362 self.src1 = src1

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367 self.ext = 0
368 else:
369 if not isinstance(flags, (list, tuple)):
370 raise Exception, "flags must be a list or tuple of flags"
371 self.ext = " | ".join(flags)
372 self.className += "Flags"
373
374 def getAllocator(self, microFlags):
376 flag_code = ""
377 cond_check = "true"
378 else_code = ";"
379 cond_control_flag_init = ""
380
381 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
382 self.dest = dest
383 self.src1 = src1

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388 self.ext = 0
389 else:
390 if not isinstance(flags, (list, tuple)):
391 raise Exception, "flags must be a list or tuple of flags"
392 self.ext = " | ".join(flags)
393 self.className += "Flags"
394
395 def getAllocator(self, microFlags):
375 className = self.className
376 if self.mnemonic == self.base_mnemonic + 'i':
377 className += "Imm"
378 allocator = '''new %(class_name)s(machInst, macrocodeBlock,
379 %(flags)s, %(src1)s, %(op2)s, %(dest)s,
380 %(dataSize)s, %(ext)s)''' % {
381 "class_name" : className,
382 "flags" : self.microFlagsText(microFlags),
383 "src1" : self.src1, "op2" : self.op2,
384 "dest" : self.dest,
385 "dataSize" : self.dataSize,
386 "ext" : self.ext}
387 return allocator
396 if self.big_code != "":
397 className = self.className
398 if self.mnemonic == self.base_mnemonic + 'i':
399 className += "Imm"
400 allocString = '''
401 (%(dataSize)s >= 4) ?
402 (StaticInstPtr)(new %(class_name)sBig(machInst,
403 macrocodeBlock, %(flags)s, %(src1)s, %(op2)s,
404 %(dest)s, %(dataSize)s, %(ext)s)) :
405 (StaticInstPtr)(new %(class_name)s(machInst,
406 macrocodeBlock, %(flags)s, %(src1)s, %(op2)s,
407 %(dest)s, %(dataSize)s, %(ext)s))
408 '''
409 allocator = allocString % {
410 "class_name" : className,
411 "flags" : self.microFlagsText(microFlags),
412 "src1" : self.src1, "op2" : self.op2,
413 "dest" : self.dest,
414 "dataSize" : self.dataSize,
415 "ext" : self.ext}
416 return allocator
417 else:
418 className = self.className
419 if self.mnemonic == self.base_mnemonic + 'i':
420 className += "Imm"
421 allocator = '''new %(class_name)s(machInst, macrocodeBlock,
422 %(flags)s, %(src1)s, %(op2)s, %(dest)s,
423 %(dataSize)s, %(ext)s)''' % {
424 "class_name" : className,
425 "flags" : self.microFlagsText(microFlags),
426 "src1" : self.src1, "op2" : self.op2,
427 "dest" : self.dest,
428 "dataSize" : self.dataSize,
429 "ext" : self.ext}
430 return allocator
388
389 class LogicRegOp(RegOp):
390 abstract = True
391 flag_code = '''
392 //Don't have genFlags handle the OF or CF bits
393 uint64_t mask = CFBit | ECFBit | OFBit;
394 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
395 //If a logic microop wants to set these, it wants to set them to 0.

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424 class WrRegOp(RegOp):
425 abstract = True
426 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
427 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
428 src1, src2, flags, dataSize)
429
430 class Add(FlagRegOp):
431 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
431
432 class LogicRegOp(RegOp):
433 abstract = True
434 flag_code = '''
435 //Don't have genFlags handle the OF or CF bits
436 uint64_t mask = CFBit | ECFBit | OFBit;
437 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
438 //If a logic microop wants to set these, it wants to set them to 0.

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467 class WrRegOp(RegOp):
468 abstract = True
469 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
470 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
471 src1, src2, flags, dataSize)
472
473 class Add(FlagRegOp):
474 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
475 big_code = 'DestReg = (psrc1 + op2) & mask(dataSize * 8);'
432
433 class Or(LogicRegOp):
434 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
476
477 class Or(LogicRegOp):
478 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
479 big_code = 'DestReg = (psrc1 | op2) & mask(dataSize * 8);'
435
436 class Adc(FlagRegOp):
437 code = '''
438 CCFlagBits flags = ccFlagBits;
439 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
440 '''
480
481 class Adc(FlagRegOp):
482 code = '''
483 CCFlagBits flags = ccFlagBits;
484 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
485 '''
486 big_code = '''
487 CCFlagBits flags = ccFlagBits;
488 DestReg = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
489 '''
441
442 class Sbb(SubRegOp):
443 code = '''
444 CCFlagBits flags = ccFlagBits;
445 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
446 '''
490
491 class Sbb(SubRegOp):
492 code = '''
493 CCFlagBits flags = ccFlagBits;
494 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
495 '''
496 big_code = '''
497 CCFlagBits flags = ccFlagBits;
498 DestReg = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
499 '''
447
448 class And(LogicRegOp):
449 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
500
501 class And(LogicRegOp):
502 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
503 big_code = 'DestReg = (psrc1 & op2) & mask(dataSize * 8)'
450
451 class Sub(SubRegOp):
452 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
504
505 class Sub(SubRegOp):
506 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
507 big_code = 'DestReg = (psrc1 - op2) & mask(dataSize * 8)'
453
454 class Xor(LogicRegOp):
455 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
508
509 class Xor(LogicRegOp):
510 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
511 big_code = 'DestReg = (psrc1 ^ op2) & mask(dataSize * 8)'
456
457 class Mul1s(WrRegOp):
458 code = '''
459 ProdLow = psrc1 * op2;
460 int halfSize = (dataSize * 8) / 2;
461 uint64_t shifter = (ULL(1) << halfSize);
462 uint64_t hiResult;
463 uint64_t psrc1_h = psrc1 / shifter;

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500 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
501 } else {
502 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
503 }
504 '''
505
506 class Mulel(RdRegOp):
507 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
512
513 class Mul1s(WrRegOp):
514 code = '''
515 ProdLow = psrc1 * op2;
516 int halfSize = (dataSize * 8) / 2;
517 uint64_t shifter = (ULL(1) << halfSize);
518 uint64_t hiResult;
519 uint64_t psrc1_h = psrc1 / shifter;

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556 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
557 } else {
558 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
559 }
560 '''
561
562 class Mulel(RdRegOp):
563 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
564 big_code = 'DestReg = ProdLow & mask(dataSize * 8);'
508
509 class Muleh(RdRegOp):
510 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
511 if not src1:
512 src1 = dest
513 super(RdRegOp, self).__init__(dest, src1, \
514 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
515 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
565
566 class Muleh(RdRegOp):
567 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
568 if not src1:
569 src1 = dest
570 super(RdRegOp, self).__init__(dest, src1, \
571 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
572 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
573 big_code = 'DestReg = ProdHi & mask(dataSize * 8);'
516
517 # One or two bit divide
518 class Div1(WrRegOp):
519 code = '''
520 //These are temporaries so that modifying them later won't make
521 //the ISA parser think they're also sources.
522 uint64_t quotient = 0;
523 uint64_t remainder = psrc1;

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535 Remainder = remainder;
536 Quotient = quotient;
537 Divisor = divisor;
538 }
539 '''
540
541 # Step divide
542 class Div2(RegOp):
574
575 # One or two bit divide
576 class Div1(WrRegOp):
577 code = '''
578 //These are temporaries so that modifying them later won't make
579 //the ISA parser think they're also sources.
580 uint64_t quotient = 0;
581 uint64_t remainder = psrc1;

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593 Remainder = remainder;
594 Quotient = quotient;
595 Divisor = divisor;
596 }
597 '''
598
599 # Step divide
600 class Div2(RegOp):
543 code = '''
601 divCode = '''
544 uint64_t dividend = Remainder;
545 uint64_t divisor = Divisor;
546 uint64_t quotient = Quotient;
547 uint64_t remainder = dividend;
548 int remaining = op2;
549 //If we overshot, do nothing. This lets us unrool division loops a
550 //little.
551 if (divisor == 0) {

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582 remaining--;
583 }
584 remainder = dividend;
585 //Do the division.
586 divide(dividend, divisor, quotient, remainder);
587 }
588 }
589 //Keep track of how many bits there are still to pull in.
602 uint64_t dividend = Remainder;
603 uint64_t divisor = Divisor;
604 uint64_t quotient = Quotient;
605 uint64_t remainder = dividend;
606 int remaining = op2;
607 //If we overshot, do nothing. This lets us unrool division loops a
608 //little.
609 if (divisor == 0) {

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640 remaining--;
641 }
642 remainder = dividend;
643 //Do the division.
644 divide(dividend, divisor, quotient, remainder);
645 }
646 }
647 //Keep track of how many bits there are still to pull in.
590 DestReg = merge(DestReg, remaining, dataSize);
648 %s
591 //Record the final results
592 Remainder = remainder;
593 Quotient = quotient;
594 '''
649 //Record the final results
650 Remainder = remainder;
651 Quotient = quotient;
652 '''
653 code = divCode % "DestReg = merge(DestReg, remaining, dataSize);"
654 big_code = divCode % "DestReg = remaining & mask(dataSize * 8);"
595 flag_code = '''
596 if (remaining == 0)
597 ccFlagBits = ccFlagBits | (ext & EZFBit);
598 else
599 ccFlagBits = ccFlagBits & ~(ext & EZFBit);
600 '''
601
602 class Divq(RdRegOp):
603 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
655 flag_code = '''
656 if (remaining == 0)
657 ccFlagBits = ccFlagBits | (ext & EZFBit);
658 else
659 ccFlagBits = ccFlagBits & ~(ext & EZFBit);
660 '''
661
662 class Divq(RdRegOp):
663 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
664 big_code = 'DestReg = Quotient & mask(dataSize * 8);'
604
605 class Divr(RdRegOp):
606 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
665
666 class Divr(RdRegOp):
667 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
668 big_code = 'DestReg = Remainder & mask(dataSize * 8);'
607
608 class Mov(CondRegOp):
609 code = 'DestReg = merge(SrcReg1, op2, dataSize)'
610 else_code = 'DestReg = DestReg;'
611
612 # Shift instructions
613
614 class Sll(RegOp):
615 code = '''
616 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
617 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
618 '''
669
670 class Mov(CondRegOp):
671 code = 'DestReg = merge(SrcReg1, op2, dataSize)'
672 else_code = 'DestReg = DestReg;'
673
674 # Shift instructions
675
676 class Sll(RegOp):
677 code = '''
678 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
679 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
680 '''
681 big_code = '''
682 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
683 DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8);
684 '''
619 flag_code = '''
620 // If the shift amount is zero, no flags should be modified.
621 if (shiftAmt) {
622 //Zero out any flags we might modify. This way we only have to
623 //worry about setting them.
624 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
625 int CFBits = 0;
626 //Figure out if we -would- set the CF bits if requested.

--- 9 unchanged lines hidden (view full) ---

636 ccFlagBits = ccFlagBits | OFBit;
637 //Use the regular mechanisms to calculate the other flags.
638 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
639 DestReg, psrc1, op2);
640 }
641 '''
642
643 class Srl(RegOp):
685 flag_code = '''
686 // If the shift amount is zero, no flags should be modified.
687 if (shiftAmt) {
688 //Zero out any flags we might modify. This way we only have to
689 //worry about setting them.
690 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
691 int CFBits = 0;
692 //Figure out if we -would- set the CF bits if requested.

--- 9 unchanged lines hidden (view full) ---

702 ccFlagBits = ccFlagBits | OFBit;
703 //Use the regular mechanisms to calculate the other flags.
704 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
705 DestReg, psrc1, op2);
706 }
707 '''
708
709 class Srl(RegOp):
710 # Because what happens to the bits shift -in- on a right shift
711 # is not defined in the C/C++ standard, we have to mask them out
712 # to be sure they're zero.
644 code = '''
645 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
713 code = '''
714 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
646 // Because what happens to the bits shift -in- on a right shift
647 // is not defined in the C/C++ standard, we have to mask them out
648 // to be sure they're zero.
649 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
650 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
651 '''
715 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
716 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
717 '''
718 big_code = '''
719 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
720 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
721 DestReg = (psrc1 >> shiftAmt) & logicalMask;
722 '''
652 flag_code = '''
653 // If the shift amount is zero, no flags should be modified.
654 if (shiftAmt) {
655 //Zero out any flags we might modify. This way we only have to
656 //worry about setting them.
657 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
658 //If some combination of the CF bits need to be set, set them.
659 if ((ext & (CFBit | ECFBit)) &&

--- 6 unchanged lines hidden (view full) ---

666 ccFlagBits = ccFlagBits | OFBit;
667 //Use the regular mechanisms to calculate the other flags.
668 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
669 DestReg, psrc1, op2);
670 }
671 '''
672
673 class Sra(RegOp):
723 flag_code = '''
724 // If the shift amount is zero, no flags should be modified.
725 if (shiftAmt) {
726 //Zero out any flags we might modify. This way we only have to
727 //worry about setting them.
728 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
729 //If some combination of the CF bits need to be set, set them.
730 if ((ext & (CFBit | ECFBit)) &&

--- 6 unchanged lines hidden (view full) ---

737 ccFlagBits = ccFlagBits | OFBit;
738 //Use the regular mechanisms to calculate the other flags.
739 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
740 DestReg, psrc1, op2);
741 }
742 '''
743
744 class Sra(RegOp):
745 # Because what happens to the bits shift -in- on a right shift
746 # is not defined in the C/C++ standard, we have to sign extend
747 # them manually to be sure.
674 code = '''
675 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
748 code = '''
749 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
676 // Because what happens to the bits shift -in- on a right shift
677 // is not defined in the C/C++ standard, we have to sign extend
678 // them manually to be sure.
679 uint64_t arithMask = (shiftAmt == 0) ? 0 :
680 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
681 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
682 '''
750 uint64_t arithMask = (shiftAmt == 0) ? 0 :
751 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
752 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
753 '''
754 big_code = '''
755 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
756 uint64_t arithMask = (shiftAmt == 0) ? 0 :
757 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
758 DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8);
759 '''
683 flag_code = '''
684 // If the shift amount is zero, no flags should be modified.
685 if (shiftAmt) {
686 //Zero out any flags we might modify. This way we only have to
687 //worry about setting them.
688 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
689 //If some combination of the CF bits need to be set, set them.
690 uint8_t effectiveShift =

--- 8 unchanged lines hidden (view full) ---

699 }
700 '''
701
702 class Ror(RegOp):
703 code = '''
704 uint8_t shiftAmt =
705 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
706 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
760 flag_code = '''
761 // If the shift amount is zero, no flags should be modified.
762 if (shiftAmt) {
763 //Zero out any flags we might modify. This way we only have to
764 //worry about setting them.
765 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
766 //If some combination of the CF bits need to be set, set them.
767 uint8_t effectiveShift =

--- 8 unchanged lines hidden (view full) ---

776 }
777 '''
778
779 class Ror(RegOp):
780 code = '''
781 uint8_t shiftAmt =
782 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
783 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
707 if(realShiftAmt)
708 {
784 if (realShiftAmt) {
709 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt);
710 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt);
711 DestReg = merge(DestReg, top | bottom, dataSize);
785 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt);
786 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt);
787 DestReg = merge(DestReg, top | bottom, dataSize);
712 }
713 else
788 } else
714 DestReg = merge(DestReg, DestReg, dataSize);
715 '''
716 flag_code = '''
717 // If the shift amount is zero, no flags should be modified.
718 if (shiftAmt) {
719 //Zero out any flags we might modify. This way we only have to
720 //worry about setting them.
721 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));

--- 12 unchanged lines hidden (view full) ---

734 }
735 '''
736
737 class Rcr(RegOp):
738 code = '''
739 uint8_t shiftAmt =
740 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
741 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
789 DestReg = merge(DestReg, DestReg, dataSize);
790 '''
791 flag_code = '''
792 // If the shift amount is zero, no flags should be modified.
793 if (shiftAmt) {
794 //Zero out any flags we might modify. This way we only have to
795 //worry about setting them.
796 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));

--- 12 unchanged lines hidden (view full) ---

809 }
810 '''
811
812 class Rcr(RegOp):
813 code = '''
814 uint8_t shiftAmt =
815 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
816 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
742 if(realShiftAmt)
743 {
817 if (realShiftAmt) {
744 CCFlagBits flags = ccFlagBits;
745 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt);
746 if (realShiftAmt > 1)
747 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1);
748 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt);
749 DestReg = merge(DestReg, top | bottom, dataSize);
818 CCFlagBits flags = ccFlagBits;
819 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt);
820 if (realShiftAmt > 1)
821 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1);
822 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt);
823 DestReg = merge(DestReg, top | bottom, dataSize);
750 }
751 else
824 } else
752 DestReg = merge(DestReg, DestReg, dataSize);
753 '''
754 flag_code = '''
755 // If the shift amount is zero, no flags should be modified.
756 if (shiftAmt) {
757 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
758 //Zero out any flags we might modify. This way we only have to
759 //worry about setting them.

--- 15 unchanged lines hidden (view full) ---

775 }
776 '''
777
778 class Rol(RegOp):
779 code = '''
780 uint8_t shiftAmt =
781 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
782 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
825 DestReg = merge(DestReg, DestReg, dataSize);
826 '''
827 flag_code = '''
828 // If the shift amount is zero, no flags should be modified.
829 if (shiftAmt) {
830 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
831 //Zero out any flags we might modify. This way we only have to
832 //worry about setting them.

--- 15 unchanged lines hidden (view full) ---

848 }
849 '''
850
851 class Rol(RegOp):
852 code = '''
853 uint8_t shiftAmt =
854 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
855 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
783 if(realShiftAmt)
784 {
856 if (realShiftAmt) {
785 uint64_t top = psrc1 << realShiftAmt;
786 uint64_t bottom =
787 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt);
788 DestReg = merge(DestReg, top | bottom, dataSize);
857 uint64_t top = psrc1 << realShiftAmt;
858 uint64_t bottom =
859 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt);
860 DestReg = merge(DestReg, top | bottom, dataSize);
789 }
790 else
861 } else
791 DestReg = merge(DestReg, DestReg, dataSize);
792 '''
793 flag_code = '''
794 // If the shift amount is zero, no flags should be modified.
795 if (shiftAmt) {
796 //Zero out any flags we might modify. This way we only have to
797 //worry about setting them.
798 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));

--- 12 unchanged lines hidden (view full) ---

811 }
812 '''
813
814 class Rcl(RegOp):
815 code = '''
816 uint8_t shiftAmt =
817 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
818 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
862 DestReg = merge(DestReg, DestReg, dataSize);
863 '''
864 flag_code = '''
865 // If the shift amount is zero, no flags should be modified.
866 if (shiftAmt) {
867 //Zero out any flags we might modify. This way we only have to
868 //worry about setting them.
869 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));

--- 12 unchanged lines hidden (view full) ---

882 }
883 '''
884
885 class Rcl(RegOp):
886 code = '''
887 uint8_t shiftAmt =
888 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
889 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
819 if(realShiftAmt)
820 {
890 if (realShiftAmt) {
821 CCFlagBits flags = ccFlagBits;
822 uint64_t top = psrc1 << realShiftAmt;
823 uint64_t bottom = flags.cf << (realShiftAmt - 1);
824 if(shiftAmt > 1)
825 bottom |=
826 bits(psrc1, dataSize * 8 - 1,
827 dataSize * 8 - realShiftAmt + 1);
828 DestReg = merge(DestReg, top | bottom, dataSize);
891 CCFlagBits flags = ccFlagBits;
892 uint64_t top = psrc1 << realShiftAmt;
893 uint64_t bottom = flags.cf << (realShiftAmt - 1);
894 if(shiftAmt > 1)
895 bottom |=
896 bits(psrc1, dataSize * 8 - 1,
897 dataSize * 8 - realShiftAmt + 1);
898 DestReg = merge(DestReg, top | bottom, dataSize);
829 }
830 else
899 } else
831 DestReg = merge(DestReg, DestReg, dataSize);
832 '''
833 flag_code = '''
834 // If the shift amount is zero, no flags should be modified.
835 if (shiftAmt) {
836 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
837 //Zero out any flags we might modify. This way we only have to
838 //worry about setting them.

--- 9 unchanged lines hidden (view full) ---

848 ccFlagBits = ccFlagBits | OFBit;
849 //Use the regular mechanisms to calculate the other flags.
850 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
851 DestReg, psrc1, op2);
852 }
853 '''
854
855 class Sld(RegOp):
900 DestReg = merge(DestReg, DestReg, dataSize);
901 '''
902 flag_code = '''
903 // If the shift amount is zero, no flags should be modified.
904 if (shiftAmt) {
905 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
906 //Zero out any flags we might modify. This way we only have to
907 //worry about setting them.

--- 9 unchanged lines hidden (view full) ---

917 ccFlagBits = ccFlagBits | OFBit;
918 //Use the regular mechanisms to calculate the other flags.
919 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
920 DestReg, psrc1, op2);
921 }
922 '''
923
924 class Sld(RegOp):
856 code = '''
925 sldCode = '''
857 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
858 uint8_t dataBits = dataSize * 8;
926 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
927 uint8_t dataBits = dataSize * 8;
859 uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
928 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);
860 uint64_t result;
861 if (realShiftAmt == 0) {
862 result = psrc1;
863 } else if (realShiftAmt < dataBits) {
864 result = (psrc1 << realShiftAmt) |
865 (DoubleBits >> (dataBits - realShiftAmt));
866 } else {
867 result = (DoubleBits << (realShiftAmt - dataBits)) |
868 (psrc1 >> (2 * dataBits - realShiftAmt));
869 }
929 uint64_t result;
930 if (realShiftAmt == 0) {
931 result = psrc1;
932 } else if (realShiftAmt < dataBits) {
933 result = (psrc1 << realShiftAmt) |
934 (DoubleBits >> (dataBits - realShiftAmt));
935 } else {
936 result = (DoubleBits << (realShiftAmt - dataBits)) |
937 (psrc1 >> (2 * dataBits - realShiftAmt));
938 }
870 DestReg = merge(DestReg, result, dataSize);
939 %s
871 '''
940 '''
941 code = sldCode % "DestReg = merge(DestReg, result, dataSize);"
942 big_code = sldCode % "DestReg = result & mask(dataSize * 8);"
872 flag_code = '''
873 // If the shift amount is zero, no flags should be modified.
874 if (shiftAmt) {
875 //Zero out any flags we might modify. This way we only have to
876 //worry about setting them.
877 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
878 int CFBits = 0;
879 //Figure out if we -would- set the CF bits if requested.

--- 14 unchanged lines hidden (view full) ---

894 ccFlagBits = ccFlagBits | OFBit;
895 //Use the regular mechanisms to calculate the other flags.
896 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
897 DestReg, psrc1, op2);
898 }
899 '''
900
901 class Srd(RegOp):
943 flag_code = '''
944 // If the shift amount is zero, no flags should be modified.
945 if (shiftAmt) {
946 //Zero out any flags we might modify. This way we only have to
947 //worry about setting them.
948 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
949 int CFBits = 0;
950 //Figure out if we -would- set the CF bits if requested.

--- 14 unchanged lines hidden (view full) ---

965 ccFlagBits = ccFlagBits | OFBit;
966 //Use the regular mechanisms to calculate the other flags.
967 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
968 DestReg, psrc1, op2);
969 }
970 '''
971
972 class Srd(RegOp):
902 code = '''
973 srdCode = '''
903 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
904 uint8_t dataBits = dataSize * 8;
974 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
975 uint8_t dataBits = dataSize * 8;
905 uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
976 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);
906 uint64_t result;
907 if (realShiftAmt == 0) {
908 result = psrc1;
909 } else if (realShiftAmt < dataBits) {
910 // Because what happens to the bits shift -in- on a right
911 // shift is not defined in the C/C++ standard, we have to
912 // mask them out to be sure they're zero.
913 uint64_t logicalMask = mask(dataBits - realShiftAmt);
914 result = ((psrc1 >> realShiftAmt) & logicalMask) |
915 (DoubleBits << (dataBits - realShiftAmt));
916 } else {
917 uint64_t logicalMask = mask(2 * dataBits - realShiftAmt);
918 result = ((DoubleBits >> (realShiftAmt - dataBits)) &
919 logicalMask) |
920 (psrc1 << (2 * dataBits - realShiftAmt));
921 }
977 uint64_t result;
978 if (realShiftAmt == 0) {
979 result = psrc1;
980 } else if (realShiftAmt < dataBits) {
981 // Because what happens to the bits shift -in- on a right
982 // shift is not defined in the C/C++ standard, we have to
983 // mask them out to be sure they're zero.
984 uint64_t logicalMask = mask(dataBits - realShiftAmt);
985 result = ((psrc1 >> realShiftAmt) & logicalMask) |
986 (DoubleBits << (dataBits - realShiftAmt));
987 } else {
988 uint64_t logicalMask = mask(2 * dataBits - realShiftAmt);
989 result = ((DoubleBits >> (realShiftAmt - dataBits)) &
990 logicalMask) |
991 (psrc1 << (2 * dataBits - realShiftAmt));
992 }
922 DestReg = merge(DestReg, result, dataSize);
993 %s
923 '''
994 '''
995 code = srdCode % "DestReg = merge(DestReg, result, dataSize);"
996 big_code = srdCode % "DestReg = result & mask(dataSize * 8);"
924 flag_code = '''
925 // If the shift amount is zero, no flags should be modified.
926 if (shiftAmt) {
927 //Zero out any flags we might modify. This way we only have to
928 //worry about setting them.
929 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
930 int CFBits = 0;
931 //If some combination of the CF bits need to be set, set them.

--- 49 unchanged lines hidden (view full) ---

981
982 class Ruflag(RegOp):
983 code = '''
984 int flag = bits(ccFlagBits, imm8);
985 DestReg = merge(DestReg, flag, dataSize);
986 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
987 (ccFlagBits & ~EZFBit);
988 '''
997 flag_code = '''
998 // If the shift amount is zero, no flags should be modified.
999 if (shiftAmt) {
1000 //Zero out any flags we might modify. This way we only have to
1001 //worry about setting them.
1002 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
1003 int CFBits = 0;
1004 //If some combination of the CF bits need to be set, set them.

--- 49 unchanged lines hidden (view full) ---

1054
1055 class Ruflag(RegOp):
1056 code = '''
1057 int flag = bits(ccFlagBits, imm8);
1058 DestReg = merge(DestReg, flag, dataSize);
1059 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1060 (ccFlagBits & ~EZFBit);
1061 '''
1062 big_code = '''
1063 int flag = bits(ccFlagBits, imm8);
1064 DestReg = flag & mask(dataSize * 8);
1065 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1066 (ccFlagBits & ~EZFBit);
1067 '''
989 def __init__(self, dest, imm, flags=None, \
990 dataSize="env.dataSize"):
991 super(Ruflag, self).__init__(dest, \
992 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
993
994 class Rflag(RegOp):
995 code = '''
996 MiscReg flagMask = 0x3F7FDD5;
997 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
998 int flag = bits(flags, imm8);
999 DestReg = merge(DestReg, flag, dataSize);
1000 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1001 (ccFlagBits & ~EZFBit);
1002 '''
1068 def __init__(self, dest, imm, flags=None, \
1069 dataSize="env.dataSize"):
1070 super(Ruflag, self).__init__(dest, \
1071 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1072
1073 class Rflag(RegOp):
1074 code = '''
1075 MiscReg flagMask = 0x3F7FDD5;
1076 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
1077 int flag = bits(flags, imm8);
1078 DestReg = merge(DestReg, flag, dataSize);
1079 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1080 (ccFlagBits & ~EZFBit);
1081 '''
1082 big_code = '''
1083 MiscReg flagMask = 0x3F7FDD5;
1084 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
1085 int flag = bits(flags, imm8);
1086 DestReg = flag & mask(dataSize * 8);
1087 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1088 (ccFlagBits & ~EZFBit);
1089 '''
1003 def __init__(self, dest, imm, flags=None, \
1004 dataSize="env.dataSize"):
1005 super(Rflag, self).__init__(dest, \
1006 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1007
1008 class Sext(RegOp):
1009 code = '''
1010 IntReg val = psrc1;
1011 // Mask the bit position so that it wraps.
1012 int bitPos = op2 & (dataSize * 8 - 1);
1013 int sign_bit = bits(val, bitPos, bitPos);
1014 uint64_t maskVal = mask(bitPos+1);
1015 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1016 DestReg = merge(DestReg, val, dataSize);
1017 '''
1090 def __init__(self, dest, imm, flags=None, \
1091 dataSize="env.dataSize"):
1092 super(Rflag, self).__init__(dest, \
1093 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1094
1095 class Sext(RegOp):
1096 code = '''
1097 IntReg val = psrc1;
1098 // Mask the bit position so that it wraps.
1099 int bitPos = op2 & (dataSize * 8 - 1);
1100 int sign_bit = bits(val, bitPos, bitPos);
1101 uint64_t maskVal = mask(bitPos+1);
1102 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1103 DestReg = merge(DestReg, val, dataSize);
1104 '''
1105 big_code = '''
1106 IntReg val = psrc1;
1107 // Mask the bit position so that it wraps.
1108 int bitPos = op2 & (dataSize * 8 - 1);
1109 int sign_bit = bits(val, bitPos, bitPos);
1110 uint64_t maskVal = mask(bitPos+1);
1111 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1112 DestReg = val & mask(dataSize * 8);
1113 '''
1018 flag_code = '''
1019 if (!sign_bit)
1020 ccFlagBits = ccFlagBits &
1021 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
1022 else
1023 ccFlagBits = ccFlagBits |
1024 (ext & (CFBit | ECFBit | ZFBit | EZFBit));
1025 '''
1026
1027 class Zext(RegOp):
1028 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
1114 flag_code = '''
1115 if (!sign_bit)
1116 ccFlagBits = ccFlagBits &
1117 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
1118 else
1119 ccFlagBits = ccFlagBits |
1120 (ext & (CFBit | ECFBit | ZFBit | EZFBit));
1121 '''
1122
1123 class Zext(RegOp):
1124 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
1125 big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);'
1029
1030 class Rddr(RegOp):
1031 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1032 super(Rddr, self).__init__(dest, \
1033 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1126
1127 class Rddr(RegOp):
1128 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1129 super(Rddr, self).__init__(dest, \
1130 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1034 code = '''
1131 rdrCode = '''
1035 CR4 cr4 = CR4Op;
1036 DR7 dr7 = DR7Op;
1037 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
1038 fault = new InvalidOpcode();
1039 } else if (dr7.gd) {
1040 fault = new DebugException();
1041 } else {
1132 CR4 cr4 = CR4Op;
1133 DR7 dr7 = DR7Op;
1134 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
1135 fault = new InvalidOpcode();
1136 } else if (dr7.gd) {
1137 fault = new DebugException();
1138 } else {
1042 DestReg = merge(DestReg, DebugSrc1, dataSize);
1139 %s
1043 }
1044 '''
1140 }
1141 '''
1142 code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);"
1143 big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);"
1045
1046 class Wrdr(RegOp):
1047 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1048 super(Wrdr, self).__init__(dest, \
1049 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1050 code = '''
1051 CR4 cr4 = CR4Op;
1052 DR7 dr7 = DR7Op;

--- 8 unchanged lines hidden (view full) ---

1061 DebugDest = psrc1;
1062 }
1063 '''
1064
1065 class Rdcr(RegOp):
1066 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1067 super(Rdcr, self).__init__(dest, \
1068 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1144
1145 class Wrdr(RegOp):
1146 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1147 super(Wrdr, self).__init__(dest, \
1148 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1149 code = '''
1150 CR4 cr4 = CR4Op;
1151 DR7 dr7 = DR7Op;

--- 8 unchanged lines hidden (view full) ---

1160 DebugDest = psrc1;
1161 }
1162 '''
1163
1164 class Rdcr(RegOp):
1165 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1166 super(Rdcr, self).__init__(dest, \
1167 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1069 code = '''
1168 rdcrCode = '''
1070 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
1071 fault = new InvalidOpcode();
1072 } else {
1169 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
1170 fault = new InvalidOpcode();
1171 } else {
1073 DestReg = merge(DestReg, ControlSrc1, dataSize);
1172 %s
1074 }
1075 '''
1173 }
1174 '''
1175 code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);"
1176 big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);"
1076
1077 class Wrcr(RegOp):
1078 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1079 super(Wrcr, self).__init__(dest, \
1080 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1081 code = '''
1082 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
1083 fault = new InvalidOpcode();

--- 65 unchanged lines hidden (view full) ---

1149 '''
1150
1151 class WrAttr(SegOp):
1152 code = '''
1153 SegAttrDest = psrc1;
1154 '''
1155
1156 class Rdbase(SegOp):
1177
1178 class Wrcr(RegOp):
1179 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1180 super(Wrcr, self).__init__(dest, \
1181 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1182 code = '''
1183 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
1184 fault = new InvalidOpcode();

--- 65 unchanged lines hidden (view full) ---

1250 '''
1251
1252 class WrAttr(SegOp):
1253 code = '''
1254 SegAttrDest = psrc1;
1255 '''
1256
1257 class Rdbase(SegOp):
1157 code = '''
1158 DestReg = merge(DestReg, SegBaseSrc1, dataSize);
1159 '''
1258 code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);'
1259 big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);'
1160
1161 class Rdlimit(SegOp):
1260
1261 class Rdlimit(SegOp):
1162 code = '''
1163 DestReg = merge(DestReg, SegLimitSrc1, dataSize);
1164 '''
1262 code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);'
1263 big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);'
1165
1166 class RdAttr(SegOp):
1264
1265 class RdAttr(SegOp):
1167 code = '''
1168 DestReg = merge(DestReg, SegAttrSrc1, dataSize);
1169 '''
1266 code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);'
1267 big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);'
1170
1171 class Rdsel(SegOp):
1268
1269 class Rdsel(SegOp):
1172 code = '''
1173 DestReg = merge(DestReg, SegSelSrc1, dataSize);
1174 '''
1270 code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);'
1271 big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);'
1175
1176 class Rdval(RegOp):
1177 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1178 super(Rdval, self).__init__(dest, src1, \
1179 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1180 code = '''
1181 DestReg = MiscRegSrc1;
1182 '''

--- 215 unchanged lines hidden --- 		1272
1273 class Rdval(RegOp):
1274 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1275 super(Rdval, self).__init__(dest, src1, \
1276 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1277 code = '''
1278 DestReg = MiscRegSrc1;
1279 '''

--- 215 unchanged lines hidden ---