regop.isa (6345:f9ae7c3a036c) regop.isa (6430:4c5671ecceda)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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512 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
513
514 class Sub(SubRegOp):
515 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
516
517 class Xor(LogicRegOp):
518 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
519
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

--- 503 unchanged lines hidden (view full) ---

512 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
513
514 class Sub(SubRegOp):
515 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
516
517 class Xor(LogicRegOp):
518 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
519
520 # Neither of these is quite correct because it assumes that right shifting
521 # a signed or unsigned value does sign or zero extension respectively.
522 # The C standard says that what happens on a right shift with a 1 in the
523 # MSB position is undefined. On x86 and under likely most compilers the
524 # "right thing" happens, but this isn't a guarantee.
525 class Mul1s(WrRegOp):
526 code = '''
527 ProdLow = psrc1 * op2;
528 int halfSize = (dataSize * 8) / 2;
520 class Mul1s(WrRegOp):
521 code = '''
522 ProdLow = psrc1 * op2;
523 int halfSize = (dataSize * 8) / 2;
529 int64_t spsrc1_h = spsrc1 >> halfSize;
530 int64_t spsrc1_l = spsrc1 & mask(halfSize);
531 int64_t spsrc2_h = sop2 >> halfSize;
532 int64_t spsrc2_l = sop2 & mask(halfSize);
533 ProdHi = ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l +
534 ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) +
535 spsrc1_h * spsrc2_h;
524 uint64_t shifter = (1ULL << halfSize);
525 uint64_t hiResult;
526 uint64_t psrc1_h = psrc1 / shifter;
527 uint64_t psrc1_l = psrc1 & mask(halfSize);
528 uint64_t psrc2_h = op2 / shifter;
529 uint64_t psrc2_l = op2 & mask(halfSize);
530 hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
531 ((psrc1_l * psrc2_l) / shifter)) /shifter) +
532 psrc1_h * psrc2_h;
533 if (spsrc1 < 0)
534 hiResult -= op2;
535 int64_t bigSop2 = sop2;
536 if (bigSop2 < 0)
537 hiResult -= psrc1;
538 ProdHi = hiResult;
536 '''
537
538 class Mul1u(WrRegOp):
539 code = '''
540 ProdLow = psrc1 * op2;
541 int halfSize = (dataSize * 8) / 2;
539 '''
540
541 class Mul1u(WrRegOp):
542 code = '''
543 ProdLow = psrc1 * op2;
544 int halfSize = (dataSize * 8) / 2;
542 uint64_t psrc1_h = psrc1 >> halfSize;
545 uint64_t shifter = (1ULL << halfSize);
546 uint64_t psrc1_h = psrc1 / shifter;
543 uint64_t psrc1_l = psrc1 & mask(halfSize);
547 uint64_t psrc1_l = psrc1 & mask(halfSize);
544 uint64_t psrc2_h = op2 >> halfSize;
548 uint64_t psrc2_h = op2 / shifter;
545 uint64_t psrc2_l = op2 & mask(halfSize);
546 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
549 uint64_t psrc2_l = op2 & mask(halfSize);
550 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
547 ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) +
551 ((psrc1_l * psrc2_l) / shifter)) / shifter) +
548 psrc1_h * psrc2_h;
549 '''
550
551 class Mulel(RdRegOp):
552 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
553
554 class Muleh(RdRegOp):
555 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):

--- 741 unchanged lines hidden --- 		552 psrc1_h * psrc2_h;
553 '''
554
555 class Mulel(RdRegOp):
556 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
557
558 class Muleh(RdRegOp):
559 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):

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