regop.isa (6222:9ee4a06a960b) | regop.isa (6345:f9ae7c3a036c) |
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1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 112 unchanged lines hidden (view full) --- 121 { 122 protected: 123 void buildMe(); 124 125 public: 126 %(class_name)s(ExtMachInst _machInst, 127 const char * instMnem, 128 bool isMicro, bool isDelayed, bool isFirst, bool isLast, | 1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 112 unchanged lines hidden (view full) --- 121 { 122 protected: 123 void buildMe(); 124 125 public: 126 %(class_name)s(ExtMachInst _machInst, 127 const char * instMnem, 128 bool isMicro, bool isDelayed, bool isFirst, bool isLast, |
129 RegIndex _src1, RegIndex _src2, RegIndex _dest, | 129 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, |
130 uint8_t _dataSize, uint16_t _ext); 131 132 %(class_name)s(ExtMachInst _machInst, 133 const char * instMnem, | 130 uint8_t _dataSize, uint16_t _ext); 131 132 %(class_name)s(ExtMachInst _machInst, 133 const char * instMnem, |
134 RegIndex _src1, RegIndex _src2, RegIndex _dest, | 134 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, |
135 uint8_t _dataSize, uint16_t _ext); 136 137 %(BasicExecDeclare)s 138 }; 139}}; 140 141def template MicroRegOpImmDeclare {{ 142 143 class %(class_name)s : public %(base_class)s 144 { 145 protected: 146 void buildMe(); 147 148 public: 149 %(class_name)s(ExtMachInst _machInst, 150 const char * instMnem, 151 bool isMicro, bool isDelayed, bool isFirst, bool isLast, | 135 uint8_t _dataSize, uint16_t _ext); 136 137 %(BasicExecDeclare)s 138 }; 139}}; 140 141def template MicroRegOpImmDeclare {{ 142 143 class %(class_name)s : public %(base_class)s 144 { 145 protected: 146 void buildMe(); 147 148 public: 149 %(class_name)s(ExtMachInst _machInst, 150 const char * instMnem, 151 bool isMicro, bool isDelayed, bool isFirst, bool isLast, |
152 RegIndex _src1, uint16_t _imm8, RegIndex _dest, | 152 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, |
153 uint8_t _dataSize, uint16_t _ext); 154 155 %(class_name)s(ExtMachInst _machInst, 156 const char * instMnem, | 153 uint8_t _dataSize, uint16_t _ext); 154 155 %(class_name)s(ExtMachInst _machInst, 156 const char * instMnem, |
157 RegIndex _src1, uint16_t _imm8, RegIndex _dest, | 157 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, |
158 uint8_t _dataSize, uint16_t _ext); 159 160 %(BasicExecDeclare)s 161 }; 162}}; 163 164def template MicroRegOpConstructor {{ 165 166 inline void %(class_name)s::buildMe() 167 { 168 %(constructor)s; 169 } 170 171 inline %(class_name)s::%(class_name)s( 172 ExtMachInst machInst, const char * instMnem, | 158 uint8_t _dataSize, uint16_t _ext); 159 160 %(BasicExecDeclare)s 161 }; 162}}; 163 164def template MicroRegOpConstructor {{ 165 166 inline void %(class_name)s::buildMe() 167 { 168 %(constructor)s; 169 } 170 171 inline %(class_name)s::%(class_name)s( 172 ExtMachInst machInst, const char * instMnem, |
173 RegIndex _src1, RegIndex _src2, RegIndex _dest, | 173 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, |
174 uint8_t _dataSize, uint16_t _ext) : 175 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 176 false, false, false, false, 177 _src1, _src2, _dest, _dataSize, _ext, 178 %(op_class)s) 179 { 180 buildMe(); 181 } 182 183 inline %(class_name)s::%(class_name)s( 184 ExtMachInst machInst, const char * instMnem, 185 bool isMicro, bool isDelayed, bool isFirst, bool isLast, | 174 uint8_t _dataSize, uint16_t _ext) : 175 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 176 false, false, false, false, 177 _src1, _src2, _dest, _dataSize, _ext, 178 %(op_class)s) 179 { 180 buildMe(); 181 } 182 183 inline %(class_name)s::%(class_name)s( 184 ExtMachInst machInst, const char * instMnem, 185 bool isMicro, bool isDelayed, bool isFirst, bool isLast, |
186 RegIndex _src1, RegIndex _src2, RegIndex _dest, | 186 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, |
187 uint8_t _dataSize, uint16_t _ext) : 188 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 189 isMicro, isDelayed, isFirst, isLast, 190 _src1, _src2, _dest, _dataSize, _ext, 191 %(op_class)s) 192 { 193 buildMe(); 194 } 195}}; 196 197def template MicroRegOpImmConstructor {{ 198 199 inline void %(class_name)s::buildMe() 200 { 201 %(constructor)s; 202 } 203 204 inline %(class_name)s::%(class_name)s( 205 ExtMachInst machInst, const char * instMnem, | 187 uint8_t _dataSize, uint16_t _ext) : 188 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 189 isMicro, isDelayed, isFirst, isLast, 190 _src1, _src2, _dest, _dataSize, _ext, 191 %(op_class)s) 192 { 193 buildMe(); 194 } 195}}; 196 197def template MicroRegOpImmConstructor {{ 198 199 inline void %(class_name)s::buildMe() 200 { 201 %(constructor)s; 202 } 203 204 inline %(class_name)s::%(class_name)s( 205 ExtMachInst machInst, const char * instMnem, |
206 RegIndex _src1, uint16_t _imm8, RegIndex _dest, | 206 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, |
207 uint8_t _dataSize, uint16_t _ext) : 208 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 209 false, false, false, false, 210 _src1, _imm8, _dest, _dataSize, _ext, 211 %(op_class)s) 212 { 213 buildMe(); 214 } 215 216 inline %(class_name)s::%(class_name)s( 217 ExtMachInst machInst, const char * instMnem, 218 bool isMicro, bool isDelayed, bool isFirst, bool isLast, | 207 uint8_t _dataSize, uint16_t _ext) : 208 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 209 false, false, false, false, 210 _src1, _imm8, _dest, _dataSize, _ext, 211 %(op_class)s) 212 { 213 buildMe(); 214 } 215 216 inline %(class_name)s::%(class_name)s( 217 ExtMachInst machInst, const char * instMnem, 218 bool isMicro, bool isDelayed, bool isFirst, bool isLast, |
219 RegIndex _src1, uint16_t _imm8, RegIndex _dest, | 219 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, |
220 uint8_t _dataSize, uint16_t _ext) : 221 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 222 isMicro, isDelayed, isFirst, isLast, 223 _src1, _imm8, _dest, _dataSize, _ext, 224 %(op_class)s) 225 { 226 buildMe(); 227 } --- 248 unchanged lines hidden (view full) --- 476 abstract = True 477 cond_check = "checkCondition(ccFlagBits, ext)" 478 479 class RdRegOp(RegOp): 480 abstract = True 481 def __init__(self, dest, src1=None, dataSize="env.dataSize"): 482 if not src1: 483 src1 = dest | 220 uint8_t _dataSize, uint16_t _ext) : 221 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 222 isMicro, isDelayed, isFirst, isLast, 223 _src1, _imm8, _dest, _dataSize, _ext, 224 %(op_class)s) 225 { 226 buildMe(); 227 } --- 248 unchanged lines hidden (view full) --- 476 abstract = True 477 cond_check = "checkCondition(ccFlagBits, ext)" 478 479 class RdRegOp(RegOp): 480 abstract = True 481 def __init__(self, dest, src1=None, dataSize="env.dataSize"): 482 if not src1: 483 src1 = dest |
484 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) | 484 super(RdRegOp, self).__init__(dest, src1, \ 485 "InstRegIndex(NUM_INTREGS)", None, dataSize) |
485 486 class WrRegOp(RegOp): 487 abstract = True 488 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): | 486 487 class WrRegOp(RegOp): 488 abstract = True 489 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): |
489 super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) | 490 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 491 src1, src2, flags, dataSize) |
490 491 class Add(FlagRegOp): 492 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 493 494 class Or(LogicRegOp): 495 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 496 497 class Adc(FlagRegOp): --- 50 unchanged lines hidden (view full) --- 548 549 class Mulel(RdRegOp): 550 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 551 552 class Muleh(RdRegOp): 553 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 554 if not src1: 555 src1 = dest | 492 493 class Add(FlagRegOp): 494 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 495 496 class Or(LogicRegOp): 497 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 498 499 class Adc(FlagRegOp): --- 50 unchanged lines hidden (view full) --- 550 551 class Mulel(RdRegOp): 552 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 553 554 class Muleh(RdRegOp): 555 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 556 if not src1: 557 src1 = dest |
556 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize) | 558 super(RdRegOp, self).__init__(dest, src1, \ 559 "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
557 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 558 flag_code = ''' 559 if (ProdHi) 560 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 561 else 562 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 563 ''' 564 --- 315 unchanged lines hidden (view full) --- 880 int flag = bits(ccFlagBits, imm8); 881 DestReg = merge(DestReg, flag, dataSize); 882 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 883 (ccFlagBits & ~EZFBit); 884 ''' 885 def __init__(self, dest, imm, flags=None, \ 886 dataSize="env.dataSize"): 887 super(Ruflag, self).__init__(dest, \ | 560 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 561 flag_code = ''' 562 if (ProdHi) 563 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 564 else 565 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 566 ''' 567 --- 315 unchanged lines hidden (view full) --- 883 int flag = bits(ccFlagBits, imm8); 884 DestReg = merge(DestReg, flag, dataSize); 885 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 886 (ccFlagBits & ~EZFBit); 887 ''' 888 def __init__(self, dest, imm, flags=None, \ 889 dataSize="env.dataSize"): 890 super(Ruflag, self).__init__(dest, \ |
888 "NUM_INTREGS", imm, flags, dataSize) | 891 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) |
889 890 class Rflag(RegOp): 891 code = ''' 892 MiscReg flagMask = 0x3F7FDD5; 893 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 894 int flag = bits(flags, imm8); 895 DestReg = merge(DestReg, flag, dataSize); 896 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 897 (ccFlagBits & ~EZFBit); 898 ''' 899 def __init__(self, dest, imm, flags=None, \ 900 dataSize="env.dataSize"): 901 super(Rflag, self).__init__(dest, \ | 892 893 class Rflag(RegOp): 894 code = ''' 895 MiscReg flagMask = 0x3F7FDD5; 896 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 897 int flag = bits(flags, imm8); 898 DestReg = merge(DestReg, flag, dataSize); 899 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 900 (ccFlagBits & ~EZFBit); 901 ''' 902 def __init__(self, dest, imm, flags=None, \ 903 dataSize="env.dataSize"): 904 super(Rflag, self).__init__(dest, \ |
902 "NUM_INTREGS", imm, flags, dataSize) | 905 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) |
903 904 class Sext(RegOp): 905 code = ''' 906 IntReg val = psrc1; 907 // Mask the bit position so that it wraps. 908 int bitPos = op2 & (dataSize * 8 - 1); 909 int sign_bit = bits(val, bitPos, bitPos); 910 uint64_t maskVal = mask(bitPos+1); --- 10 unchanged lines hidden (view full) --- 921 ''' 922 923 class Zext(RegOp): 924 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 925 926 class Rddr(RegOp): 927 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 928 super(Rddr, self).__init__(dest, \ | 906 907 class Sext(RegOp): 908 code = ''' 909 IntReg val = psrc1; 910 // Mask the bit position so that it wraps. 911 int bitPos = op2 & (dataSize * 8 - 1); 912 int sign_bit = bits(val, bitPos, bitPos); 913 uint64_t maskVal = mask(bitPos+1); --- 10 unchanged lines hidden (view full) --- 924 ''' 925 926 class Zext(RegOp): 927 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 928 929 class Rddr(RegOp): 930 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 931 super(Rddr, self).__init__(dest, \ |
929 src1, "NUM_INTREGS", flags, dataSize) | 932 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
930 code = ''' 931 CR4 cr4 = CR4Op; 932 DR7 dr7 = DR7Op; 933 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 934 fault = new InvalidOpcode(); 935 } else if (dr7.gd) { 936 fault = new DebugException(); 937 } else { 938 DestReg = merge(DestReg, DebugSrc1, dataSize); 939 } 940 ''' 941 942 class Wrdr(RegOp): 943 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 944 super(Wrdr, self).__init__(dest, \ | 933 code = ''' 934 CR4 cr4 = CR4Op; 935 DR7 dr7 = DR7Op; 936 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 937 fault = new InvalidOpcode(); 938 } else if (dr7.gd) { 939 fault = new DebugException(); 940 } else { 941 DestReg = merge(DestReg, DebugSrc1, dataSize); 942 } 943 ''' 944 945 class Wrdr(RegOp): 946 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 947 super(Wrdr, self).__init__(dest, \ |
945 src1, "NUM_INTREGS", flags, dataSize) | 948 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
946 code = ''' 947 CR4 cr4 = CR4Op; 948 DR7 dr7 = DR7Op; 949 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 950 fault = new InvalidOpcode(); | 949 code = ''' 950 CR4 cr4 = CR4Op; 951 DR7 dr7 = DR7Op; 952 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 953 fault = new InvalidOpcode(); |
951 } else if ((dest == 6 || dest == 7) && 952 bits(psrc1, 63, 32) && | 954 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && |
953 machInst.mode.mode == LongMode) { 954 fault = new GeneralProtection(0); 955 } else if (dr7.gd) { 956 fault = new DebugException(); 957 } else { 958 DebugDest = psrc1; 959 } 960 ''' 961 962 class Rdcr(RegOp): 963 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 964 super(Rdcr, self).__init__(dest, \ | 955 machInst.mode.mode == LongMode) { 956 fault = new GeneralProtection(0); 957 } else if (dr7.gd) { 958 fault = new DebugException(); 959 } else { 960 DebugDest = psrc1; 961 } 962 ''' 963 964 class Rdcr(RegOp): 965 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 966 super(Rdcr, self).__init__(dest, \ |
965 src1, "NUM_INTREGS", flags, dataSize) | 967 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
966 code = ''' 967 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 968 fault = new InvalidOpcode(); 969 } else { 970 DestReg = merge(DestReg, ControlSrc1, dataSize); 971 } 972 ''' 973 974 class Wrcr(RegOp): 975 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 976 super(Wrcr, self).__init__(dest, \ | 968 code = ''' 969 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 970 fault = new InvalidOpcode(); 971 } else { 972 DestReg = merge(DestReg, ControlSrc1, dataSize); 973 } 974 ''' 975 976 class Wrcr(RegOp): 977 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 978 super(Wrcr, self).__init__(dest, \ |
977 src1, "NUM_INTREGS", flags, dataSize) | 979 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
978 code = ''' 979 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 980 fault = new InvalidOpcode(); 981 } else { 982 // There are *s in the line below so it doesn't confuse the 983 // parser. They may be unnecessary. 984 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 985 MiscReg newVal = psrc1; --- 37 unchanged lines hidden (view full) --- 1023 } 1024 ''' 1025 1026 # Microops for manipulating segmentation registers 1027 class SegOp(CondRegOp): 1028 abstract = True 1029 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1030 super(SegOp, self).__init__(dest, \ | 980 code = ''' 981 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 982 fault = new InvalidOpcode(); 983 } else { 984 // There are *s in the line below so it doesn't confuse the 985 // parser. They may be unnecessary. 986 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 987 MiscReg newVal = psrc1; --- 37 unchanged lines hidden (view full) --- 1025 } 1026 ''' 1027 1028 # Microops for manipulating segmentation registers 1029 class SegOp(CondRegOp): 1030 abstract = True 1031 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1032 super(SegOp, self).__init__(dest, \ |
1031 src1, "NUM_INTREGS", flags, dataSize) | 1033 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
1032 1033 class Wrbase(SegOp): 1034 code = ''' 1035 SegBaseDest = psrc1; 1036 ''' 1037 1038 class Wrlimit(SegOp): 1039 code = ''' --- 27 unchanged lines hidden (view full) --- 1067 1068 class Rdsel(SegOp): 1069 code = ''' 1070 DestReg = merge(DestReg, SegSelSrc1, dataSize); 1071 ''' 1072 1073 class Rdval(RegOp): 1074 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): | 1034 1035 class Wrbase(SegOp): 1036 code = ''' 1037 SegBaseDest = psrc1; 1038 ''' 1039 1040 class Wrlimit(SegOp): 1041 code = ''' --- 27 unchanged lines hidden (view full) --- 1069 1070 class Rdsel(SegOp): 1071 code = ''' 1072 DestReg = merge(DestReg, SegSelSrc1, dataSize); 1073 ''' 1074 1075 class Rdval(RegOp): 1076 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): |
1075 super(Rdval, self).__init__(dest, \ 1076 src1, "NUM_INTREGS", flags, dataSize) | 1077 super(Rdval, self).__init__(dest, src1, \ 1078 "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
1077 code = ''' 1078 DestReg = MiscRegSrc1; 1079 ''' 1080 1081 class Wrval(RegOp): 1082 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): | 1079 code = ''' 1080 DestReg = MiscRegSrc1; 1081 ''' 1082 1083 class Wrval(RegOp): 1084 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): |
1083 super(Wrval, self).__init__(dest, \ 1084 src1, "NUM_INTREGS", flags, dataSize) | 1085 super(Wrval, self).__init__(dest, src1, \ 1086 "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
1085 code = ''' 1086 MiscRegDest = SrcReg1; 1087 ''' 1088 1089 class Chks(RegOp): 1090 def __init__(self, dest, src1, src2=0, 1091 flags=None, dataSize="env.dataSize"): 1092 super(Chks, self).__init__(dest, --- 202 unchanged lines hidden --- | 1087 code = ''' 1088 MiscRegDest = SrcReg1; 1089 ''' 1090 1091 class Chks(RegOp): 1092 def __init__(self, dest, src1, src2=0, 1093 flags=None, dataSize="env.dataSize"): 1094 super(Chks, self).__init__(dest, --- 202 unchanged lines hidden --- |