regop.isa (5932:afa0866171e1) regop.isa (5934:367ac7cae7b5)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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962 class Rdcr(RegOp):
963 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
964 super(Rdcr, self).__init__(dest, \
965 src1, "NUM_INTREGS", flags, dataSize)
966 code = '''
967 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
968 fault = new InvalidOpcode();
969 } else {
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

--- 953 unchanged lines hidden (view full) ---

962 class Rdcr(RegOp):
963 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
964 super(Rdcr, self).__init__(dest, \
965 src1, "NUM_INTREGS", flags, dataSize)
966 code = '''
967 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
968 fault = new InvalidOpcode();
969 } else {
970 DestReg = ControlSrc1;
970 DestReg = merge(DestReg, ControlSrc1, dataSize);
971 }
972 '''
973
974 class Wrcr(RegOp):
975 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
976 super(Wrcr, self).__init__(dest, \
977 src1, "NUM_INTREGS", flags, dataSize)
978 code = '''

--- 289 unchanged lines hidden --- 		971 }
972 '''
973
974 class Wrcr(RegOp):
975 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
976 super(Wrcr, self).__init__(dest, \
977 src1, "NUM_INTREGS", flags, dataSize)
978 code = '''

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