| regop.isa (5926:c182698e1ab3) | regop.isa (5927:5e3367b103da) |
|---|---|
| 1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 907 unchanged lines hidden (view full) --- 916 ccFlagBits = ccFlagBits & 917 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 918 else 919 ccFlagBits = ccFlagBits | 920 (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 921 ''' 922 923 class Zext(RegOp): | 1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 907 unchanged lines hidden (view full) --- 916 ccFlagBits = ccFlagBits & 917 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 918 else 919 ccFlagBits = ccFlagBits | 920 (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 921 ''' 922 923 class Zext(RegOp): |
| 924 code = 'DestReg = bits(psrc1, op2, 0);' | 924 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' |
| 925 926 class Rddr(RegOp): 927 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 928 super(Rddr, self).__init__(dest, \ 929 src1, "NUM_INTREGS", flags, dataSize) 930 code = ''' 931 CR4 cr4 = CR4Op; 932 DR7 dr7 = DR7Op; --- 335 unchanged lines hidden --- | 925 926 class Rddr(RegOp): 927 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 928 super(Rddr, self).__init__(dest, \ 929 src1, "NUM_INTREGS", flags, dataSize) 930 code = ''' 931 CR4 cr4 = CR4Op; 932 DR7 dr7 = DR7Op; --- 335 unchanged lines hidden --- |