regop.isa (5924:516eda09c743) regop.isa (5926:c182698e1ab3)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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918 else
919 ccFlagBits = ccFlagBits |
920 (ext & (CFBit | ECFBit | ZFBit | EZFBit));
921 '''
922
923 class Zext(RegOp):
924 code = 'DestReg = bits(psrc1, op2, 0);'
925
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

--- 909 unchanged lines hidden (view full) ---

918 else
919 ccFlagBits = ccFlagBits |
920 (ext & (CFBit | ECFBit | ZFBit | EZFBit));
921 '''
922
923 class Zext(RegOp):
924 code = 'DestReg = bits(psrc1, op2, 0);'
925
926 class Rddr(RegOp):
927 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
928 super(Rddr, self).__init__(dest, \
929 src1, "NUM_INTREGS", flags, dataSize)
930 code = '''
931 CR4 cr4 = CR4Op;
932 DR7 dr7 = DR7Op;
933 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
934 fault = new InvalidOpcode();
935 } else if (dr7.gd) {
936 fault = new DebugException();
937 } else {
938 DestReg = merge(DestReg, DebugSrc1, dataSize);
939 }
940 '''
941
942 class Wrdr(RegOp):
943 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
944 super(Wrdr, self).__init__(dest, \
945 src1, "NUM_INTREGS", flags, dataSize)
946 code = '''
947 CR4 cr4 = CR4Op;
948 DR7 dr7 = DR7Op;
949 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) {
950 fault = new InvalidOpcode();
951 } else if ((dest == 6 || dest == 7) &&
952 bits(psrc1, 63, 32) &&
953 machInst.mode.mode == LongMode) {
954 fault = new GeneralProtection(0);
955 } else if (dr7.gd) {
956 fault = new DebugException();
957 } else {
958 DebugDest = psrc1;
959 }
960 '''
961
926 class Rdcr(RegOp):
927 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
928 super(Rdcr, self).__init__(dest, \
929 src1, "NUM_INTREGS", flags, dataSize)
930 code = '''
931 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
932 fault = new InvalidOpcode();
933 } else {

--- 298 unchanged lines hidden --- 		962 class Rdcr(RegOp):
963 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
964 super(Rdcr, self).__init__(dest, \
965 src1, "NUM_INTREGS", flags, dataSize)
966 code = '''
967 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
968 fault = new InvalidOpcode();
969 } else {

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