regop.isa (5905:e342ab8f92fa) regop.isa (5924:516eda09c743)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

--- 914 unchanged lines hidden (view full) ---

923 class Zext(RegOp):
924 code = 'DestReg = bits(psrc1, op2, 0);'
925
926 class Rdcr(RegOp):
927 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
928 super(Rdcr, self).__init__(dest, \
929 src1, "NUM_INTREGS", flags, dataSize)
930 code = '''
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

--- 914 unchanged lines hidden (view full) ---

923 class Zext(RegOp):
924 code = 'DestReg = bits(psrc1, op2, 0);'
925
926 class Rdcr(RegOp):
927 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
928 super(Rdcr, self).__init__(dest, \
929 src1, "NUM_INTREGS", flags, dataSize)
930 code = '''
931 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
931 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
932 fault = new InvalidOpcode();
933 } else {
934 DestReg = ControlSrc1;
935 }
936 '''
937
938 class Wrcr(RegOp):
939 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):

--- 292 unchanged lines hidden --- 		932 fault = new InvalidOpcode();
933 } else {
934 DestReg = ControlSrc1;
935 }
936 '''
937
938 class Wrcr(RegOp):
939 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):

--- 292 unchanged lines hidden ---