regop.isa (5076:956a475dddea) | regop.isa (5083:49559a8060e8) |
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1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 444 unchanged lines hidden (view full) --- 453 454 class SubRegOp(RegOp): 455 abstract = True 456 flag_code = \ 457 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 458 459 class CondRegOp(RegOp): 460 abstract = True | 1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 444 unchanged lines hidden (view full) --- 453 454 class SubRegOp(RegOp): 455 abstract = True 456 flag_code = \ 457 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 458 459 class CondRegOp(RegOp): 460 abstract = True |
461 cond_check = "checkCondition(ccFlagBits)" | 461 cond_check = "checkCondition(ccFlagBits, ext)" |
462 463 class RdRegOp(RegOp): 464 abstract = True 465 def __init__(self, dest, src1=None, dataSize="env.dataSize"): 466 if not src1: 467 src1 = dest 468 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 469 --- 398 unchanged lines hidden (view full) --- 868 int sign_bit = bits(val, imm8-1, imm8-1); 869 uint64_t maskVal = mask(imm8); 870 val = sign_bit ? (val | ~maskVal) : (val & maskVal); 871 DestReg = merge(DestReg, val, dataSize); 872 ''' 873 874 class Zext(RegOp): 875 code = 'DestReg = bits(psrc1, imm8-1, 0);' | 462 463 class RdRegOp(RegOp): 464 abstract = True 465 def __init__(self, dest, src1=None, dataSize="env.dataSize"): 466 if not src1: 467 src1 = dest 468 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 469 --- 398 unchanged lines hidden (view full) --- 868 int sign_bit = bits(val, imm8-1, imm8-1); 869 uint64_t maskVal = mask(imm8); 870 val = sign_bit ? (val | ~maskVal) : (val & maskVal); 871 DestReg = merge(DestReg, val, dataSize); 872 ''' 873 874 class Zext(RegOp): 875 code = 'DestReg = bits(psrc1, imm8-1, 0);' |
876 877 class Compfp(WrRegOp): 878 # This class sets the condition codes in rflags according to the 879 # rules for comparing floating point. 880 code = ''' 881 // ZF PF CF 882 // Unordered 1 1 1 883 // Greater than 0 0 0 884 // Less than 0 0 1 885 // Equal 1 0 0 886 // OF = SF = AF = 0 887 ccFlagBits = ccFlagBits & ~(OFBit | SFBit | AFBit | 888 ZFBit | PFBit | CFBit); 889 if (isnan(FpSrcReg1) || isnan(FpSrcReg2)) 890 ccFlagBits = ccFlagBits | (ZFBit | PFBit | CFBit); 891 else if(FpSrcReg1 < FpSrcReg2) 892 ccFlagBits = ccFlagBits | CFBit; 893 else if(FpSrcReg1 == FpSrcReg2) 894 ccFlagBits = ccFlagBits | ZFBit; 895 ''' 896 897 class Xorfp(RegOp): 898 code = 'FpDestReg.uqw = FpSrcReg1.uqw ^ FpSrcReg2.uqw;' 899 900 class Sqrtfp(RegOp): 901 code = 'FpDestReg = sqrt(FpSrcReg2);' 902 903 class Movfp(CondRegOp): 904 code = 'FpDestReg.uqw = FpSrcReg2.uqw;' 905 else_code = 'FpDestReg.uqw = FpDestReg.uqw;' 906 907 # Conversion microops 908 class ConvOp(RegOp): 909 abstract = True 910 def __init__(self, dest, src1): 911 super(ConvOp, self).__init__(dest, src1, "NUM_INTREGS") 912 913 #FIXME This needs to always use 32 bits unless REX.W is present 914 class cvtf_i2d(ConvOp): 915 code = 'FpDestReg = spsrc1;' 916 917 class cvtf_i2d_hi(ConvOp): 918 code = 'FpDestReg = bits(SrcReg1, 63, 32);' 919 920 class cvtf_d2i(ConvOp): 921 code = ''' 922 int64_t intSrcReg1 = static_cast<int64_t>(FpSrcReg1); 923 DestReg = merge(DestReg, intSrcReg1, dataSize); 924 ''' 925 926 # These need to consider size at some point. They'll always use doubles 927 # for the moment. 928 class addfp(RegOp): 929 code = 'FpDestReg = FpSrcReg1 + FpSrcReg2;' 930 931 class mulfp(RegOp): 932 code = 'FpDestReg = FpSrcReg1 * FpSrcReg2;' 933 934 class divfp(RegOp): 935 code = 'FpDestReg = FpSrcReg1 / FpSrcReg2;' 936 937 class subfp(RegOp): 938 code = 'FpDestReg = FpSrcReg1 - FpSrcReg2;' | |
939}}; | 876}}; |