regop.isa (5075:4ae876c5037d) regop.isa (5076:956a475dddea)
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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607 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
608
609 class Mov(CondRegOp):
610 code = 'DestReg = merge(SrcReg1, op2, dataSize)'
611 else_code = 'DestReg=DestReg;'
612
613 # Shift instructions
614
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

--- 598 unchanged lines hidden (view full) ---

607 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
608
609 class Mov(CondRegOp):
610 code = 'DestReg = merge(SrcReg1, op2, dataSize)'
611 else_code = 'DestReg=DestReg;'
612
613 # Shift instructions
614
615 class Sll(FlagRegOp):
615 class Sll(RegOp):
616 code = '''
617 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
618 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
619 '''
616 code = '''
617 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
618 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
619 '''
620 flag_code = '''
621 // If the shift amount is zero, no flags should be modified.
622 if (shiftAmt) {
623 //Zero out any flags we might modify. This way we only have to
624 //worry about setting them.
625 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
626 int CFBits = 0;
627 //Figure out if we -would- set the CF bits if requested.
628 if (bits(SrcReg1, dataSize * 8 - shiftAmt))
629 CFBits = 1;
630 //If some combination of the CF bits need to be set, set them.
631 if ((ext & (CFBit | ECFBit)) && CFBits)
632 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
633 //Figure out what the OF bit should be.
634 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
635 ccFlagBits = ccFlagBits | OFBit;
636 //Use the regular mechanisms to calculate the other flags.
637 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
638 DestReg, psrc1, op2);
639 }
640 '''
620
641
621 class Srl(FlagRegOp):
642 class Srl(RegOp):
622 code = '''
623 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
624 // Because what happens to the bits shift -in- on a right shift
625 // is not defined in the C/C++ standard, we have to mask them out
626 // to be sure they're zero.
627 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
628 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
629 '''
643 code = '''
644 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
645 // Because what happens to the bits shift -in- on a right shift
646 // is not defined in the C/C++ standard, we have to mask them out
647 // to be sure they're zero.
648 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
649 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
650 '''
651 flag_code = '''
652 // If the shift amount is zero, no flags should be modified.
653 if (shiftAmt) {
654 //Zero out any flags we might modify. This way we only have to
655 //worry about setting them.
656 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
657 //If some combination of the CF bits need to be set, set them.
658 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
659 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
660 //Figure out what the OF bit should be.
661 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
662 ccFlagBits = ccFlagBits | OFBit;
663 //Use the regular mechanisms to calculate the other flags.
664 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
665 DestReg, psrc1, op2);
666 }
667 '''
630
668
631 class Sra(FlagRegOp):
669 class Sra(RegOp):
632 code = '''
633 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
634 // Because what happens to the bits shift -in- on a right shift
635 // is not defined in the C/C++ standard, we have to sign extend
636 // them manually to be sure.
637 uint64_t arithMask =
638 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
639 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
640 '''
670 code = '''
671 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
672 // Because what happens to the bits shift -in- on a right shift
673 // is not defined in the C/C++ standard, we have to sign extend
674 // them manually to be sure.
675 uint64_t arithMask =
676 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
677 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
678 '''
679 flag_code = '''
680 // If the shift amount is zero, no flags should be modified.
681 if (shiftAmt) {
682 //Zero out any flags we might modify. This way we only have to
683 //worry about setting them.
684 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
685 //If some combination of the CF bits need to be set, set them.
686 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
687 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
688 //Use the regular mechanisms to calculate the other flags.
689 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
690 DestReg, psrc1, op2);
691 }
692 '''
641
693
642 class Ror(FlagRegOp):
694 class Ror(RegOp):
643 code = '''
644 uint8_t shiftAmt =
645 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
646 if(shiftAmt)
647 {
648 uint64_t top = psrc1 << (dataSize * 8 - shiftAmt);
649 uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
650 DestReg = merge(DestReg, top | bottom, dataSize);
651 }
652 else
653 DestReg = DestReg;
654 '''
695 code = '''
696 uint8_t shiftAmt =
697 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
698 if(shiftAmt)
699 {
700 uint64_t top = psrc1 << (dataSize * 8 - shiftAmt);
701 uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
702 DestReg = merge(DestReg, top | bottom, dataSize);
703 }
704 else
705 DestReg = DestReg;
706 '''
707 flag_code = '''
708 // If the shift amount is zero, no flags should be modified.
709 if (shiftAmt) {
710 //Zero out any flags we might modify. This way we only have to
711 //worry about setting them.
712 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
713 //Find the most and second most significant bits of the result.
714 int msb = bits(DestReg, dataSize * 8 - 1);
715 int smsb = bits(DestReg, dataSize * 8 - 2);
716 //If some combination of the CF bits need to be set, set them.
717 if ((ext & (CFBit | ECFBit)) && msb)
718 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
719 //Figure out what the OF bit should be.
720 if ((ext & OFBit) && (msb ^ smsb))
721 ccFlagBits = ccFlagBits | OFBit;
722 //Use the regular mechanisms to calculate the other flags.
723 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
724 DestReg, psrc1, op2);
725 }
726 '''
655
727
656 class Rcr(FlagRegOp):
728 class Rcr(RegOp):
657 code = '''
658 uint8_t shiftAmt =
659 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
660 if(shiftAmt)
661 {
662 CCFlagBits flags = ccFlagBits;
663 uint64_t top = flags.CF << (dataSize * 8 - shiftAmt);
664 if(shiftAmt > 1)
665 top |= psrc1 << (dataSize * 8 - shiftAmt - 1);
666 uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
667 DestReg = merge(DestReg, top | bottom, dataSize);
668 }
669 else
670 DestReg = DestReg;
671 '''
729 code = '''
730 uint8_t shiftAmt =
731 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
732 if(shiftAmt)
733 {
734 CCFlagBits flags = ccFlagBits;
735 uint64_t top = flags.CF << (dataSize * 8 - shiftAmt);
736 if(shiftAmt > 1)
737 top |= psrc1 << (dataSize * 8 - shiftAmt - 1);
738 uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
739 DestReg = merge(DestReg, top | bottom, dataSize);
740 }
741 else
742 DestReg = DestReg;
743 '''
744 flag_code = '''
745 // If the shift amount is zero, no flags should be modified.
746 if (shiftAmt) {
747 //Zero out any flags we might modify. This way we only have to
748 //worry about setting them.
749 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
750 //Figure out what the OF bit should be.
751 if ((ext & OFBit) && ((ccFlagBits & CFBit) ^
752 bits(SrcReg1, dataSize * 8 - 1)))
753 ccFlagBits = ccFlagBits | OFBit;
754 //If some combination of the CF bits need to be set, set them.
755 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
756 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
757 //Use the regular mechanisms to calculate the other flags.
758 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
759 DestReg, psrc1, op2);
760 }
761 '''
672
762
673 class Rol(FlagRegOp):
763 class Rol(RegOp):
674 code = '''
675 uint8_t shiftAmt =
676 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
677 if(shiftAmt)
678 {
679 uint64_t top = psrc1 << shiftAmt;
680 uint64_t bottom =
681 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
682 DestReg = merge(DestReg, top | bottom, dataSize);
683 }
684 else
685 DestReg = DestReg;
686 '''
764 code = '''
765 uint8_t shiftAmt =
766 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
767 if(shiftAmt)
768 {
769 uint64_t top = psrc1 << shiftAmt;
770 uint64_t bottom =
771 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
772 DestReg = merge(DestReg, top | bottom, dataSize);
773 }
774 else
775 DestReg = DestReg;
776 '''
777 flag_code = '''
778 // If the shift amount is zero, no flags should be modified.
779 if (shiftAmt) {
780 //Zero out any flags we might modify. This way we only have to
781 //worry about setting them.
782 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
783 //The CF bits, if set, would be set to the lsb of the result.
784 int lsb = DestReg & 0x1;
785 int msb = bits(DestReg, dataSize * 8 - 1);
786 //If some combination of the CF bits need to be set, set them.
787 if ((ext & (CFBit | ECFBit)) && lsb)
788 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
789 //Figure out what the OF bit should be.
790 if ((ext & OFBit) && (msb ^ lsb))
791 ccFlagBits = ccFlagBits | OFBit;
792 //Use the regular mechanisms to calculate the other flags.
793 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
794 DestReg, psrc1, op2);
795 }
796 '''
687
797
688 class Rcl(FlagRegOp):
798 class Rcl(RegOp):
689 code = '''
690 uint8_t shiftAmt =
691 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
692 if(shiftAmt)
693 {
694 CCFlagBits flags = ccFlagBits;
695 uint64_t top = psrc1 << shiftAmt;
696 uint64_t bottom = flags.CF << (shiftAmt - 1);
697 if(shiftAmt > 1)
698 bottom |=
699 bits(psrc1, dataSize * 8 - 1,
700 dataSize * 8 - shiftAmt + 1);
701 DestReg = merge(DestReg, top | bottom, dataSize);
702 }
703 else
704 DestReg = DestReg;
705 '''
799 code = '''
800 uint8_t shiftAmt =
801 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
802 if(shiftAmt)
803 {
804 CCFlagBits flags = ccFlagBits;
805 uint64_t top = psrc1 << shiftAmt;
806 uint64_t bottom = flags.CF << (shiftAmt - 1);
807 if(shiftAmt > 1)
808 bottom |=
809 bits(psrc1, dataSize * 8 - 1,
810 dataSize * 8 - shiftAmt + 1);
811 DestReg = merge(DestReg, top | bottom, dataSize);
812 }
813 else
814 DestReg = DestReg;
815 '''
816 flag_code = '''
817 // If the shift amount is zero, no flags should be modified.
818 if (shiftAmt) {
819 //Zero out any flags we might modify. This way we only have to
820 //worry about setting them.
821 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
822 int msb = bits(DestReg, dataSize * 8 - 1);
823 int CFBits = bits(SrcReg1, dataSize * 8 - shiftAmt);
824 //If some combination of the CF bits need to be set, set them.
825 if ((ext & (CFBit | ECFBit)) && CFBits)
826 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
827 //Figure out what the OF bit should be.
828 if ((ext & OFBit) && (msb ^ CFBits))
829 ccFlagBits = ccFlagBits | OFBit;
830 //Use the regular mechanisms to calculate the other flags.
831 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
832 DestReg, psrc1, op2);
833 }
834 '''
706
707 class Wrip(WrRegOp, CondRegOp):
708 code = 'RIP = psrc1 + op2'
709 else_code="RIP = RIP;"
710
711 class Br(WrRegOp, CondRegOp):
712 code = 'nuIP = psrc1 + op2;'
713 else_code='nuIP = nuIP;'

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836 class Wrip(WrRegOp, CondRegOp):
837 code = 'RIP = psrc1 + op2'
838 else_code="RIP = RIP;"
839
840 class Br(WrRegOp, CondRegOp):
841 code = 'nuIP = psrc1 + op2;'
842 else_code='nuIP = nuIP;'

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