regop.isa (5063:8eb72b1bd3c6) regop.isa (5065:63321c544086)
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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455 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
456
457 class Sub(SubRegOp):
458 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
459
460 class Xor(LogicRegOp):
461 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
462
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

--- 446 unchanged lines hidden (view full) ---

455 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
456
457 class Sub(SubRegOp):
458 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
459
460 class Xor(LogicRegOp):
461 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
462
463 # Neither of these is quite correct because it assumes that right shifting
464 # a signed or unsigned value does sign or zero extension respectively.
465 # The C standard says that what happens on a right shift with a 1 in the
466 # MSB position is undefined. On x86 and under likely most compilers the
467 # "right thing" happens, but this isn't a guarantee.
463 class Mul1s(WrRegOp):
464 code = '''
465 ProdLow = psrc1 * op2;
466 int halfSize = (dataSize * 8) / 2;
467 int64_t spsrc1_h = spsrc1 >> halfSize;
468 int64_t spsrc1_l = spsrc1 & mask(halfSize);
469 int64_t spsrc2_h = sop2 >> halfSize;
470 int64_t spsrc2_l = sop2 & mask(halfSize);

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484 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
485 ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) +
486 psrc1_h * psrc2_h;
487 '''
488
489 class Mulel(RdRegOp):
490 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
491
468 class Mul1s(WrRegOp):
469 code = '''
470 ProdLow = psrc1 * op2;
471 int halfSize = (dataSize * 8) / 2;
472 int64_t spsrc1_h = spsrc1 >> halfSize;
473 int64_t spsrc1_l = spsrc1 & mask(halfSize);
474 int64_t spsrc2_h = sop2 >> halfSize;
475 int64_t spsrc2_l = sop2 & mask(halfSize);

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489 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
490 ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) +
491 psrc1_h * psrc2_h;
492 '''
493
494 class Mulel(RdRegOp):
495 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
496
492 # Neither of these is quite correct because it assumes that right shifting
493 # a signed or unsigned value does sign or zero extension respectively.
494 # The C standard says that what happens on a right shift with a 1 in the
495 # MSB position is undefined. On x86 and under likely most compilers the
496 # "right thing" happens, but this isn't a guarantee.
497 class Muleh(RdRegOp):
498 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
499 if not src1:
500 src1 = dest
501 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize)
502 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
503 flag_code = '''
504 if (ProdHi)

--- 222 unchanged lines hidden --- 		497 class Muleh(RdRegOp):
498 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
499 if not src1:
500 src1 = dest
501 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize)
502 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
503 flag_code = '''
504 if (ProdHi)

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