regop.isa (5062:4c98f8cdcc11) regop.isa (5063:8eb72b1bd3c6)
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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416 abstract = True
417 flag_code = \
418 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
419
420 class CondRegOp(RegOp):
421 abstract = True
422 cond_check = "checkCondition(ccFlagBits)"
423
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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416 abstract = True
417 flag_code = \
418 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
419
420 class CondRegOp(RegOp):
421 abstract = True
422 cond_check = "checkCondition(ccFlagBits)"
423
424 class RdRegOp(RegOp):
425 abstract = True
426 def __init__(self, dest, src1=None, dataSize="env.dataSize"):
427 if not src1:
428 src1 = dest
429 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
430
431 class WrRegOp(RegOp):
432 abstract = True
433 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
434 super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
435
424 class Add(FlagRegOp):
425 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
426
427 class Or(LogicRegOp):
428 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
429
430 class Adc(FlagRegOp):
431 code = '''

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443 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
444
445 class Sub(SubRegOp):
446 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
447
448 class Xor(LogicRegOp):
449 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
450
436 class Add(FlagRegOp):
437 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
438
439 class Or(LogicRegOp):
440 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
441
442 class Adc(FlagRegOp):
443 code = '''

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455 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
456
457 class Sub(SubRegOp):
458 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
459
460 class Xor(LogicRegOp):
461 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
462
451 class Mul1s(FlagRegOp):
463 class Mul1s(WrRegOp):
452 code = '''
464 code = '''
453 int signPos = (dataSize * 8) / 2 - 1;
454 IntReg srcVal1 = psrc1 | (-bits(psrc1, signPos) << signPos);
455 IntReg srcVal2 = op2 | (-bits(psrc1, signPos) << signPos);
456 DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
465 ProdLow = psrc1 * op2;
466 int halfSize = (dataSize * 8) / 2;
467 int64_t spsrc1_h = spsrc1 >> halfSize;
468 int64_t spsrc1_l = spsrc1 & mask(halfSize);
469 int64_t spsrc2_h = sop2 >> halfSize;
470 int64_t spsrc2_l = sop2 & mask(halfSize);
471 ProdHi = ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l +
472 ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) +
473 spsrc1_h * spsrc2_h;
457 '''
458
474 '''
475
459 class Mul1u(FlagRegOp):
476 class Mul1u(WrRegOp):
460 code = '''
477 code = '''
478 ProdLow = psrc1 * op2;
461 int halfSize = (dataSize * 8) / 2;
479 int halfSize = (dataSize * 8) / 2;
462 IntReg srcVal1 = psrc1 & mask(halfSize);
463 IntReg srcVal2 = op2 & mask(halfSize);
464 DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
480 uint64_t psrc1_h = psrc1 >> halfSize;
481 uint64_t psrc1_l = psrc1 & mask(halfSize);
482 uint64_t psrc2_h = op2 >> halfSize;
483 uint64_t psrc2_l = op2 & mask(halfSize);
484 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
485 ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) +
486 psrc1_h * psrc2_h;
465 '''
466
487 '''
488
467 class Mulel(FlagRegOp):
468 code = 'DestReg = merge(DestReg, psrc1 * op2, dataSize);'
489 class Mulel(RdRegOp):
490 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
469
470 # Neither of these is quite correct because it assumes that right shifting
471 # a signed or unsigned value does sign or zero extension respectively.
472 # The C standard says that what happens on a right shift with a 1 in the
473 # MSB position is undefined. On x86 and under likely most compilers the
474 # "right thing" happens, but this isn't a guarantee.
491
492 # Neither of these is quite correct because it assumes that right shifting
493 # a signed or unsigned value does sign or zero extension respectively.
494 # The C standard says that what happens on a right shift with a 1 in the
495 # MSB position is undefined. On x86 and under likely most compilers the
496 # "right thing" happens, but this isn't a guarantee.
475 class Muleh(FlagRegOp):
476 code = '''
477 int halfSize = (dataSize * 8) / 2;
478 uint64_t psrc1_h = psrc1 >> halfSize;
479 uint64_t psrc1_l = psrc1 & mask(halfSize);
480 uint64_t psrc2_h = op2 >> halfSize;
481 uint64_t psrc2_l = op2 & mask(halfSize);
482 uint64_t result =
483 ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
484 ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) +
485 psrc1_h * psrc2_h;
486 DestReg = merge(DestReg, result, dataSize);
487 '''
497 class Muleh(RdRegOp):
498 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
499 if not src1:
500 src1 = dest
501 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize)
502 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
503 flag_code = '''
504 if (ProdHi)
505 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
506 else
507 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
508 '''
488
509
489 class Mulehs(FlagRegOp):
490 code = '''
491 int halfSize = (dataSize * 8) / 2;
492 int64_t spsrc1_h = spsrc1 >> halfSize;
493 int64_t spsrc1_l = spsrc1 & mask(halfSize);
494 int64_t spsrc2_h = sop2 >> halfSize;
495 int64_t spsrc2_l = sop2 & mask(halfSize);
496 int64_t result =
497 ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l +
498 ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) +
499 spsrc1_h * spsrc2_h;
500 DestReg = merge(DestReg, result, dataSize);
501 '''
502
503 class Div1(FlagRegOp):
504 code = '''
505 int halfSize = (dataSize * 8) / 2;
506 IntReg quotient = (psrc1 / op2) & mask(halfSize);
507 IntReg remainder = (psrc1 % op2) & mask(halfSize);
508 IntReg result = quotient | (remainder << halfSize);
509 DestReg = merge(DestReg, result, dataSize);
510 '''

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608 bits(psrc1, dataSize * 8 - 1,
609 dataSize * 8 - shiftAmt + 1);
610 DestReg = merge(DestReg, top | bottom, dataSize);
611 }
612 else
613 DestReg = DestReg;
614 '''
615
510 class Div1(FlagRegOp):
511 code = '''
512 int halfSize = (dataSize * 8) / 2;
513 IntReg quotient = (psrc1 / op2) & mask(halfSize);
514 IntReg remainder = (psrc1 % op2) & mask(halfSize);
515 IntReg result = quotient | (remainder << halfSize);
516 DestReg = merge(DestReg, result, dataSize);
517 '''

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615 bits(psrc1, dataSize * 8 - 1,
616 dataSize * 8 - shiftAmt + 1);
617 DestReg = merge(DestReg, top | bottom, dataSize);
618 }
619 else
620 DestReg = DestReg;
621 '''
622
616 class WrRegOp(RegOp):
617 abstract = True
618 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
619 super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
620
621 class Wrip(WrRegOp, CondRegOp):
622 code = 'RIP = psrc1 + op2'
623 else_code="RIP = RIP;"
624
625 class Br(WrRegOp, CondRegOp):
626 code = 'nuIP = psrc1 + op2;'
627 else_code='nuIP = nuIP;'
628
629 class Wruflags(WrRegOp):
630 code = 'ccFlagBits = psrc1 ^ op2'
631
623 class Wrip(WrRegOp, CondRegOp):
624 code = 'RIP = psrc1 + op2'
625 else_code="RIP = RIP;"
626
627 class Br(WrRegOp, CondRegOp):
628 code = 'nuIP = psrc1 + op2;'
629 else_code='nuIP = nuIP;'
630
631 class Wruflags(WrRegOp):
632 code = 'ccFlagBits = psrc1 ^ op2'
633
632 class RdRegOp(RegOp):
633 abstract = True
634 def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
635 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
636
637 class Rdip(RdRegOp):
638 code = 'DestReg = RIP'
639
640 class Ruflags(RdRegOp):
641 code = 'DestReg = ccFlagBits'
642
643 class Ruflag(RegOp):
644 code = '''

--- 85 unchanged lines hidden --- 		634 class Rdip(RdRegOp):
635 code = 'DestReg = RIP'
636
637 class Ruflags(RdRegOp):
638 code = 'DestReg = ccFlagBits'
639
640 class Ruflag(RegOp):
641 code = '''

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