regop.isa (5042:bc2c08abe249) regop.isa (5046:da031ef02439)
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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631 int sign_bit = bits(val, imm8-1, imm8-1);
632 uint64_t maskVal = mask(imm8);
633 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
634 DestReg = merge(DestReg, val, dataSize);
635 '''
636
637 class Zext(RegOp):
638 code = 'DestReg = bits(psrc1, imm8-1, 0);'
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

--- 622 unchanged lines hidden (view full) ---

631 int sign_bit = bits(val, imm8-1, imm8-1);
632 uint64_t maskVal = mask(imm8);
633 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
634 DestReg = merge(DestReg, val, dataSize);
635 '''
636
637 class Zext(RegOp):
638 code = 'DestReg = bits(psrc1, imm8-1, 0);'
639
640 # Conversion microops
641 class ConvOp(RegOp):
642 abstract = True
643 def __init__(self, dest, src1):
644 super(ConvOp, self).__init__(dest, src1, "NUM_INTREGS")
645
646 #FIXME This needs to always use 32 bits unless REX.W is present
647 class cvtf_i2d(ConvOp):
648 code = 'FpDestReg = psrc1;'
649
650 class cvtf_i2d_hi(ConvOp):
651 code = 'FpDestReg = bits(SrcReg1, 63, 32);'
652
653 class cvtf_d2i(ConvOp):
654 code = '''
655 int64_t intSrcReg1 = static_cast<int64_t>(FpSrcReg1);
656 DestReg = merge(DestReg, intSrcReg1, dataSize);
657 '''
639}};
658}};