regop.isa (4950:f5f19784acf1) | regop.isa (4951:1b51fb0c3983) |
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1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 75 unchanged lines hidden (view full) --- 84 { 85 %(op_wb)s; 86 } 87 return fault; 88 } 89}}; 90 91def template MicroRegOpImmExecute {{ | 1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 75 unchanged lines hidden (view full) --- 84 { 85 %(op_wb)s; 86 } 87 return fault; 88 } 89}}; 90 91def template MicroRegOpImmExecute {{ |
92 Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc, | 92 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, |
93 Trace::InstRecord *traceData) const 94 { 95 Fault fault = NoFault; 96 97 %(op_decl)s; 98 %(op_rd)s; 99 100 if(%(cond_check)s) --- 34 unchanged lines hidden (view full) --- 135 uint8_t _dataSize, uint16_t _ext); 136 137 %(BasicExecDeclare)s 138 }; 139}}; 140 141def template MicroRegOpImmDeclare {{ 142 | 93 Trace::InstRecord *traceData) const 94 { 95 Fault fault = NoFault; 96 97 %(op_decl)s; 98 %(op_rd)s; 99 100 if(%(cond_check)s) --- 34 unchanged lines hidden (view full) --- 135 uint8_t _dataSize, uint16_t _ext); 136 137 %(BasicExecDeclare)s 138 }; 139}}; 140 141def template MicroRegOpImmDeclare {{ 142 |
143 class %(class_name)sImm : public %(base_class)s | 143 class %(class_name)s : public %(base_class)s |
144 { 145 protected: 146 void buildMe(); 147 148 public: | 144 { 145 protected: 146 void buildMe(); 147 148 public: |
149 %(class_name)sImm(ExtMachInst _machInst, | 149 %(class_name)s(ExtMachInst _machInst, |
150 const char * instMnem, 151 bool isMicro, bool isDelayed, bool isFirst, bool isLast, | 150 const char * instMnem, 151 bool isMicro, bool isDelayed, bool isFirst, bool isLast, |
152 RegIndex _src1, uint8_t _imm8, RegIndex _dest, | 152 RegIndex _src1, uint16_t _imm8, RegIndex _dest, |
153 uint8_t _dataSize, uint16_t _ext); 154 | 153 uint8_t _dataSize, uint16_t _ext); 154 |
155 %(class_name)sImm(ExtMachInst _machInst, | 155 %(class_name)s(ExtMachInst _machInst, |
156 const char * instMnem, | 156 const char * instMnem, |
157 RegIndex _src1, uint8_t _imm8, RegIndex _dest, | 157 RegIndex _src1, uint16_t _imm8, RegIndex _dest, |
158 uint8_t _dataSize, uint16_t _ext); 159 160 %(BasicExecDeclare)s 161 }; 162}}; 163 164def template MicroRegOpConstructor {{ 165 --- 25 unchanged lines hidden (view full) --- 191 %(op_class)s) 192 { 193 buildMe(); 194 } 195}}; 196 197def template MicroRegOpImmConstructor {{ 198 | 158 uint8_t _dataSize, uint16_t _ext); 159 160 %(BasicExecDeclare)s 161 }; 162}}; 163 164def template MicroRegOpConstructor {{ 165 --- 25 unchanged lines hidden (view full) --- 191 %(op_class)s) 192 { 193 buildMe(); 194 } 195}}; 196 197def template MicroRegOpImmConstructor {{ 198 |
199 inline void %(class_name)sImm::buildMe() | 199 inline void %(class_name)s::buildMe() |
200 { 201 %(constructor)s; 202 } 203 | 200 { 201 %(constructor)s; 202 } 203 |
204 inline %(class_name)sImm::%(class_name)sImm( | 204 inline %(class_name)s::%(class_name)s( |
205 ExtMachInst machInst, const char * instMnem, | 205 ExtMachInst machInst, const char * instMnem, |
206 RegIndex _src1, uint8_t _imm8, RegIndex _dest, | 206 RegIndex _src1, uint16_t _imm8, RegIndex _dest, |
207 uint8_t _dataSize, uint16_t _ext) : 208 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 209 false, false, false, false, 210 _src1, _imm8, _dest, _dataSize, _ext, 211 %(op_class)s) 212 { 213 buildMe(); 214 } 215 | 207 uint8_t _dataSize, uint16_t _ext) : 208 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 209 false, false, false, false, 210 _src1, _imm8, _dest, _dataSize, _ext, 211 %(op_class)s) 212 { 213 buildMe(); 214 } 215 |
216 inline %(class_name)sImm::%(class_name)sImm( | 216 inline %(class_name)s::%(class_name)s( |
217 ExtMachInst machInst, const char * instMnem, 218 bool isMicro, bool isDelayed, bool isFirst, bool isLast, | 217 ExtMachInst machInst, const char * instMnem, 218 bool isMicro, bool isDelayed, bool isFirst, bool isLast, |
219 RegIndex _src1, uint8_t _imm8, RegIndex _dest, | 219 RegIndex _src1, uint16_t _imm8, RegIndex _dest, |
220 uint8_t _dataSize, uint16_t _ext) : 221 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 222 isMicro, isDelayed, isFirst, isLast, 223 _src1, _imm8, _dest, _dataSize, _ext, 224 %(op_class)s) 225 { 226 buildMe(); 227 } --- 77 unchanged lines hidden (view full) --- 305 306 # Make these empty strings so that concatenating onto 307 # them will always work. 308 header_output = "" 309 decoder_output = "" 310 exec_output = "" 311 312 # A function which builds the C++ classes that implement the microops | 220 uint8_t _dataSize, uint16_t _ext) : 221 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 222 isMicro, isDelayed, isFirst, isLast, 223 _src1, _imm8, _dest, _dataSize, _ext, 224 %(op_class)s) 225 { 226 buildMe(); 227 } --- 77 unchanged lines hidden (view full) --- 305 306 # Make these empty strings so that concatenating onto 307 # them will always work. 308 header_output = "" 309 decoder_output = "" 310 exec_output = "" 311 312 # A function which builds the C++ classes that implement the microops |
313 def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";"): | 313 def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";", imm=False): |
314 global header_output 315 global decoder_output 316 global exec_output 317 global microopClasses 318 319 iop = InstObjParams(name, Name, base, 320 {"code" : code, 321 "flag_code" : flagCode, 322 "cond_check" : condCheck, 323 "else_code" : elseCode}) | 314 global header_output 315 global decoder_output 316 global exec_output 317 global microopClasses 318 319 iop = InstObjParams(name, Name, base, 320 {"code" : code, 321 "flag_code" : flagCode, 322 "cond_check" : condCheck, 323 "else_code" : elseCode}) |
324 header_output += MicroRegOpDeclare.subst(iop) 325 decoder_output += MicroRegOpConstructor.subst(iop) 326 exec_output += MicroRegOpExecute.subst(iop) | 324 if imm: 325 header_output += MicroRegOpImmDeclare.subst(iop) 326 decoder_output += MicroRegOpImmConstructor.subst(iop) 327 exec_output += MicroRegOpImmExecute.subst(iop) 328 else: 329 header_output += MicroRegOpDeclare.subst(iop) 330 decoder_output += MicroRegOpConstructor.subst(iop) 331 exec_output += MicroRegOpExecute.subst(iop) |
327 328 329 checkCCFlagBits = "checkCondition(ccFlagBits)" 330 genCCFlagBits = \ 331 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 332 genCCFlagBitsSub = \ 333 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 334 genCCFlagBitsLogic = ''' --- 57 unchanged lines hidden (view full) --- 392 className = Name + 'Imm' 393 def __init__(self, dest, src1, src2, \ 394 flags=None, dataSize="env.dataSize"): 395 super(RegOpChildImm, self).__init__(dest, src1, src2, \ 396 flags, dataSize) 397 398 microopClasses[name + 'i'] = RegOpChildImm 399 | 332 333 334 checkCCFlagBits = "checkCondition(ccFlagBits)" 335 genCCFlagBits = \ 336 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 337 genCCFlagBitsSub = \ 338 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 339 genCCFlagBitsLogic = ''' --- 57 unchanged lines hidden (view full) --- 397 className = Name + 'Imm' 398 def __init__(self, dest, src1, src2, \ 399 flags=None, dataSize="env.dataSize"): 400 super(RegOpChildImm, self).__init__(dest, src1, src2, \ 401 flags, dataSize) 402 403 microopClasses[name + 'i'] = RegOpChildImm 404 |
400 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode); | 405 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \ 406 immCode, imm=True); |
401 setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", 402 immCode, flagCode=immFlagCode, | 407 setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", 408 immCode, flagCode=immFlagCode, |
403 condCheck=condCode, elseCode=elseCode); | 409 condCheck=condCode, elseCode=elseCode, imm=True); |
404 405 # This has it's own function because Wr ops have implicit destinations 406 def defineMicroRegOpWr(mnemonic, code, elseCode=";"): 407 Name = mnemonic 408 name = mnemonic.lower() 409 410 # Find op2 in each of the instruction definitions. Create two versions 411 # of the code, one with an integer operand, and one with an immediate --- 17 unchanged lines hidden (view full) --- 429 class RegOpChildImm(RegOpImm): 430 mnemonic = name + 'i' 431 className = Name + 'Imm' 432 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 433 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 434 435 microopClasses[name + 'i'] = RegOpChildImm 436 | 410 411 # This has it's own function because Wr ops have implicit destinations 412 def defineMicroRegOpWr(mnemonic, code, elseCode=";"): 413 Name = mnemonic 414 name = mnemonic.lower() 415 416 # Find op2 in each of the instruction definitions. Create two versions 417 # of the code, one with an integer operand, and one with an immediate --- 17 unchanged lines hidden (view full) --- 435 class RegOpChildImm(RegOpImm): 436 mnemonic = name + 'i' 437 className = Name + 'Imm' 438 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 439 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 440 441 microopClasses[name + 'i'] = RegOpChildImm 442 |
437 setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode); 438 setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, 439 condCheck = checkCCFlagBits, elseCode = elseCode); | 443 setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", \ 444 immCode, imm=True); 445 setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", \ 446 immCode, condCheck = checkCCFlagBits, elseCode = elseCode, \ 447 imm=True); |
440 441 # This has it's own function because Rd ops don't always have two parameters 442 def defineMicroRegOpRd(mnemonic, code): 443 Name = mnemonic 444 name = mnemonic.lower() 445 446 class RegOpChild(RegOp): | 448 449 # This has it's own function because Rd ops don't always have two parameters 450 def defineMicroRegOpRd(mnemonic, code): 451 Name = mnemonic 452 name = mnemonic.lower() 453 454 class RegOpChild(RegOp): |
455 className = Name 456 mnemonic = name |
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447 def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"): 448 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) | 457 def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"): 458 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) |
449 self.className = Name 450 self.mnemonic = name | |
451 452 microopClasses[name] = RegOpChild 453 454 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code); 455 456 def defineMicroRegOpImm(mnemonic, code, flagCode=""): 457 Name = mnemonic 458 name = mnemonic.lower() 459 code = immPick + code 460 461 class RegOpChild(RegOpImm): | 459 460 microopClasses[name] = RegOpChild 461 462 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code); 463 464 def defineMicroRegOpImm(mnemonic, code, flagCode=""): 465 Name = mnemonic 466 name = mnemonic.lower() 467 code = immPick + code 468 469 class RegOpChild(RegOpImm): |
462 def __init__(self, dest, src1, src2, dataSize="env.dataSize"): 463 super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize) 464 self.className = Name 465 self.mnemonic = name | 470 className = Name 471 mnemonic = name 472 def __init__(self, dest, src1, src2, \ 473 flags=None, dataSize="env.dataSize"): 474 super(RegOpChild, self).__init__(dest, \ 475 src1, src2, flags, dataSize) |
466 467 microopClasses[name] = RegOpChild 468 | 476 477 microopClasses[name] = RegOpChild 478 |
469 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code); | 479 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, imm=True); 480 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOpImm", \ 481 code, flagCode=flagCode, imm=True); |
470 | 482 |
483 def defineMicroRegOpRdImm(mnemonic, code, flagCode=""): 484 Name = mnemonic 485 name = mnemonic.lower() 486 code = immPick + code 487 488 class RegOpChildRdImm(RegOpImm): 489 className = Name 490 mnemonic = name 491 def __init__(self, dest, imm, flags=None, \ 492 dataSize="env.dataSize"): 493 super(RegOpChildRdImm, self).__init__(dest, \ 494 "NUM_INTREGS", imm, flags, dataSize) 495 496 microopClasses[name] = RegOpChildRdImm 497 498 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, imm=True); 499 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOpImm", \ 500 code, flagCode=flagCode, imm=True); 501 |
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471 defineMicroRegOp('Add', 'DestReg = merge(DestReg, psrc1 + op2, dataSize)') 472 defineMicroRegOp('Or', 'DestReg = merge(DestReg, psrc1 | op2, dataSize);', 473 flagCode = genCCFlagBitsLogic) 474 defineMicroRegOp('Adc', ''' 475 CCFlagBits flags = ccFlagBits; 476 DestReg = merge(DestReg, psrc1 + op2 + flags.CF, dataSize); 477 ''') 478 defineMicroRegOp('Sbb', ''' --- 136 unchanged lines hidden (view full) --- 615 ''') 616 617 defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;") 618 defineMicroRegOpWr('Br', 'nuIP = psrc1 + op2;', elseCode='nuIP = nuIP;') 619 defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2') 620 621 defineMicroRegOpRd('Rdip', 'DestReg = RIP') 622 defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits') | 502 defineMicroRegOp('Add', 'DestReg = merge(DestReg, psrc1 + op2, dataSize)') 503 defineMicroRegOp('Or', 'DestReg = merge(DestReg, psrc1 | op2, dataSize);', 504 flagCode = genCCFlagBitsLogic) 505 defineMicroRegOp('Adc', ''' 506 CCFlagBits flags = ccFlagBits; 507 DestReg = merge(DestReg, psrc1 + op2 + flags.CF, dataSize); 508 ''') 509 defineMicroRegOp('Sbb', ''' --- 136 unchanged lines hidden (view full) --- 646 ''') 647 648 defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;") 649 defineMicroRegOpWr('Br', 'nuIP = psrc1 + op2;', elseCode='nuIP = nuIP;') 650 defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2') 651 652 defineMicroRegOpRd('Rdip', 'DestReg = RIP') 653 defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits') |
623 defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8 + 0*psrc1);', \ 624 flagCode = genCCFlagBitsLogic) | 654 defineMicroRegOpRdImm('Ruflag', ''' 655 int flag = bits(ccFlagBits, (1 << imm8) + 0*psrc1); 656 DestReg = merge(DestReg, flag, dataSize); 657 ccFlagBits = ccFlagBits & ~EZFBit; 658 ccFlagBits = ccFlagBits | ((flag == 0) ? EZFBit : 0); 659 ''') |
625 626 defineMicroRegOpImm('Sext', ''' 627 IntReg val = psrc1; 628 int sign_bit = bits(val, imm8-1, imm8-1); 629 val = sign_bit ? (val | ~mask(imm8)) : val; 630 DestReg = merge(DestReg, val, dataSize);''') 631 632 defineMicroRegOpImm('Zext', 'DestReg = bits(psrc1, imm8-1, 0);') 633}}; | 660 661 defineMicroRegOpImm('Sext', ''' 662 IntReg val = psrc1; 663 int sign_bit = bits(val, imm8-1, imm8-1); 664 val = sign_bit ? (val | ~mask(imm8)) : val; 665 DestReg = merge(DestReg, val, dataSize);''') 666 667 defineMicroRegOpImm('Zext', 'DestReg = bits(psrc1, imm8-1, 0);') 668}}; |