regop.isa (4868:99d4946469a1) | regop.isa (4950:f5f19784acf1) |
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1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 439 unchanged lines hidden (view full) --- 448 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 449 self.className = Name 450 self.mnemonic = name 451 452 microopClasses[name] = RegOpChild 453 454 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code); 455 | 1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 439 unchanged lines hidden (view full) --- 448 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 449 self.className = Name 450 self.mnemonic = name 451 452 microopClasses[name] = RegOpChild 453 454 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code); 455 |
456 def defineMicroRegOpImm(mnemonic, code): | 456 def defineMicroRegOpImm(mnemonic, code, flagCode=""): |
457 Name = mnemonic 458 name = mnemonic.lower() 459 code = immPick + code 460 461 class RegOpChild(RegOpImm): 462 def __init__(self, dest, src1, src2, dataSize="env.dataSize"): 463 super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize) 464 self.className = Name --- 145 unchanged lines hidden (view full) --- 610 dataSize * 8 - shiftAmt + 1); 611 DestReg = merge(DestReg, top | bottom, dataSize); 612 } 613 else 614 DestReg = DestReg; 615 ''') 616 617 defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;") | 457 Name = mnemonic 458 name = mnemonic.lower() 459 code = immPick + code 460 461 class RegOpChild(RegOpImm): 462 def __init__(self, dest, src1, src2, dataSize="env.dataSize"): 463 super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize) 464 self.className = Name --- 145 unchanged lines hidden (view full) --- 610 dataSize * 8 - shiftAmt + 1); 611 DestReg = merge(DestReg, top | bottom, dataSize); 612 } 613 else 614 DestReg = DestReg; 615 ''') 616 617 defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;") |
618 defineMicroRegOpWr('Br', 'nuIP = psrc1 + op2;', elseCode='nuIP = nuIP;') |
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618 defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2') 619 620 defineMicroRegOpRd('Rdip', 'DestReg = RIP') 621 defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits') | 619 defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2') 620 621 defineMicroRegOpRd('Rdip', 'DestReg = RIP') 622 defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits') |
622 defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8);', \ | 623 defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8 + 0*psrc1);', \ |
623 flagCode = genCCFlagBitsLogic) 624 625 defineMicroRegOpImm('Sext', ''' 626 IntReg val = psrc1; 627 int sign_bit = bits(val, imm8-1, imm8-1); 628 val = sign_bit ? (val | ~mask(imm8)) : val; 629 DestReg = merge(DestReg, val, dataSize);''') 630 631 defineMicroRegOpImm('Zext', 'DestReg = bits(psrc1, imm8-1, 0);') 632}}; | 624 flagCode = genCCFlagBitsLogic) 625 626 defineMicroRegOpImm('Sext', ''' 627 IntReg val = psrc1; 628 int sign_bit = bits(val, imm8-1, imm8-1); 629 val = sign_bit ? (val | ~mask(imm8)) : val; 630 DestReg = merge(DestReg, val, dataSize);''') 631 632 defineMicroRegOpImm('Zext', 'DestReg = bits(psrc1, imm8-1, 0);') 633}}; |