regop.isa (4728:d60b98171bef) regop.isa (4732:9fdd1a5ab692)
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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376 super(RegOpChildImm, self).__init__(dest, src1, src2, flags, dataSize)
377
378 microopClasses[name + 'i'] = RegOpChildImm
379
380 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode);
381 setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
382 flagCode = immFlagCode, condCheck = condCode, elseCode = elseCode);
383
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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376 super(RegOpChildImm, self).__init__(dest, src1, src2, flags, dataSize)
377
378 microopClasses[name + 'i'] = RegOpChildImm
379
380 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode);
381 setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
382 flagCode = immFlagCode, condCheck = condCode, elseCode = elseCode);
383
384 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
385 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
386 defineMicroRegOp('Adc', '''
387 CCFlagBits flags = ccFlagBits;
388 DestReg = merge(DestReg, SrcReg1 + op2 + flags.CF, dataSize);
389 ''')
390 defineMicroRegOp('Sbb', '''
391 CCFlagBits flags = ccFlagBits;
392 DestReg = merge(DestReg, SrcReg1 - op2 - flags.CF, dataSize);
393 ''', True)
394 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
395 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', True)
396 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
397 # defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', True)
398 defineMicroRegOp('Mul1s', 'DestReg = merge(DestReg, DestReg * op2, dataSize)')
399 defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)',
400 elseCode='DestReg=DestReg;', cc=True)
401
402 # Shift instructions
403 defineMicroRegOp('Sll', '''
404 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
405 DestReg = merge(DestReg, SrcReg1 << shiftAmt, dataSize);
406 ''')
407 # There are special rules for the flag for a single bit shift
408 defineMicroRegOp('Bll', '''
409 DestReg = merge(DestReg, SrcReg1 << 1, dataSize);
410 ''')
411
412 # This has it's own function because Wr ops have implicit destinations
413 def defineMicroRegOpWr(mnemonic, code, elseCode=";"):
414 Name = mnemonic
415 name = mnemonic.lower()
416
417 # Find op2 in each of the instruction definitions. Create two versions
418 # of the code, one with an integer operand, and one with an immediate
419 # operand.

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440 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
441
442 microopClasses[name + 'i'] = RegOpChildImm
443
444 setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode);
445 setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
446 condCheck = checkCCFlagBits, elseCode = elseCode);
447
384 # This has it's own function because Wr ops have implicit destinations
385 def defineMicroRegOpWr(mnemonic, code, elseCode=";"):
386 Name = mnemonic
387 name = mnemonic.lower()
388
389 # Find op2 in each of the instruction definitions. Create two versions
390 # of the code, one with an integer operand, and one with an immediate
391 # operand.

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412 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
413
414 microopClasses[name + 'i'] = RegOpChildImm
415
416 setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode);
417 setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
418 condCheck = checkCCFlagBits, elseCode = elseCode);
419
448 defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2', elseCode="RIP = RIP;")
449
450 # This has it's own function because Rd ops don't always have two parameters
451 def defineMicroRegOpRd(mnemonic, code):
452 Name = mnemonic
453 name = mnemonic.lower()
454
455 class RegOpChild(RegOp):
456 def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
457 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
458 self.className = Name
459 self.mnemonic = name
460
461 microopClasses[name] = RegOpChild
462
463 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code);
464
420 # This has it's own function because Rd ops don't always have two parameters
421 def defineMicroRegOpRd(mnemonic, code):
422 Name = mnemonic
423 name = mnemonic.lower()
424
425 class RegOpChild(RegOp):
426 def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
427 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
428 self.className = Name
429 self.mnemonic = name
430
431 microopClasses[name] = RegOpChild
432
433 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code);
434
465 defineMicroRegOpRd('Rdip', 'DestReg = RIP')
466
467 def defineMicroRegOpImm(mnemonic, code):
468 Name = mnemonic
469 name = mnemonic.lower()
470
471 class RegOpChild(RegOpImm):
472 def __init__(self, dest, src1, src2, dataSize="env.dataSize"):
473 super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize)
474 self.className = Name
475 self.mnemonic = name
476
477 microopClasses[name] = RegOpChild
478
479 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code);
480
435 def defineMicroRegOpImm(mnemonic, code):
436 Name = mnemonic
437 name = mnemonic.lower()
438
439 class RegOpChild(RegOpImm):
440 def __init__(self, dest, src1, src2, dataSize="env.dataSize"):
441 super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize)
442 self.className = Name
443 self.mnemonic = name
444
445 microopClasses[name] = RegOpChild
446
447 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code);
448
449 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
450 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
451 defineMicroRegOp('Adc', '''
452 CCFlagBits flags = ccFlagBits;
453 DestReg = merge(DestReg, SrcReg1 + op2 + flags.CF, dataSize);
454 ''')
455 defineMicroRegOp('Sbb', '''
456 CCFlagBits flags = ccFlagBits;
457 DestReg = merge(DestReg, SrcReg1 - op2 - flags.CF, dataSize);
458 ''', True)
459 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
460 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', True)
461 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
462 # defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', True)
463 defineMicroRegOp('Mul1s', 'DestReg = merge(DestReg, DestReg * op2, dataSize)')
464 defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)',
465 elseCode='DestReg=DestReg;', cc=True)
466
467 # Shift instructions
468 defineMicroRegOp('Sll', '''
469 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
470 DestReg = merge(DestReg, SrcReg1 << shiftAmt, dataSize);
471 ''')
472 defineMicroRegOp('Srl', '''
473 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
474 // Because what happens to the bits shift -in- on a right shift
475 // is not defined in the C/C++ standard, we have to mask them out
476 // to be sure they're zero.
477 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
478 DestReg = merge(DestReg, (SrcReg1 >> shiftAmt) & logicalMask, dataSize);
479 ''')
480 defineMicroRegOp('Sra', '''
481 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
482 // Because what happens to the bits shift -in- on a right shift
483 // is not defined in the C/C++ standard, we have to sign extend
484 // them manually to be sure.
485 uint64_t arithMask =
486 -bits(op2, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
487 DestReg = merge(DestReg, (SrcReg1 >> shiftAmt) | arithMask, dataSize);
488 ''')
489 defineMicroRegOp('Ror', '''
490 uint8_t shiftAmt =
491 (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
492 if(shiftAmt)
493 {
494 uint64_t top = SrcReg1 << (dataSize * 8 - shiftAmt);
495 uint64_t bottom = bits(SrcReg1, dataSize * 8, shiftAmt);
496 DestReg = merge(DestReg, top | bottom, dataSize);
497 }
498 else
499 DestReg = DestReg;
500 ''')
501 defineMicroRegOp('Rcr', '''
502 ''')
503 defineMicroRegOp('Rol', '''
504 uint8_t shiftAmt =
505 (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
506 if(shiftAmt)
507 {
508 uint64_t top = SrcReg1 << shiftAmt;
509 uint64_t bottom =
510 bits(SrcReg1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
511 DestReg = merge(DestReg, top | bottom, dataSize);
512 }
513 else
514 DestReg = DestReg;
515 ''')
516 defineMicroRegOp('Rcl', '''
517 ''')
518
519 defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2', elseCode="RIP = RIP;")
520
521 defineMicroRegOpRd('Rdip', 'DestReg = RIP')
522
481 defineMicroRegOpImm('Sext', '''
482 IntReg val = SrcReg1;
483 int sign_bit = bits(val, imm8-1, imm8-1);
484 val = sign_bit ? (val | ~mask(imm8)) : val;
485 DestReg = merge(DestReg, val, dataSize);''')
486
487 defineMicroRegOpImm('Zext', 'DestReg = bits(SrcReg1, imm8-1, 0);')
488}};
523 defineMicroRegOpImm('Sext', '''
524 IntReg val = SrcReg1;
525 int sign_bit = bits(val, imm8-1, imm8-1);
526 val = sign_bit ? (val | ~mask(imm8)) : val;
527 DestReg = merge(DestReg, val, dataSize);''')
528
529 defineMicroRegOpImm('Zext', 'DestReg = bits(SrcReg1, imm8-1, 0);')
530}};