regop.isa (4712:79b4c64296ce) regop.isa (4714:5e9f906ea0a0)
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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304
305 # Make these empty strings so that concatenating onto
306 # them will always work.
307 header_output = ""
308 decoder_output = ""
309 exec_output = ""
310
311 # A function which builds the C++ classes that implement the microops
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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304
305 # Make these empty strings so that concatenating onto
306 # them will always work.
307 header_output = ""
308 decoder_output = ""
309 exec_output = ""
310
311 # A function which builds the C++ classes that implement the microops
312 def setUpMicroRegOp(name, Name, base, code, flagCode, condCheck, elseCode):
312 def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";"):
313 global header_output
314 global decoder_output
315 global exec_output
316 global microopClasses
317
318 iop = InstObjParams(name, Name, base,
319 {"code" : code,
320 "flag_code" : flagCode,

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326
327
328 checkCCFlagBits = "checkCondition(ccFlagBits)"
329 genCCFlagBits = "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, %s);"
330
331
332 # This creates a python representations of a microop which are a cross
333 # product of reg/immediate and flag/no flag versions.
313 global header_output
314 global decoder_output
315 global exec_output
316 global microopClasses
317
318 iop = InstObjParams(name, Name, base,
319 {"code" : code,
320 "flag_code" : flagCode,

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326
327
328 checkCCFlagBits = "checkCondition(ccFlagBits)"
329 genCCFlagBits = "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, %s);"
330
331
332 # This creates a python representations of a microop which are a cross
333 # product of reg/immediate and flag/no flag versions.
334 def defineMicroRegOp(mnemonic, code, secondSrc = "op2", cc=False, elseCode=";"):
334 def defineMicroRegOp(mnemonic, code, subtract = False, cc=False, elseCode=";"):
335 Name = mnemonic
336 name = mnemonic.lower()
337
338 # Find op2 in each of the instruction definitions. Create two versions
339 # of the code, one with an integer operand, and one with an immediate
340 # operand.
341 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
342 regCode = matcher.sub("SrcReg2", code)
343 immCode = matcher.sub("imm8", code)
344
335 Name = mnemonic
336 name = mnemonic.lower()
337
338 # Find op2 in each of the instruction definitions. Create two versions
339 # of the code, one with an integer operand, and one with an immediate
340 # operand.
341 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
342 regCode = matcher.sub("SrcReg2", code)
343 immCode = matcher.sub("imm8", code)
344
345 if subtract:
346 secondSrc = "-op2, true"
347 else:
348 secondSrc = "op2"
349
345 if not cc:
346 flagCode = genCCFlagBits % secondSrc
347 condCode = "true"
348 else:
349 flagCode = ""
350 condCode = checkCCFlagBits
351
352 regFlagCode = matcher.sub("SrcReg2", flagCode)
353 immFlagCode = matcher.sub("imm8", flagCode)
354
355 class RegOpChild(RegOp):
356 mnemonic = name
357 className = Name
358 def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"):
359 super(RegOpChild, self).__init__(dest, src1, src2, flags, dataSize)
360
361 microopClasses[name] = RegOpChild
362
350 if not cc:
351 flagCode = genCCFlagBits % secondSrc
352 condCode = "true"
353 else:
354 flagCode = ""
355 condCode = checkCCFlagBits
356
357 regFlagCode = matcher.sub("SrcReg2", flagCode)
358 immFlagCode = matcher.sub("imm8", flagCode)
359
360 class RegOpChild(RegOp):
361 mnemonic = name
362 className = Name
363 def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"):
364 super(RegOpChild, self).__init__(dest, src1, src2, flags, dataSize)
365
366 microopClasses[name] = RegOpChild
367
363 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true", elseCode);
364 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, regFlagCode, condCode, elseCode);
368 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
369 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode,
370 flagCode = regFlagCode, condCheck = condCode, elseCode = elseCode);
365
366 class RegOpChildImm(RegOpImm):
367 mnemonic = name + 'i'
368 className = Name + 'Imm'
369 def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"):
370 super(RegOpChildImm, self).__init__(dest, src1, src2, flags, dataSize)
371
372 microopClasses[name + 'i'] = RegOpChildImm
373
371
372 class RegOpChildImm(RegOpImm):
373 mnemonic = name + 'i'
374 className = Name + 'Imm'
375 def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"):
376 super(RegOpChildImm, self).__init__(dest, src1, src2, flags, dataSize)
377
378 microopClasses[name + 'i'] = RegOpChildImm
379
374 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true", elseCode);
375 setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, immFlagCode, condCode, elseCode);
380 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode);
381 setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
382 flagCode = immFlagCode, condCheck = condCode, elseCode = elseCode);
376
377 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
378 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
379 defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
383
384 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
385 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
386 defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
380 defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2')
387 defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', True)
381 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
388 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
382 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2')
389 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', True)
383 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
390 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
384 defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', '-op2')
391 defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', True)
392 defineMicroRegOp('mul1s', 'DestReg = merge(DestReg, DestReg * op2, dataSize)')
385 defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)',
386 elseCode='DestReg=DestReg;', cc=True)
387
388 # This has it's own function because Wr ops have implicit destinations
389 def defineMicroRegOpWr(mnemonic, code, elseCode=";"):
390 Name = mnemonic
391 name = mnemonic.lower()
392

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400 class RegOpChild(RegOp):
401 mnemonic = name
402 className = Name
403 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
404 super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
405
406 microopClasses[name] = RegOpChild
407
393 defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)',
394 elseCode='DestReg=DestReg;', cc=True)
395
396 # This has it's own function because Wr ops have implicit destinations
397 def defineMicroRegOpWr(mnemonic, code, elseCode=";"):
398 Name = mnemonic
399 name = mnemonic.lower()
400

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408 class RegOpChild(RegOp):
409 mnemonic = name
410 className = Name
411 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
412 super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
413
414 microopClasses[name] = RegOpChild
415
408 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true", elseCode);
409 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, "", checkCCFlagBits, elseCode);
416 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
417 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode,
418 condCheck = checkCCFlagBits, elseCode = elseCode);
410
411 class RegOpChildImm(RegOpImm):
412 mnemonic = name + 'i'
413 className = Name + 'Imm'
414 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
415 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
416
417 microopClasses[name + 'i'] = RegOpChildImm
418
419
420 class RegOpChildImm(RegOpImm):
421 mnemonic = name + 'i'
422 className = Name + 'Imm'
423 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
424 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
425
426 microopClasses[name + 'i'] = RegOpChildImm
427
419 setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true", elseCode);
420 setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, "", checkCCFlagBits, elseCode);
428 setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode);
429 setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
430 condCheck = checkCCFlagBits, elseCode = elseCode);
421
422 defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2', elseCode="RIP = RIP;")
423
424 # This has it's own function because Rd ops don't always have two parameters
425 def defineMicroRegOpRd(mnemonic, code):
426 Name = mnemonic
427 name = mnemonic.lower()
428
429 class RegOpChild(RegOp):
430 def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
431 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
432 self.className = Name
433 self.mnemonic = name
434
435 microopClasses[name] = RegOpChild
436
431
432 defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2', elseCode="RIP = RIP;")
433
434 # This has it's own function because Rd ops don't always have two parameters
435 def defineMicroRegOpRd(mnemonic, code):
436 Name = mnemonic
437 name = mnemonic.lower()
438
439 class RegOpChild(RegOp):
440 def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
441 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
442 self.className = Name
443 self.mnemonic = name
444
445 microopClasses[name] = RegOpChild
446
437 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, "", "true", ";");
447 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code);
438
439 defineMicroRegOpRd('Rdip', 'DestReg = RIP')
440
441 def defineMicroRegOpImm(mnemonic, code):
442 Name = mnemonic
443 name = mnemonic.lower()
444
445 class RegOpChild(RegOpImm):
446 def __init__(self, dest, src1, src2, dataSize="env.dataSize"):
447 super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize)
448 self.className = Name
449 self.mnemonic = name
450
451 microopClasses[name] = RegOpChild
452
448
449 defineMicroRegOpRd('Rdip', 'DestReg = RIP')
450
451 def defineMicroRegOpImm(mnemonic, code):
452 Name = mnemonic
453 name = mnemonic.lower()
454
455 class RegOpChild(RegOpImm):
456 def __init__(self, dest, src1, src2, dataSize="env.dataSize"):
457 super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize)
458 self.className = Name
459 self.mnemonic = name
460
461 microopClasses[name] = RegOpChild
462
453 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, "", "true", ";");
463 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code);
454
455 defineMicroRegOpImm('Sext', '''
456 IntReg val = SrcReg1;
457 int sign_bit = bits(val, imm8-1, imm8-1);
458 val = sign_bit ? (val | ~mask(imm8)) : val;
459 DestReg = merge(DestReg, val, dataSize);''')
464
465 defineMicroRegOpImm('Sext', '''
466 IntReg val = SrcReg1;
467 int sign_bit = bits(val, imm8-1, imm8-1);
468 val = sign_bit ? (val | ~mask(imm8)) : val;
469 DestReg = merge(DestReg, val, dataSize);''')
470
471 defineMicroRegOpImm('Zext', 'DestReg = bits(SrcReg1, imm8-1, 0);')
460}};
472}};