regop.isa (4701:6086c14956da) | regop.isa (4708:efa060dd6f3c) |
---|---|
1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 59 unchanged lines hidden (view full) --- 68 %(op_decl)s; 69 %(op_rd)s; 70 71 if(%(cond_check)s) 72 { 73 %(code)s; 74 %(flag_code)s; 75 } | 1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 59 unchanged lines hidden (view full) --- 68 %(op_decl)s; 69 %(op_rd)s; 70 71 if(%(cond_check)s) 72 { 73 %(code)s; 74 %(flag_code)s; 75 } |
76 else 77 { 78 %(else_code)s; 79 } |
|
76 77 //Write the resulting state to the execution context 78 if(fault == NoFault) 79 { 80 %(op_wb)s; 81 } 82 return fault; 83 } --- 8 unchanged lines hidden (view full) --- 92 %(op_decl)s; 93 %(op_rd)s; 94 95 if(%(cond_check)s) 96 { 97 %(code)s; 98 %(flag_code)s; 99 } | 80 81 //Write the resulting state to the execution context 82 if(fault == NoFault) 83 { 84 %(op_wb)s; 85 } 86 return fault; 87 } --- 8 unchanged lines hidden (view full) --- 96 %(op_decl)s; 97 %(op_rd)s; 98 99 if(%(cond_check)s) 100 { 101 %(code)s; 102 %(flag_code)s; 103 } |
104 else 105 { 106 %(else_code)s; 107 } |
|
100 101 //Write the resulting state to the execution context 102 if(fault == NoFault) 103 { 104 %(op_wb)s; 105 } 106 return fault; 107 } --- 188 unchanged lines hidden (view full) --- 296 297 # Make these empty strings so that concatenating onto 298 # them will always work. 299 header_output = "" 300 decoder_output = "" 301 exec_output = "" 302 303 # A function which builds the C++ classes that implement the microops | 108 109 //Write the resulting state to the execution context 110 if(fault == NoFault) 111 { 112 %(op_wb)s; 113 } 114 return fault; 115 } --- 188 unchanged lines hidden (view full) --- 304 305 # Make these empty strings so that concatenating onto 306 # them will always work. 307 header_output = "" 308 decoder_output = "" 309 exec_output = "" 310 311 # A function which builds the C++ classes that implement the microops |
304 def setUpMicroRegOp(name, Name, base, code, flagCode, condCheck): | 312 def setUpMicroRegOp(name, Name, base, code, flagCode, condCheck, elseCode): |
305 global header_output 306 global decoder_output 307 global exec_output 308 global microopClasses 309 310 iop = InstObjParams(name, Name, base, 311 {"code" : code, 312 "flag_code" : flagCode, | 313 global header_output 314 global decoder_output 315 global exec_output 316 global microopClasses 317 318 iop = InstObjParams(name, Name, base, 319 {"code" : code, 320 "flag_code" : flagCode, |
313 "cond_check" : condCheck}) | 321 "cond_check" : condCheck, 322 "else_code" : elseCode}) |
314 header_output += MicroRegOpDeclare.subst(iop) 315 decoder_output += MicroRegOpConstructor.subst(iop) 316 exec_output += MicroRegOpExecute.subst(iop) 317 318 319 checkCCFlagBits = "checkCondition(ccFlagBits)" 320 genCCFlagBits = "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, %s);" 321 322 323 # This creates a python representations of a microop which are a cross 324 # product of reg/immediate and flag/no flag versions. | 323 header_output += MicroRegOpDeclare.subst(iop) 324 decoder_output += MicroRegOpConstructor.subst(iop) 325 exec_output += MicroRegOpExecute.subst(iop) 326 327 328 checkCCFlagBits = "checkCondition(ccFlagBits)" 329 genCCFlagBits = "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, %s);" 330 331 332 # This creates a python representations of a microop which are a cross 333 # product of reg/immediate and flag/no flag versions. |
325 def defineMicroRegOp(mnemonic, code, secondSrc = "op2", cc=False): | 334 def defineMicroRegOp(mnemonic, code, secondSrc = "op2", cc=False, elseCode=";"): |
326 Name = mnemonic 327 name = mnemonic.lower() 328 329 # Find op2 in each of the instruction definitions. Create two versions 330 # of the code, one with an integer operand, and one with an immediate 331 # operand. 332 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 333 regCode = matcher.sub("SrcReg2", code) --- 12 unchanged lines hidden (view full) --- 346 class RegOpChild(RegOp): 347 mnemonic = name 348 className = Name 349 def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"): 350 super(RegOpChild, self).__init__(dest, src1, src2, flags, dataSize) 351 352 microopClasses[name] = RegOpChild 353 | 335 Name = mnemonic 336 name = mnemonic.lower() 337 338 # Find op2 in each of the instruction definitions. Create two versions 339 # of the code, one with an integer operand, and one with an immediate 340 # operand. 341 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 342 regCode = matcher.sub("SrcReg2", code) --- 12 unchanged lines hidden (view full) --- 355 class RegOpChild(RegOp): 356 mnemonic = name 357 className = Name 358 def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"): 359 super(RegOpChild, self).__init__(dest, src1, src2, flags, dataSize) 360 361 microopClasses[name] = RegOpChild 362 |
354 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true"); 355 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, regFlagCode, condCode); | 363 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true", elseCode); 364 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, regFlagCode, condCode, elseCode); |
356 357 class RegOpChildImm(RegOpImm): 358 mnemonic = name + 'i' 359 className = Name + 'Imm' 360 def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"): 361 super(RegOpChildImm, self).__init__(dest, src1, src2, flags, dataSize) 362 363 microopClasses[name + 'i'] = RegOpChildImm 364 | 365 366 class RegOpChildImm(RegOpImm): 367 mnemonic = name + 'i' 368 className = Name + 'Imm' 369 def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"): 370 super(RegOpChildImm, self).__init__(dest, src1, src2, flags, dataSize) 371 372 microopClasses[name + 'i'] = RegOpChildImm 373 |
365 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true"); 366 setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, immFlagCode, condCode); | 374 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true", elseCode); 375 setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, immFlagCode, condCode, elseCode); |
367 368 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') 369 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') 370 defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') 371 defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2') 372 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') 373 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2') 374 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') 375 defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', '-op2') | 376 377 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') 378 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') 379 defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') 380 defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2') 381 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') 382 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2') 383 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') 384 defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', '-op2') |
376 defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', cc=True) | 385 defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', 386 elseCode='DestReg=DestReg;', cc=True) |
377 378 # This has it's own function because Wr ops have implicit destinations | 387 388 # This has it's own function because Wr ops have implicit destinations |
379 def defineMicroRegOpWr(mnemonic, code): | 389 def defineMicroRegOpWr(mnemonic, code, elseCode=";"): |
380 Name = mnemonic 381 name = mnemonic.lower() 382 383 # Find op2 in each of the instruction definitions. Create two versions 384 # of the code, one with an integer operand, and one with an immediate 385 # operand. 386 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 387 regCode = matcher.sub("SrcReg2", code) 388 immCode = matcher.sub("imm8", code) 389 390 class RegOpChild(RegOp): 391 mnemonic = name 392 className = Name 393 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 394 super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 395 396 microopClasses[name] = RegOpChild 397 | 390 Name = mnemonic 391 name = mnemonic.lower() 392 393 # Find op2 in each of the instruction definitions. Create two versions 394 # of the code, one with an integer operand, and one with an immediate 395 # operand. 396 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 397 regCode = matcher.sub("SrcReg2", code) 398 immCode = matcher.sub("imm8", code) 399 400 class RegOpChild(RegOp): 401 mnemonic = name 402 className = Name 403 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 404 super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 405 406 microopClasses[name] = RegOpChild 407 |
398 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true"); 399 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, "", checkCCFlagBits); | 408 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true", elseCode); 409 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, "", checkCCFlagBits, elseCode); |
400 401 class RegOpChildImm(RegOpImm): | 410 411 class RegOpChildImm(RegOpImm): |
402 mnemonic = name 403 className = Name | 412 mnemonic = name + 'i' 413 className = Name + 'Imm' |
404 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 405 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 406 407 microopClasses[name + 'i'] = RegOpChildImm 408 | 414 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 415 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 416 417 microopClasses[name + 'i'] = RegOpChildImm 418 |
409 setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true"); 410 setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, "", checkCCFlagBits); | 419 setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true", elseCode); 420 setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, "", checkCCFlagBits, elseCode); |
411 | 421 |
412 defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2') | 422 defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2', elseCode="RIP = RIP;") |
413 414 # This has it's own function because Rd ops don't always have two parameters 415 def defineMicroRegOpRd(mnemonic, code): 416 Name = mnemonic 417 name = mnemonic.lower() 418 419 class RegOpChild(RegOp): 420 def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"): 421 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 422 self.className = Name 423 self.mnemonic = name 424 425 microopClasses[name] = RegOpChild 426 | 423 424 # This has it's own function because Rd ops don't always have two parameters 425 def defineMicroRegOpRd(mnemonic, code): 426 Name = mnemonic 427 name = mnemonic.lower() 428 429 class RegOpChild(RegOp): 430 def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"): 431 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 432 self.className = Name 433 self.mnemonic = name 434 435 microopClasses[name] = RegOpChild 436 |
427 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, "", "true"); | 437 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, "", "true", ";"); |
428 429 defineMicroRegOpRd('Rdip', 'DestReg = RIP') 430 431 def defineMicroRegOpImm(mnemonic, code): 432 Name = mnemonic 433 name = mnemonic.lower() 434 435 class RegOpChild(RegOpImm): 436 def __init__(self, dest, src1, src2, dataSize="env.dataSize"): 437 super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize) 438 self.className = Name 439 self.mnemonic = name 440 441 microopClasses[name] = RegOpChild 442 | 438 439 defineMicroRegOpRd('Rdip', 'DestReg = RIP') 440 441 def defineMicroRegOpImm(mnemonic, code): 442 Name = mnemonic 443 name = mnemonic.lower() 444 445 class RegOpChild(RegOpImm): 446 def __init__(self, dest, src1, src2, dataSize="env.dataSize"): 447 super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize) 448 self.className = Name 449 self.mnemonic = name 450 451 microopClasses[name] = RegOpChild 452 |
443 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, "", "true"); | 453 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, "", "true", ";"); |
444 445 defineMicroRegOpImm('Sext', ''' 446 IntReg val = SrcReg1; 447 int sign_bit = bits(val, imm8-1, imm8-1); 448 val = sign_bit ? (val | ~mask(imm8)) : val; 449 DestReg = merge(DestReg, val, dataSize);''') 450}}; | 454 455 defineMicroRegOpImm('Sext', ''' 456 IntReg val = SrcReg1; 457 int sign_bit = bits(val, imm8-1, imm8-1); 458 val = sign_bit ? (val | ~mask(imm8)) : val; 459 DestReg = merge(DestReg, val, dataSize);''') 460}}; |