regop.isa (4612:a29c0616839d) regop.isa (4679:0b39fa8f5eb8)
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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54// Authors: Gabe Black
55
56//////////////////////////////////////////////////////////////////////////
57//
58// RegOp Microop templates
59//
60//////////////////////////////////////////////////////////////////////////
61
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

--- 45 unchanged lines hidden (view full) ---

54// Authors: Gabe Black
55
56//////////////////////////////////////////////////////////////////////////
57//
58// RegOp Microop templates
59//
60//////////////////////////////////////////////////////////////////////////
61
62output header {{
63 /**
64 * Base classes for RegOps which provides a generateDisassembly method.
65 */
66 class RegOp : public X86MicroopBase
67 {
68 protected:
69 const RegIndex src1;
70 const RegIndex src2;
71 const RegIndex dest;
72 const bool setStatus;
73 const uint8_t dataSize;
74 const uint8_t ext;
75
76 // Constructor
77 RegOp(ExtMachInst _machInst,
78 const char *mnem, const char *_instMnem,
79 bool isMicro, bool isDelayed,
80 bool isFirst, bool isLast,
81 RegIndex _src1, RegIndex _src2, RegIndex _dest,
82 bool _setStatus, uint8_t _dataSize, uint8_t _ext,
83 OpClass __opClass) :
84 X86MicroopBase(_machInst, mnem, _instMnem,
85 isMicro, isDelayed, isFirst, isLast,
86 __opClass),
87 src1(_src1), src2(_src2), dest(_dest),
88 setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
89 {
90 }
91
92 std::string generateDisassembly(Addr pc,
93 const SymbolTable *symtab) const;
94 };
95
96 class RegOpImm : public X86MicroopBase
97 {
98 protected:
99 const RegIndex src1;
100 const uint8_t imm8;
101 const RegIndex dest;
102 const bool setStatus;
103 const uint8_t dataSize;
104 const uint8_t ext;
105
106 // Constructor
107 RegOpImm(ExtMachInst _machInst,
108 const char * mnem, const char *_instMnem,
109 bool isMicro, bool isDelayed,
110 bool isFirst, bool isLast,
111 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
112 bool _setStatus, uint8_t _dataSize, uint8_t _ext,
113 OpClass __opClass) :
114 X86MicroopBase(_machInst, mnem, _instMnem,
115 isMicro, isDelayed, isFirst, isLast,
116 __opClass),
117 src1(_src1), imm8(_imm8), dest(_dest),
118 setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
119 {
120 }
121
122 std::string generateDisassembly(Addr pc,
123 const SymbolTable *symtab) const;
124 };
125}};
126
127output decoder {{
128 std::string RegOp::generateDisassembly(Addr pc,
129 const SymbolTable *symtab) const
130 {
131 std::stringstream response;
132
133 printMnemonic(response, instMnem, mnemonic);
134 printReg(response, dest);
135 response << ", ";
136 printReg(response, src1);
137 response << ", ";
138 printReg(response, src2);
139 return response.str();
140 }
141
142 std::string RegOpImm::generateDisassembly(Addr pc,
143 const SymbolTable *symtab) const
144 {
145 std::stringstream response;
146
147 printMnemonic(response, instMnem, mnemonic);
148 printReg(response, dest);
149 response << ", ";
150 printReg(response, src1);
151 ccprintf(response, ", %#x", imm8);
152 return response.str();
153 }
154}};
155
156def template MicroRegOpExecute {{
157 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
158 Trace::InstRecord *traceData) const
159 {
160 Fault fault = NoFault;
161
162 %(op_decl)s;
163 %(op_rd)s;

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386
387 # Build the all register version of this micro op
388 class RegOpChild(RegOp):
389 def __init__(self, dest, src1, src2, setStatus=False):
390 super(RegOpChild, self).__init__(dest, src1, src2, setStatus)
391 self.className = Name
392 self.mnemonic = name
393
62def template MicroRegOpExecute {{
63 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
64 Trace::InstRecord *traceData) const
65 {
66 Fault fault = NoFault;
67
68 %(op_decl)s;
69 %(op_rd)s;

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292
293 # Build the all register version of this micro op
294 class RegOpChild(RegOp):
295 def __init__(self, dest, src1, src2, setStatus=False):
296 super(RegOpChild, self).__init__(dest, src1, src2, setStatus)
297 self.className = Name
298 self.mnemonic = name
299
394 setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, flagCode);
300 setUpMicroRegOp(name, Name, "X86ISA::RegOp", \
301 regCode, RegOpChild, flagCode);
395
396 # Build the immediate version of this micro op
397 class RegOpChildImm(RegOpImm):
398 def __init__(self, dest, src1, src2, setStatus=False):
399 super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus)
400 self.className = Name + "Imm"
401 self.mnemonic = name + "i"
402
302
303 # Build the immediate version of this micro op
304 class RegOpChildImm(RegOpImm):
305 def __init__(self, dest, src1, src2, setStatus=False):
306 super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus)
307 self.className = Name + "Imm"
308 self.mnemonic = name + "i"
309
403 setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, flagCode);
310 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
311 immCode, RegOpChildImm, flagCode);
404
405 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF
406 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "")
407 defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF
408 defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF
409 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "")
410 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF
411 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "")

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426
427 # Build the all register version of this micro op
428 class RegOpChild(RegOp):
429 def __init__(self, src1, src2):
430 super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False)
431 self.className = Name
432 self.mnemonic = name
433
312
313 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF
314 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "")
315 defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF
316 defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF
317 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "")
318 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF
319 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "")

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334
335 # Build the all register version of this micro op
336 class RegOpChild(RegOp):
337 def __init__(self, src1, src2):
338 super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False)
339 self.className = Name
340 self.mnemonic = name
341
434 setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, "");
342 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, RegOpChild, "");
435
436 # Build the immediate version of this micro op
437 class RegOpChildImm(RegOpImm):
438 def __init__(self, src1, src2):
439 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False)
440 self.className = Name + "Imm"
441 self.mnemonic = name + "i"
442
343
344 # Build the immediate version of this micro op
345 class RegOpChildImm(RegOpImm):
346 def __init__(self, src1, src2):
347 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False)
348 self.className = Name + "Imm"
349 self.mnemonic = name + "i"
350
443 setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, "");
351 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
352 immCode, RegOpChildImm, "");
444
445 defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2')
446
447 # This has it's own function because Rd ops don't always have two parameters
448 def defineMicroRegOpRd(mnemonic, code):
449 Name = mnemonic
450 name = mnemonic.lower()
451
452 class RegOpChild(RegOp):
453 def __init__(self, dest, src1 = "NUM_INTREGS"):
454 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False)
455 self.className = Name
456 self.mnemonic = name
457
353
354 defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2')
355
356 # This has it's own function because Rd ops don't always have two parameters
357 def defineMicroRegOpRd(mnemonic, code):
358 Name = mnemonic
359 name = mnemonic.lower()
360
361 class RegOpChild(RegOp):
362 def __init__(self, dest, src1 = "NUM_INTREGS"):
363 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False)
364 self.className = Name
365 self.mnemonic = name
366
458 setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild, "");
367 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, RegOpChild, "");
459
460 defineMicroRegOpRd('Rdip', 'DestReg = RIP')
461
462 def defineMicroRegOpImm(mnemonic, code):
463 Name = mnemonic
464 name = mnemonic.lower()
465
466 class RegOpChild(RegOpImm):
467 def __init__(self, dest, src1, src2):
468 super(RegOpChild, self).__init__(dest, src1, src2, False)
469 self.className = Name
470 self.mnemonic = name
471
368
369 defineMicroRegOpRd('Rdip', 'DestReg = RIP')
370
371 def defineMicroRegOpImm(mnemonic, code):
372 Name = mnemonic
373 name = mnemonic.lower()
374
375 class RegOpChild(RegOpImm):
376 def __init__(self, dest, src1, src2):
377 super(RegOpChild, self).__init__(dest, src1, src2, False)
378 self.className = Name
379 self.mnemonic = name
380
472 setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild, "");
381 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, RegOpChild, "");
473
474 defineMicroRegOpImm('Sext', '''
475 IntReg val = SrcReg1;
476 int sign_bit = bits(val, imm8-1, imm8-1);
477 val = sign_bit ? (val | ~mask(imm8)) : val;
478 DestReg = merge(DestReg, val, dataSize);''')
479}};
382
383 defineMicroRegOpImm('Sext', '''
384 IntReg val = SrcReg1;
385 int sign_bit = bits(val, imm8-1, imm8-1);
386 val = sign_bit ? (val | ~mask(imm8)) : val;
387 DestReg = merge(DestReg, val, dataSize);''')
388}};