regop.isa (4592:520664dfb26f) | regop.isa (4595:5162e9a7728c) |
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1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 342 unchanged lines hidden (view full) --- 351let {{ 352 353 # Make these empty strings so that concatenating onto 354 # them will always work. 355 header_output = "" 356 decoder_output = "" 357 exec_output = "" 358 | 1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 342 unchanged lines hidden (view full) --- 351let {{ 352 353 # Make these empty strings so that concatenating onto 354 # them will always work. 355 header_output = "" 356 decoder_output = "" 357 exec_output = "" 358 |
359 def defineMicroRegOp(mnemonic, code): | 359 def setUpMicroRegOp(name, Name, base, code, child): |
360 global header_output 361 global decoder_output 362 global exec_output 363 global microopClasses | 360 global header_output 361 global decoder_output 362 global exec_output 363 global microopClasses |
364 365 iop = InstObjParams(name, Name, base, {"code" : code}) 366 header_output += MicroRegOpDeclare.subst(iop) 367 decoder_output += MicroRegOpConstructor.subst(iop) 368 exec_output += MicroRegOpExecute.subst(iop) 369 370 microopClasses[name] = child 371 372 def defineMicroRegOp(mnemonic, code): |
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364 Name = mnemonic 365 name = mnemonic.lower() 366 367 # Find op2 in each of the instruction definitions. Create two versions 368 # of the code, one with an integer operand, and one with an immediate 369 # operand. 370 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 371 regCode = matcher.sub("SrcReg2", code) 372 immCode = matcher.sub("imm8", code) 373 | 373 Name = mnemonic 374 name = mnemonic.lower() 375 376 # Find op2 in each of the instruction definitions. Create two versions 377 # of the code, one with an integer operand, and one with an immediate 378 # operand. 379 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 380 regCode = matcher.sub("SrcReg2", code) 381 immCode = matcher.sub("imm8", code) 382 |
374 # Build up the all register version of this micro op 375 iop = InstObjParams(name, Name, 'RegOp', {"code" : regCode}) 376 header_output += MicroRegOpDeclare.subst(iop) 377 decoder_output += MicroRegOpConstructor.subst(iop) 378 exec_output += MicroRegOpExecute.subst(iop) 379 | 383 # Build the all register version of this micro op |
380 class RegOpChild(RegOp): 381 def __init__(self, dest, src1, src2): 382 super(RegOpChild, self).__init__(dest, src1, src2) 383 self.className = Name 384 self.mnemonic = name 385 | 384 class RegOpChild(RegOp): 385 def __init__(self, dest, src1, src2): 386 super(RegOpChild, self).__init__(dest, src1, src2) 387 self.className = Name 388 self.mnemonic = name 389 |
386 microopClasses[name] = RegOpChild | 390 setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild); |
387 | 391 |
388 # Build up the immediate version of this micro op 389 iop = InstObjParams(name + "i", Name, 390 'RegOpImm', {"code" : immCode}) 391 header_output += MicroRegOpImmDeclare.subst(iop) 392 decoder_output += MicroRegOpImmConstructor.subst(iop) 393 exec_output += MicroRegOpImmExecute.subst(iop) 394 395 class RegOpImmChild(RegOpImm): 396 def __init__(self, dest, src1, imm): 397 super(RegOpImmChild, self).__init__(dest, src1, imm) | 392 # Build the immediate version of this micro op 393 class RegOpChildImm(RegOpImm): 394 def __init__(self, dest, src1, src2): 395 super(RegOpChildImm, self).__init__(dest, src1, src2) |
398 self.className = Name + "Imm" 399 self.mnemonic = name + "i" 400 | 396 self.className = Name + "Imm" 397 self.mnemonic = name + "i" 398 |
401 microopClasses[name + "i"] = RegOpImmChild | 399 setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm); |
402 403 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF 404 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') 405 defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF 406 defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF 407 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') 408 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF 409 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') 410 defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg 411 defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)') 412 413 # This has it's own function because Wr ops have implicit destinations 414 def defineMicroRegOpWr(mnemonic, code): | 400 401 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF 402 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') 403 defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF 404 defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF 405 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') 406 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF 407 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') 408 defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg 409 defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)') 410 411 # This has it's own function because Wr ops have implicit destinations 412 def defineMicroRegOpWr(mnemonic, code): |
415 global header_output 416 global decoder_output 417 global exec_output 418 global microopClasses | |
419 Name = mnemonic 420 name = mnemonic.lower() 421 422 # Find op2 in each of the instruction definitions. Create two versions 423 # of the code, one with an integer operand, and one with an immediate 424 # operand. 425 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 426 regCode = matcher.sub("SrcReg2", code) 427 immCode = matcher.sub("imm8", code) 428 | 413 Name = mnemonic 414 name = mnemonic.lower() 415 416 # Find op2 in each of the instruction definitions. Create two versions 417 # of the code, one with an integer operand, and one with an immediate 418 # operand. 419 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 420 regCode = matcher.sub("SrcReg2", code) 421 immCode = matcher.sub("imm8", code) 422 |
429 # Build up the all register version of this micro op 430 iop = InstObjParams(name, Name, 'RegOp', {"code" : regCode}) 431 header_output += MicroRegOpDeclare.subst(iop) 432 decoder_output += MicroRegOpConstructor.subst(iop) 433 exec_output += MicroRegOpExecute.subst(iop) 434 | 423 # Build the all register version of this micro op |
435 class RegOpChild(RegOp): 436 def __init__(self, src1, src2): 437 super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2) 438 self.className = Name 439 self.mnemonic = name 440 | 424 class RegOpChild(RegOp): 425 def __init__(self, src1, src2): 426 super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2) 427 self.className = Name 428 self.mnemonic = name 429 |
441 microopClasses[name] = RegOpChild | 430 setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild); |
442 | 431 |
443 # Build up the immediate version of this micro op 444 iop = InstObjParams(name + "i", Name, 445 'RegOpImm', {"code" : immCode}) 446 header_output += MicroRegOpImmDeclare.subst(iop) 447 decoder_output += MicroRegOpImmConstructor.subst(iop) 448 exec_output += MicroRegOpImmExecute.subst(iop) 449 450 class RegOpImmChild(RegOpImm): 451 def __init__(self, src1, imm): 452 super(RegOpImmChild, self).__init__("NUM_INTREGS", src1, imm) | 432 # Build the immediate version of this micro op 433 class RegOpChildImm(RegOpImm): 434 def __init__(self, src1, src2): 435 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2) |
453 self.className = Name + "Imm" 454 self.mnemonic = name + "i" 455 | 436 self.className = Name + "Imm" 437 self.mnemonic = name + "i" 438 |
456 microopClasses[name + "i"] = RegOpImmChild | 439 setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm); |
457 458 defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2') 459 460 # This has it's own function because Rd ops don't always have two parameters 461 def defineMicroRegOpRd(mnemonic, code): | 440 441 defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2') 442 443 # This has it's own function because Rd ops don't always have two parameters 444 def defineMicroRegOpRd(mnemonic, code): |
462 global header_output 463 global decoder_output 464 global exec_output 465 global microopClasses | |
466 Name = mnemonic 467 name = mnemonic.lower() 468 | 445 Name = mnemonic 446 name = mnemonic.lower() 447 |
469 iop = InstObjParams(name, Name, 'RegOp', {"code" : code}) 470 header_output += MicroRegOpDeclare.subst(iop) 471 decoder_output += MicroRegOpConstructor.subst(iop) 472 exec_output += MicroRegOpExecute.subst(iop) 473 | |
474 class RegOpChild(RegOp): 475 def __init__(self, dest, src1 = "NUM_INTREGS"): 476 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS") 477 self.className = Name 478 self.mnemonic = name 479 | 448 class RegOpChild(RegOp): 449 def __init__(self, dest, src1 = "NUM_INTREGS"): 450 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS") 451 self.className = Name 452 self.mnemonic = name 453 |
480 microopClasses[name] = RegOpChild | 454 setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild); |
481 482 defineMicroRegOpRd('Rdip', 'DestReg = RIP') | 455 456 defineMicroRegOpRd('Rdip', 'DestReg = RIP') |
457 458 def defineMicroRegOpImm(mnemonic, code): 459 Name = mnemonic 460 name = mnemonic.lower() 461 462 class RegOpChild(RegOpImm): 463 def __init__(self, dest, src1, src2): 464 super(RegOpChild, self).__init__(dest, src1, src2) 465 self.className = Name 466 self.mnemonic = name 467 468 setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild); 469 470 defineMicroRegOpImm('Sext', ''' 471 IntReg val = SrcReg1; 472 int sign_bit = bits(val, imm8-1, imm8-1); 473 val = sign_bit ? (val | ~mask(imm8)) : val; 474 DestReg = merge(DestReg, val, dataSize);''') |
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483}}; | 475}}; |