regop.isa (4560:d65c11cc31d7) regop.isa (4581:23166f771fa4)
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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54// Authors: Gabe Black
55
56//////////////////////////////////////////////////////////////////////////
57//
58// RegOp Microop templates
59//
60//////////////////////////////////////////////////////////////////////////
61
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

--- 45 unchanged lines hidden (view full) ---

54// Authors: Gabe Black
55
56//////////////////////////////////////////////////////////////////////////
57//
58// RegOp Microop templates
59//
60//////////////////////////////////////////////////////////////////////////
61
62output header {{
63 /**
64 * Base classes for RegOps which provides a generateDisassembly method.
65 */
66 class RegOp : public X86MicroopBase
67 {
68 protected:
69 const RegIndex src1;
70 const RegIndex src2;
71 const RegIndex dest;
72 const bool setStatus;
73 const uint8_t dataSize;
74 const uint8_t ext;
75
76 // Constructor
77 RegOp(ExtMachInst _machInst,
78 const char *mnem, const char *_instMnem,
79 bool isMicro, bool isDelayed,
80 bool isFirst, bool isLast,
81 RegIndex _src1, RegIndex _src2, RegIndex _dest,
82 bool _setStatus, uint8_t _dataSize, uint8_t _ext,
83 OpClass __opClass) :
84 X86MicroopBase(_machInst, mnem, _instMnem,
85 isMicro, isDelayed, isFirst, isLast,
86 __opClass),
87 src1(_src1), src2(_src2), dest(_dest),
88 setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
89 {
90 }
91
92 std::string generateDisassembly(Addr pc,
93 const SymbolTable *symtab) const;
94 };
95
96 class RegOpImm : public X86MicroopBase
97 {
98 protected:
99 const RegIndex src1;
100 const uint8_t imm8;
101 const RegIndex dest;
102 const bool setStatus;
103 const uint8_t dataSize;
104 const uint8_t ext;
105
106 // Constructor
107 RegOpImm(ExtMachInst _machInst,
108 const char * mnem, const char *_instMnem,
109 bool isMicro, bool isDelayed,
110 bool isFirst, bool isLast,
111 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
112 bool _setStatus, uint8_t _dataSize, uint8_t _ext,
113 OpClass __opClass) :
114 X86MicroopBase(_machInst, mnem, _instMnem,
115 isMicro, isDelayed, isFirst, isLast,
116 __opClass),
117 src1(_src1), imm8(_imm8), dest(_dest),
118 setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
119 {
120 }
121
122 std::string generateDisassembly(Addr pc,
123 const SymbolTable *symtab) const;
124 };
125}};
126
127output decoder {{
128 std::string RegOp::generateDisassembly(Addr pc,
129 const SymbolTable *symtab) const
130 {
131 std::stringstream response;
132
133 printMnemonic(response, instMnem, mnemonic);
134 printReg(response, dest);
135 response << ", ";
136 printReg(response, src1);
137 response << ", ";
138 printReg(response, src2);
139 return response.str();
140 }
141
142 std::string RegOpImm::generateDisassembly(Addr pc,
143 const SymbolTable *symtab) const
144 {
145 std::stringstream response;
146
147 printMnemonic(response, instMnem, mnemonic);
148 printReg(response, dest);
149 response << ", ";
150 printReg(response, src1);
151 ccprintf(response, ", %#x", imm8);
152 return response.str();
153 }
154}};
155
62def template MicroRegOpExecute {{
63 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
64 Trace::InstRecord *traceData) const
65 {
66 Fault fault = NoFault;
67
68 %(op_decl)s;
69 %(op_rd)s;

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96 return fault;
97 }
98}};
99
100def template MicroRegOpDeclare {{
101 class %(class_name)s : public %(base_class)s
102 {
103 protected:
156def template MicroRegOpExecute {{
157 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
158 Trace::InstRecord *traceData) const
159 {
160 Fault fault = NoFault;
161
162 %(op_decl)s;
163 %(op_rd)s;

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190 return fault;
191 }
192}};
193
194def template MicroRegOpDeclare {{
195 class %(class_name)s : public %(base_class)s
196 {
197 protected:
104 const RegIndex src1;
105 const RegIndex src2;
106 const RegIndex dest;
107 const bool setStatus;
108 const uint8_t dataSize;
109 const uint8_t ext;
110 void buildMe();
111
112 public:
113 %(class_name)s(ExtMachInst _machInst,
114 const char * instMnem,
115 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
116 RegIndex _src1, RegIndex _src2, RegIndex _dest,
117 bool _setStatus, uint8_t _dataSize, uint8_t _ext);

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125 };
126}};
127
128def template MicroRegOpImmDeclare {{
129
130 class %(class_name)sImm : public %(base_class)s
131 {
132 protected:
198 void buildMe();
199
200 public:
201 %(class_name)s(ExtMachInst _machInst,
202 const char * instMnem,
203 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
204 RegIndex _src1, RegIndex _src2, RegIndex _dest,
205 bool _setStatus, uint8_t _dataSize, uint8_t _ext);

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213 };
214}};
215
216def template MicroRegOpImmDeclare {{
217
218 class %(class_name)sImm : public %(base_class)s
219 {
220 protected:
133 const RegIndex src1;
134 const uint8_t imm8;
135 const RegIndex dest;
136 const bool setStatus;
137 const uint8_t dataSize;
138 const uint8_t ext;
139 void buildMe();
140
141 public:
142 %(class_name)sImm(ExtMachInst _machInst,
143 const char * instMnem,
144 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
145 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
146 bool _setStatus, uint8_t _dataSize, uint8_t _ext);

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161 %(constructor)s;
162 }
163
164 inline %(class_name)s::%(class_name)s(
165 ExtMachInst machInst, const char * instMnem,
166 RegIndex _src1, RegIndex _src2, RegIndex _dest,
167 bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
168 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
221 void buildMe();
222
223 public:
224 %(class_name)sImm(ExtMachInst _machInst,
225 const char * instMnem,
226 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
227 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
228 bool _setStatus, uint8_t _dataSize, uint8_t _ext);

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243 %(constructor)s;
244 }
245
246 inline %(class_name)s::%(class_name)s(
247 ExtMachInst machInst, const char * instMnem,
248 RegIndex _src1, RegIndex _src2, RegIndex _dest,
249 bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
250 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
169 false, false, false, false, %(op_class)s),
170 src1(_src1), src2(_src2), dest(_dest),
171 setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
251 false, false, false, false,
252 _src1, _src2, _dest, _setStatus, _dataSize, _ext,
253 %(op_class)s)
172 {
173 buildMe();
174 }
175
176 inline %(class_name)s::%(class_name)s(
177 ExtMachInst machInst, const char * instMnem,
178 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
179 RegIndex _src1, RegIndex _src2, RegIndex _dest,
180 bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
181 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
254 {
255 buildMe();
256 }
257
258 inline %(class_name)s::%(class_name)s(
259 ExtMachInst machInst, const char * instMnem,
260 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
261 RegIndex _src1, RegIndex _src2, RegIndex _dest,
262 bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
263 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
182 isMicro, isDelayed, isFirst, isLast, %(op_class)s),
183 src1(_src1), src2(_src2), dest(_dest),
184 setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
264 isMicro, isDelayed, isFirst, isLast,
265 _src1, _src2, _dest, _setStatus, _dataSize, _ext,
266 %(op_class)s)
185 {
186 buildMe();
187 }
188}};
189
190def template MicroRegOpImmConstructor {{
191
192 inline void %(class_name)sImm::buildMe()
193 {
194 %(constructor)s;
195 }
196
197 inline %(class_name)sImm::%(class_name)sImm(
198 ExtMachInst machInst, const char * instMnem,
199 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
200 bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
201 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
267 {
268 buildMe();
269 }
270}};
271
272def template MicroRegOpImmConstructor {{
273
274 inline void %(class_name)sImm::buildMe()
275 {
276 %(constructor)s;
277 }
278
279 inline %(class_name)sImm::%(class_name)sImm(
280 ExtMachInst machInst, const char * instMnem,
281 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
282 bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
283 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
202 false, false, false, false, %(op_class)s),
203 src1(_src1), imm8(_imm8), dest(_dest),
204 setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
284 false, false, false, false,
285 _src1, _imm8, _dest, _setStatus, _dataSize, _ext,
286 %(op_class)s)
205 {
206 buildMe();
207 }
208
209 inline %(class_name)sImm::%(class_name)sImm(
210 ExtMachInst machInst, const char * instMnem,
211 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
212 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
213 bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
214 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
287 {
288 buildMe();
289 }
290
291 inline %(class_name)sImm::%(class_name)sImm(
292 ExtMachInst machInst, const char * instMnem,
293 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
294 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
295 bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
296 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
215 isMicro, isDelayed, isFirst, isLast, %(op_class)s),
216 src1(_src1), imm8(_imm8), dest(_dest),
217 setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
297 isMicro, isDelayed, isFirst, isLast,
298 _src1, _imm8, _dest, _setStatus, _dataSize, _ext,
299 %(op_class)s)
218 {
219 buildMe();
220 }
221}};
222
223let {{
224 class RegOp(X86Microop):
225 def __init__(self, dest, src1, src2):
226 self.dest = dest
227 self.src1 = src1
228 self.src2 = src2
229 self.setStatus = False
300 {
301 buildMe();
302 }
303}};
304
305let {{
306 class RegOp(X86Microop):
307 def __init__(self, dest, src1, src2):
308 self.dest = dest
309 self.src1 = src1
310 self.src2 = src2
311 self.setStatus = False
230 self.dataSize = 1
312 self.dataSize = "env.dataSize"
231 self.ext = 0
232
233 def getAllocator(self, *microFlags):
234 allocator = '''new %(class_name)s(machInst, mnemonic
235 %(flags)s, %(src1)s, %(src2)s, %(dest)s,
236 %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
237 "class_name" : self.className,
238 "flags" : self.microFlagsText(microFlags),

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244 return allocator
245
246 class RegOpImm(X86Microop):
247 def __init__(self, dest, src1, imm8):
248 self.dest = dest
249 self.src1 = src1
250 self.imm8 = imm8
251 self.setStatus = False
313 self.ext = 0
314
315 def getAllocator(self, *microFlags):
316 allocator = '''new %(class_name)s(machInst, mnemonic
317 %(flags)s, %(src1)s, %(src2)s, %(dest)s,
318 %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
319 "class_name" : self.className,
320 "flags" : self.microFlagsText(microFlags),

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326 return allocator
327
328 class RegOpImm(X86Microop):
329 def __init__(self, dest, src1, imm8):
330 self.dest = dest
331 self.src1 = src1
332 self.imm8 = imm8
333 self.setStatus = False
252 self.dataSize = 1
334 self.dataSize = "env.dataSize"
253 self.ext = 0
254
255 def getAllocator(self, *microFlags):
256 allocator = '''new %(class_name)s(machInst, mnemonic
257 %(flags)s, %(src1)s, %(imm8)s, %(dest)s,
258 %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
259 "class_name" : self.className,
260 "flags" : self.microFlagsText(microFlags),

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285 # Find op2 in each of the instruction definitions. Create two versions
286 # of the code, one with an integer operand, and one with an immediate
287 # operand.
288 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
289 regCode = matcher.sub("SrcReg2", code)
290 immCode = matcher.sub("imm8", code)
291
292 # Build up the all register version of this micro op
335 self.ext = 0
336
337 def getAllocator(self, *microFlags):
338 allocator = '''new %(class_name)s(machInst, mnemonic
339 %(flags)s, %(src1)s, %(imm8)s, %(dest)s,
340 %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
341 "class_name" : self.className,
342 "flags" : self.microFlagsText(microFlags),

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367 # Find op2 in each of the instruction definitions. Create two versions
368 # of the code, one with an integer operand, and one with an immediate
369 # operand.
370 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
371 regCode = matcher.sub("SrcReg2", code)
372 immCode = matcher.sub("imm8", code)
373
374 # Build up the all register version of this micro op
293 iop = InstObjParams(name, Name, 'X86MicroopBase', {"code" : regCode})
375 iop = InstObjParams(name, Name, 'RegOp', {"code" : regCode})
294 header_output += MicroRegOpDeclare.subst(iop)
295 decoder_output += MicroRegOpConstructor.subst(iop)
296 exec_output += MicroRegOpExecute.subst(iop)
297
298 class RegOpChild(RegOp):
299 def __init__(self, dest, src1, src2):
300 super(RegOpChild, self).__init__(dest, src1, src2)
301 self.className = Name
302 self.mnemonic = name
303
304 microopClasses[name] = RegOpChild
305
306 # Build up the immediate version of this micro op
307 iop = InstObjParams(name + "i", Name,
376 header_output += MicroRegOpDeclare.subst(iop)
377 decoder_output += MicroRegOpConstructor.subst(iop)
378 exec_output += MicroRegOpExecute.subst(iop)
379
380 class RegOpChild(RegOp):
381 def __init__(self, dest, src1, src2):
382 super(RegOpChild, self).__init__(dest, src1, src2)
383 self.className = Name
384 self.mnemonic = name
385
386 microopClasses[name] = RegOpChild
387
388 # Build up the immediate version of this micro op
389 iop = InstObjParams(name + "i", Name,
308 'X86MicroopBase', {"code" : immCode})
390 'RegOpImm', {"code" : immCode})
309 header_output += MicroRegOpImmDeclare.subst(iop)
310 decoder_output += MicroRegOpImmConstructor.subst(iop)
311 exec_output += MicroRegOpImmExecute.subst(iop)
312
313 class RegOpImmChild(RegOpImm):
314 def __init__(self, dest, src1, imm):
315 super(RegOpImmChild, self).__init__(dest, src1, imm)
316 self.className = Name + "Imm"

--- 15 unchanged lines hidden --- 		391 header_output += MicroRegOpImmDeclare.subst(iop)
392 decoder_output += MicroRegOpImmConstructor.subst(iop)
393 exec_output += MicroRegOpImmExecute.subst(iop)
394
395 class RegOpImmChild(RegOpImm):
396 def __init__(self, dest, src1, imm):
397 super(RegOpImmChild, self).__init__(dest, src1, imm)
398 self.className = Name + "Imm"

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