regop.isa (4539:6eeeea62b7c4) regop.isa (4560:d65c11cc31d7)
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

--- 217 unchanged lines hidden (view full) ---

226 self.dest = dest
227 self.src1 = src1
228 self.src2 = src2
229 self.setStatus = False
230 self.dataSize = 1
231 self.ext = 0
232
233 def getAllocator(self, *microFlags):
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

--- 217 unchanged lines hidden (view full) ---

226 self.dest = dest
227 self.src1 = src1
228 self.src2 = src2
229 self.setStatus = False
230 self.dataSize = 1
231 self.ext = 0
232
233 def getAllocator(self, *microFlags):
234 allocator = '''new %(class_name)s(machInst, "%(mnemonic)s"
234 allocator = '''new %(class_name)s(machInst, mnemonic
235 %(flags)s, %(src1)s, %(src2)s, %(dest)s,
236 %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
237 "class_name" : self.className,
235 %(flags)s, %(src1)s, %(src2)s, %(dest)s,
236 %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
237 "class_name" : self.className,
238 "mnemonic" : self.mnemonic,
239 "flags" : self.microFlagsText(microFlags),
240 "src1" : self.src1, "src2" : self.src2,
241 "dest" : self.dest,
242 "setStatus" : self.cppBool(self.setStatus),
243 "dataSize" : self.dataSize,
244 "ext" : self.ext}
245 return allocator
246
247 class RegOpImm(X86Microop):
238 "flags" : self.microFlagsText(microFlags),
239 "src1" : self.src1, "src2" : self.src2,
240 "dest" : self.dest,
241 "setStatus" : self.cppBool(self.setStatus),
242 "dataSize" : self.dataSize,
243 "ext" : self.ext}
244 return allocator
245
246 class RegOpImm(X86Microop):
248 def __init__(self, dest, src1, imm):
247 def __init__(self, dest, src1, imm8):
249 self.dest = dest
250 self.src1 = src1
248 self.dest = dest
249 self.src1 = src1
251 self.imm = imm
250 self.imm8 = imm8
252 self.setStatus = False
253 self.dataSize = 1
254 self.ext = 0
255
256 def getAllocator(self, *microFlags):
251 self.setStatus = False
252 self.dataSize = 1
253 self.ext = 0
254
255 def getAllocator(self, *microFlags):
257 allocator = '''new %(class_name)s(machInst, "%(mnemonic)s"
256 allocator = '''new %(class_name)s(machInst, mnemonic
258 %(flags)s, %(src1)s, %(imm8)s, %(dest)s,
259 %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
260 "class_name" : self.className,
257 %(flags)s, %(src1)s, %(imm8)s, %(dest)s,
258 %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
259 "class_name" : self.className,
261 "mnemonic" : self.mnemonic,
262 "flags" : self.microFlagsText(microFlags),
263 "src1" : self.src1, "imm8" : self.imm8,
264 "dest" : self.dest,
265 "setStatus" : self.cppBool(self.setStatus),
266 "dataSize" : self.dataSize,
267 "ext" : self.ext}
268 return allocator
269}};

--- 43 unchanged lines hidden (view full) ---

313 exec_output += MicroRegOpImmExecute.subst(iop)
314
315 class RegOpImmChild(RegOpImm):
316 def __init__(self, dest, src1, imm):
317 super(RegOpImmChild, self).__init__(dest, src1, imm)
318 self.className = Name + "Imm"
319 self.mnemonic = name + "i"
320
260 "flags" : self.microFlagsText(microFlags),
261 "src1" : self.src1, "imm8" : self.imm8,
262 "dest" : self.dest,
263 "setStatus" : self.cppBool(self.setStatus),
264 "dataSize" : self.dataSize,
265 "ext" : self.ext}
266 return allocator
267}};

--- 43 unchanged lines hidden (view full) ---

311 exec_output += MicroRegOpImmExecute.subst(iop)
312
313 class RegOpImmChild(RegOpImm):
314 def __init__(self, dest, src1, imm):
315 super(RegOpImmChild, self).__init__(dest, src1, imm)
316 self.className = Name + "Imm"
317 self.mnemonic = name + "i"
318
321 microopClasses[name + "i"] = RegOpChild
319 microopClasses[name + "i"] = RegOpImmChild
322
323 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF
324 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
325 defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF
326 defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF
327 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
328 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF
329 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
330 defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg
331 defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)')
332
333}};
320
321 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF
322 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
323 defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF
324 defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF
325 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
326 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF
327 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
328 defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg
329 defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)')
330
331}};