regop.isa (4519:f8da6b45573f) | regop.isa (4528:f0b19ee67a7b) |
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1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 207 unchanged lines hidden (view full) --- 216 src1(_src1), imm8(_imm8), dest(_dest), 217 setStatus(_setStatus), dataSize(_dataSize), ext(_ext) 218 { 219 buildMe(); 220 } 221}}; 222 223let {{ | 1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 207 unchanged lines hidden (view full) --- 216 src1(_src1), imm8(_imm8), dest(_dest), 217 setStatus(_setStatus), dataSize(_dataSize), ext(_ext) 218 { 219 buildMe(); 220 } 221}}; 222 223let {{ |
224 class RegOp(object): | 224 class RegOp(X86Microop): |
225 def __init__(self, dest, src1, src2): 226 self.dest = dest 227 self.src1 = src1 228 self.src2 = src2 229 self.setStatus = False 230 self.dataSize = 1 231 self.ext = 0 232 --- 5 unchanged lines hidden (view full) --- 238 "mnemonic" : self.mnemonic, 239 "flags" : self.microFlagsText(microFlags), 240 "src1" : self.src1, "src2" : self.src2, 241 "dest" : self.dest, 242 "setStatus" : self.setStatus, 243 "dataSize" : self.dataSize, 244 "ext" : self.ext} 245 | 225 def __init__(self, dest, src1, src2): 226 self.dest = dest 227 self.src1 = src1 228 self.src2 = src2 229 self.setStatus = False 230 self.dataSize = 1 231 self.ext = 0 232 --- 5 unchanged lines hidden (view full) --- 238 "mnemonic" : self.mnemonic, 239 "flags" : self.microFlagsText(microFlags), 240 "src1" : self.src1, "src2" : self.src2, 241 "dest" : self.dest, 242 "setStatus" : self.setStatus, 243 "dataSize" : self.dataSize, 244 "ext" : self.ext} 245 |
246 class RegOpImm(object): | 246 class RegOpImm(X86Microop): |
247 def __init__(self, dest, src1, imm): 248 self.dest = dest 249 self.src1 = src1 250 self.imm = imm 251 self.setStatus = False 252 self.dataSize = 1 253 self.ext = 0 254 --- 14 unchanged lines hidden (view full) --- 269let {{ 270 271 # Make these empty strings so that concatenating onto 272 # them will always work. 273 header_output = "" 274 decoder_output = "" 275 exec_output = "" 276 | 247 def __init__(self, dest, src1, imm): 248 self.dest = dest 249 self.src1 = src1 250 self.imm = imm 251 self.setStatus = False 252 self.dataSize = 1 253 self.ext = 0 254 --- 14 unchanged lines hidden (view full) --- 269let {{ 270 271 # Make these empty strings so that concatenating onto 272 # them will always work. 273 header_output = "" 274 decoder_output = "" 275 exec_output = "" 276 |
277 def defineMicroIntOp(mnemonic, code): | 277 def defineMicroRegOp(mnemonic, code): |
278 global header_output 279 global decoder_output 280 global exec_output | 278 global header_output 279 global decoder_output 280 global exec_output |
281 global microopClasses |
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281 Name = mnemonic 282 name = mnemonic.lower() 283 284 # Find op2 in each of the instruction definitions. Create two versions 285 # of the code, one with an integer operand, and one with an immediate 286 # operand. 287 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 288 regCode = matcher.sub("SrcReg2", code) 289 immCode = matcher.sub("imm8", code) 290 291 # Build up the all register version of this micro op 292 iop = InstObjParams(name, Name, 'X86MicroOpBase', {"code" : regCode}) 293 header_output += MicroRegOpDeclare.subst(iop) 294 decoder_output += MicroRegOpConstructor.subst(iop) 295 exec_output += MicroRegOpExecute.subst(iop) 296 297 class RegOpChild(RegOp): 298 def __init__(self, dest, src1, src2): | 282 Name = mnemonic 283 name = mnemonic.lower() 284 285 # Find op2 in each of the instruction definitions. Create two versions 286 # of the code, one with an integer operand, and one with an immediate 287 # operand. 288 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 289 regCode = matcher.sub("SrcReg2", code) 290 immCode = matcher.sub("imm8", code) 291 292 # Build up the all register version of this micro op 293 iop = InstObjParams(name, Name, 'X86MicroOpBase', {"code" : regCode}) 294 header_output += MicroRegOpDeclare.subst(iop) 295 decoder_output += MicroRegOpConstructor.subst(iop) 296 exec_output += MicroRegOpExecute.subst(iop) 297 298 class RegOpChild(RegOp): 299 def __init__(self, dest, src1, src2): |
299 super(RegOpChild, self).__init__(self, dest, src1, src2) | 300 super(RegOpChild, self).__init__(dest, src1, src2) 301 self.className = Name |
300 self.mnemonic = name 301 302 microopClasses[name] = RegOpChild 303 304 # Build up the immediate version of this micro op 305 iop = InstObjParams(name + "i", Name, 306 'X86MicroOpBase', {"code" : immCode}) 307 header_output += MicroRegOpImmDeclare.subst(iop) 308 decoder_output += MicroRegOpImmConstructor.subst(iop) 309 exec_output += MicroRegOpImmExecute.subst(iop) 310 311 class RegOpImmChild(RegOpImm): 312 def __init__(self, dest, src1, imm): | 302 self.mnemonic = name 303 304 microopClasses[name] = RegOpChild 305 306 # Build up the immediate version of this micro op 307 iop = InstObjParams(name + "i", Name, 308 'X86MicroOpBase', {"code" : immCode}) 309 header_output += MicroRegOpImmDeclare.subst(iop) 310 decoder_output += MicroRegOpImmConstructor.subst(iop) 311 exec_output += MicroRegOpImmExecute.subst(iop) 312 313 class RegOpImmChild(RegOpImm): 314 def __init__(self, dest, src1, imm): |
313 super(RegOpImmChild, self).__init__(self, dest, src1, imm) | 315 super(RegOpImmChild, self).__init__(dest, src1, imm) 316 self.className = Name + "Imm" |
314 self.mnemonic = name + "i" 315 316 microopClasses[name + "i"] = RegOpChild 317 | 317 self.mnemonic = name + "i" 318 319 microopClasses[name + "i"] = RegOpChild 320 |
318 defineMicroIntOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF 319 defineMicroIntOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') 320 defineMicroIntOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF 321 defineMicroIntOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF 322 defineMicroIntOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') 323 defineMicroIntOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF 324 defineMicroIntOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') 325 defineMicroIntOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg 326 defineMicroIntOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)') | 321 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF 322 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') 323 defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF 324 defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF 325 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') 326 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF 327 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') 328 defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg 329 defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)') |
327 328}}; | 330 331}}; |