regop.isa (12588:c007da6c777a) regop.isa (13613:a19963be12ca)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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46 Trace::InstRecord *traceData) const
47 {
48 Fault fault = NoFault;
49
50 DPRINTF(X86, "The data size is %d\n", dataSize);
51 %(op_decl)s;
52 %(op_rd)s;
53
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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46 Trace::InstRecord *traceData) const
47 {
48 Fault fault = NoFault;
49
50 DPRINTF(X86, "The data size is %d\n", dataSize);
51 %(op_decl)s;
52 %(op_rd)s;
53
54 IntReg result M5_VAR_USED;
54 RegVal result M5_VAR_USED;
55
56 if(%(cond_check)s)
57 {
58 %(code)s;
59 %(flag_code)s;
60 }
61 else
62 {

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76 Fault %(class_name)s::execute(ExecContext *xc,
77 Trace::InstRecord *traceData) const
78 {
79 Fault fault = NoFault;
80
81 %(op_decl)s;
82 %(op_rd)s;
83
55
56 if(%(cond_check)s)
57 {
58 %(code)s;
59 %(flag_code)s;
60 }
61 else
62 {

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76 Fault %(class_name)s::execute(ExecContext *xc,
77 Trace::InstRecord *traceData) const
78 {
79 Fault fault = NoFault;
80
81 %(op_decl)s;
82 %(op_rd)s;
83
84 IntReg result M5_VAR_USED;
84 RegVal result M5_VAR_USED;
85
86 if(%(cond_check)s)
87 {
88 %(code)s;
89 %(flag_code)s;
90 }
91 else
92 {

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1215 ecfBit = newFlags & ECFBit;
1216 ezfBit = newFlags & EZFBit;
1217 dfBit = newFlags & DFBit;
1218 ccFlagBits = newFlags & ccFlagMask;
1219 '''
1220
1221 class Wrflags(WrRegOp):
1222 code = '''
85
86 if(%(cond_check)s)
87 {
88 %(code)s;
89 %(flag_code)s;
90 }
91 else
92 {

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1215 ecfBit = newFlags & ECFBit;
1216 ezfBit = newFlags & EZFBit;
1217 dfBit = newFlags & DFBit;
1218 ccFlagBits = newFlags & ccFlagMask;
1219 '''
1220
1221 class Wrflags(WrRegOp):
1222 code = '''
1223 MiscReg newFlags = psrc1 ^ op2;
1224 MiscReg userFlagMask = 0xDD5;
1223 RegVal newFlags = psrc1 ^ op2;
1224 RegVal userFlagMask = 0xDD5;
1225
1226 // Get only the user flags
1227 ccFlagBits = newFlags & ccFlagMask;
1228 dfBit = newFlags & DFBit;
1229 cfofBits = newFlags & cfofMask;
1230 ecfBit = 0;
1231 ezfBit = 0;
1232

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1263
1264 def __init__(self, dest, imm, flags=None, \
1265 dataSize="env.dataSize"):
1266 super(Ruflag, self).__init__(dest, \
1267 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1268
1269 class Rflag(RegOp):
1270 code = '''
1225
1226 // Get only the user flags
1227 ccFlagBits = newFlags & ccFlagMask;
1228 dfBit = newFlags & DFBit;
1229 cfofBits = newFlags & cfofMask;
1230 ecfBit = 0;
1231 ezfBit = 0;
1232

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1263
1264 def __init__(self, dest, imm, flags=None, \
1265 dataSize="env.dataSize"):
1266 super(Ruflag, self).__init__(dest, \
1267 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1268
1269 class Rflag(RegOp):
1270 code = '''
1271 MiscReg flagMask = 0x3F7FDD5;
1272 MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit |
1271 RegVal flagMask = 0x3F7FDD5;
1272 RegVal flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit |
1273 ecfBit | ezfBit) & flagMask;
1274
1275 int flag = bits(flags, imm8);
1276 DestReg = merge(DestReg, flag, dataSize);
1277 ezfBit = (flag == 0) ? EZFBit : 0;
1278 '''
1279
1280 big_code = '''
1273 ecfBit | ezfBit) & flagMask;
1274
1275 int flag = bits(flags, imm8);
1276 DestReg = merge(DestReg, flag, dataSize);
1277 ezfBit = (flag == 0) ? EZFBit : 0;
1278 '''
1279
1280 big_code = '''
1281 MiscReg flagMask = 0x3F7FDD5;
1282 MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit |
1281 RegVal flagMask = 0x3F7FDD5;
1282 RegVal flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit |
1283 ecfBit | ezfBit) & flagMask;
1284
1285 int flag = bits(flags, imm8);
1286 DestReg = flag & mask(dataSize * 8);
1287 ezfBit = (flag == 0) ? EZFBit : 0;
1288 '''
1289
1290 def __init__(self, dest, imm, flags=None, \
1291 dataSize="env.dataSize"):
1292 super(Rflag, self).__init__(dest, \
1293 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1294
1295 class Sext(RegOp):
1296 code = '''
1283 ecfBit | ezfBit) & flagMask;
1284
1285 int flag = bits(flags, imm8);
1286 DestReg = flag & mask(dataSize * 8);
1287 ezfBit = (flag == 0) ? EZFBit : 0;
1288 '''
1289
1290 def __init__(self, dest, imm, flags=None, \
1291 dataSize="env.dataSize"):
1292 super(Rflag, self).__init__(dest, \
1293 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1294
1295 class Sext(RegOp):
1296 code = '''
1297 IntReg val = psrc1;
1297 RegVal val = psrc1;
1298 // Mask the bit position so that it wraps.
1299 int bitPos = op2 & (dataSize * 8 - 1);
1300 int sign_bit = bits(val, bitPos, bitPos);
1301 uint64_t maskVal = mask(bitPos+1);
1302 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1303 DestReg = merge(DestReg, val, dataSize);
1304 '''
1305
1306 big_code = '''
1298 // Mask the bit position so that it wraps.
1299 int bitPos = op2 & (dataSize * 8 - 1);
1300 int sign_bit = bits(val, bitPos, bitPos);
1301 uint64_t maskVal = mask(bitPos+1);
1302 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1303 DestReg = merge(DestReg, val, dataSize);
1304 '''
1305
1306 big_code = '''
1307 IntReg val = psrc1;
1307 RegVal val = psrc1;
1308 // Mask the bit position so that it wraps.
1309 int bitPos = op2 & (dataSize * 8 - 1);
1310 int sign_bit = bits(val, bitPos, bitPos);
1311 uint64_t maskVal = mask(bitPos+1);
1312 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1313 DestReg = val & mask(dataSize * 8);
1314 '''
1315

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1385 class Wrcr(RegOp):
1386 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1387 super(Wrcr, self).__init__(dest, \
1388 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1389 code = '''
1390 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
1391 fault = std::make_shared<InvalidOpcode>();
1392 } else {
1308 // Mask the bit position so that it wraps.
1309 int bitPos = op2 & (dataSize * 8 - 1);
1310 int sign_bit = bits(val, bitPos, bitPos);
1311 uint64_t maskVal = mask(bitPos+1);
1312 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1313 DestReg = val & mask(dataSize * 8);
1314 '''
1315

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1385 class Wrcr(RegOp):
1386 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1387 super(Wrcr, self).__init__(dest, \
1388 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1389 code = '''
1390 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
1391 fault = std::make_shared<InvalidOpcode>();
1392 } else {
1393 // There are *s in the line below so it doesn't confuse the
1394 // parser. They may be unnecessary.
1395 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize);
1396 MiscReg newVal = psrc1;
1393 RegVal newVal = psrc1;
1397
1398 // Check for any modifications that would cause a fault.
1399 switch(dest) {
1400 case 0:
1401 {
1402 Efer efer = EferOp;
1403 CR0 cr0 = newVal;
1404 CR4 oldCr4 = CR4Op;

--- 326 unchanged lines hidden --- 		1394
1395 // Check for any modifications that would cause a fault.
1396 switch(dest) {
1397 case 0:
1398 {
1399 Efer efer = EferOp;
1400 CR0 cr0 = newVal;
1401 CR4 oldCr4 = CR4Op;

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