1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any 9// use which is NOT directed to receiving any direct monetary 10// compensation for, or commercial advantage from such use. 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Neither the name of 30// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 31// contributors may be used to endorse or promote products derived from 32// this software without specific prior written permission. No right of 33// sublicense is granted herewith. Derivatives of the software and 34// output created using the software may be prepared, but only for 35// Non-Commercial Uses. Derivatives of the software may be shared with 36// others provided: (i) the others agree to abide by the list of 37// conditions herein which includes the Non-Commercial Use restrictions; 38// and (ii) such Derivatives of the software include the above copyright 39// notice to acknowledge the contribution from this software where 40// applicable, this list of conditions and the disclaimer below. 41// 42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 45// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 46// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 47// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53// 54// Authors: Gabe Black 55 56////////////////////////////////////////////////////////////////////////// 57// 58// RegOp Microop templates 59// 60////////////////////////////////////////////////////////////////////////// 61 62def template MicroRegOpExecute {{ 63 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 64 Trace::InstRecord *traceData) const 65 { 66 Fault fault = NoFault; 67 68 DPRINTF(X86, "The data size is %d\n", dataSize); 69 %(op_decl)s; 70 %(op_rd)s; 71 72 if(%(cond_check)s) 73 { 74 %(code)s; 75 %(flag_code)s; 76 } 77 else 78 { 79 %(else_code)s; 80 } 81 82 //Write the resulting state to the execution context 83 if(fault == NoFault) 84 { 85 %(op_wb)s; 86 } 87 return fault; 88 } 89}}; 90 91def template MicroRegOpImmExecute {{ 92 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 93 Trace::InstRecord *traceData) const 94 { 95 Fault fault = NoFault; 96 97 %(op_decl)s; 98 %(op_rd)s; 99 100 if(%(cond_check)s) 101 { 102 %(code)s; 103 %(flag_code)s; 104 } 105 else 106 { 107 %(else_code)s; 108 } 109 110 //Write the resulting state to the execution context 111 if(fault == NoFault) 112 { 113 %(op_wb)s; 114 } 115 return fault; 116 } 117}}; 118 119def template MicroRegOpDeclare {{ 120 class %(class_name)s : public %(base_class)s 121 { 122 protected: 123 void buildMe(); 124 125 public: 126 %(class_name)s(ExtMachInst _machInst, 127 const char * instMnem, 128 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 129 RegIndex _src1, RegIndex _src2, RegIndex _dest, 130 uint8_t _dataSize, uint16_t _ext); 131 132 %(class_name)s(ExtMachInst _machInst, 133 const char * instMnem, 134 RegIndex _src1, RegIndex _src2, RegIndex _dest, 135 uint8_t _dataSize, uint16_t _ext); 136 137 %(BasicExecDeclare)s 138 }; 139}}; 140 141def template MicroRegOpImmDeclare {{ 142 143 class %(class_name)s : public %(base_class)s 144 { 145 protected: 146 void buildMe(); 147 148 public: 149 %(class_name)s(ExtMachInst _machInst, 150 const char * instMnem, 151 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 152 RegIndex _src1, uint16_t _imm8, RegIndex _dest, 153 uint8_t _dataSize, uint16_t _ext); 154 155 %(class_name)s(ExtMachInst _machInst, 156 const char * instMnem, 157 RegIndex _src1, uint16_t _imm8, RegIndex _dest, 158 uint8_t _dataSize, uint16_t _ext); 159 160 %(BasicExecDeclare)s 161 }; 162}}; 163 164def template MicroRegOpConstructor {{ 165 166 inline void %(class_name)s::buildMe() 167 { 168 %(constructor)s; 169 } 170 171 inline %(class_name)s::%(class_name)s( 172 ExtMachInst machInst, const char * instMnem, 173 RegIndex _src1, RegIndex _src2, RegIndex _dest, 174 uint8_t _dataSize, uint16_t _ext) : 175 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 176 false, false, false, false, 177 _src1, _src2, _dest, _dataSize, _ext, 178 %(op_class)s) 179 { 180 buildMe(); 181 } 182 183 inline %(class_name)s::%(class_name)s( 184 ExtMachInst machInst, const char * instMnem, 185 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 186 RegIndex _src1, RegIndex _src2, RegIndex _dest, 187 uint8_t _dataSize, uint16_t _ext) : 188 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 189 isMicro, isDelayed, isFirst, isLast, 190 _src1, _src2, _dest, _dataSize, _ext, 191 %(op_class)s) 192 { 193 buildMe(); 194 } 195}}; 196 197def template MicroRegOpImmConstructor {{ 198 199 inline void %(class_name)s::buildMe() 200 { 201 %(constructor)s; 202 } 203 204 inline %(class_name)s::%(class_name)s( 205 ExtMachInst machInst, const char * instMnem, 206 RegIndex _src1, uint16_t _imm8, RegIndex _dest, 207 uint8_t _dataSize, uint16_t _ext) : 208 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 209 false, false, false, false, 210 _src1, _imm8, _dest, _dataSize, _ext, 211 %(op_class)s) 212 { 213 buildMe(); 214 } 215 216 inline %(class_name)s::%(class_name)s( 217 ExtMachInst machInst, const char * instMnem, 218 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 219 RegIndex _src1, uint16_t _imm8, RegIndex _dest, 220 uint8_t _dataSize, uint16_t _ext) : 221 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 222 isMicro, isDelayed, isFirst, isLast, 223 _src1, _imm8, _dest, _dataSize, _ext, 224 %(op_class)s) 225 { 226 buildMe(); 227 } 228}}; 229 230let {{ 231 # Make these empty strings so that concatenating onto 232 # them will always work. 233 header_output = "" 234 decoder_output = "" 235 exec_output = "" 236 237 immTemplates = ( 238 MicroRegOpImmDeclare, 239 MicroRegOpImmConstructor, 240 MicroRegOpImmExecute) 241 242 regTemplates = ( 243 MicroRegOpDeclare, 244 MicroRegOpConstructor, 245 MicroRegOpExecute) 246 247 class RegOpMeta(type): 248 def buildCppClasses(self, name, Name, suffix, \ 249 code, flag_code, cond_check, else_code): 250 251 # Globals to stick the output in 252 global header_output 253 global decoder_output 254 global exec_output 255 256 # Stick all the code together so it can be searched at once 257 allCode = "|".join((code, flag_code, cond_check, else_code)) 258 259 # If op2 is used anywhere, make register and immediate versions 260 # of this code. 261 matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 262 match = matcher.search(allCode) 263 if match: 264 typeQual = "" 265 if match.group("typeQual"): 266 typeQual = match.group("typeQual") 267 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 268 self.buildCppClasses(name, Name, suffix, 269 matcher.sub(src2_name, code), 270 matcher.sub(src2_name, flag_code), 271 matcher.sub(src2_name, cond_check), 272 matcher.sub(src2_name, else_code)) 273 self.buildCppClasses(name + "i", Name, suffix + "Imm", 274 matcher.sub("imm8", code), 275 matcher.sub("imm8", flag_code), 276 matcher.sub("imm8", cond_check), 277 matcher.sub("imm8", else_code)) 278 return 279 280 # If there's something optional to do with flags, generate 281 # a version without it and fix up this version to use it. 282 if flag_code is not "" or cond_check is not "true": 283 self.buildCppClasses(name, Name, suffix, 284 code, "", "true", else_code) 285 suffix = "Flags" + suffix 286 287 # If psrc1 or psrc2 is used, we need to actually insert code to 288 # compute it. 289 matcher = re.compile("(?<!\w)psrc1(?!\w)") 290 if matcher.search(allCode): 291 code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 292 matcher = re.compile("(?<!\w)psrc2(?!\w)") 293 if matcher.search(allCode): 294 code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 295 # Also make available versions which do sign extension 296 matcher = re.compile("(?<!\w)spsrc1(?!\w)") 297 if matcher.search(allCode): 298 code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 299 matcher = re.compile("(?<!\w)spsrc2(?!\w)") 300 if matcher.search(allCode): 301 code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 302 303 base = "X86ISA::RegOp" 304 305 # If imm8 shows up in the code, use the immediate templates, if 306 # not, hopefully the register ones will be correct. 307 templates = regTemplates 308 matcher = re.compile("(?<!\w)imm8(?!\w)") 309 if matcher.search(allCode): 310 base += "Imm" 311 templates = immTemplates 312 313 # Get everything ready for the substitution 314 iop = InstObjParams(name, Name + suffix, base, 315 {"code" : code, 316 "flag_code" : flag_code, 317 "cond_check" : cond_check, 318 "else_code" : else_code}) 319 320 # Generate the actual code (finally!) 321 header_output += templates[0].subst(iop) 322 decoder_output += templates[1].subst(iop) 323 exec_output += templates[2].subst(iop) 324 325 326 def __new__(mcls, Name, bases, dict): 327 abstract = False 328 name = Name.lower() 329 if "abstract" in dict: 330 abstract = dict['abstract'] 331 del dict['abstract'] 332 333 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 334 if not abstract: 335 cls.className = Name 336 cls.base_mnemonic = name 337 code = cls.code 338 flag_code = cls.flag_code 339 cond_check = cls.cond_check 340 else_code = cls.else_code 341 342 # Set up the C++ classes 343 mcls.buildCppClasses(cls, name, Name, "", 344 code, flag_code, cond_check, else_code) 345 346 # Hook into the microassembler dict 347 global microopClasses 348 microopClasses[name] = cls 349 350 allCode = "|".join((code, flag_code, cond_check, else_code)) 351 352 # If op2 is used anywhere, make register and immediate versions 353 # of this code. 354 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 355 if matcher.search(allCode): 356 microopClasses[name + 'i'] = cls 357 return cls 358 359 360 class RegOp(X86Microop): 361 __metaclass__ = RegOpMeta 362 # This class itself doesn't act as a microop 363 abstract = True 364 365 # Default template parameter values 366 flag_code = "" 367 cond_check = "true" 368 else_code = ";" 369 370 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 371 self.dest = dest 372 self.src1 = src1 373 self.op2 = op2 374 self.flags = flags 375 self.dataSize = dataSize 376 if flags is None: 377 self.ext = 0 378 else: 379 if not isinstance(flags, (list, tuple)): 380 raise Exception, "flags must be a list or tuple of flags" 381 self.ext = " | ".join(flags) 382 self.className += "Flags" 383 384 def getAllocator(self, *microFlags): 385 className = self.className 386 if self.mnemonic == self.base_mnemonic + 'i': 387 className += "Imm" 388 allocator = '''new %(class_name)s(machInst, mnemonic 389 %(flags)s, %(src1)s, %(op2)s, %(dest)s, 390 %(dataSize)s, %(ext)s)''' % { 391 "class_name" : className, 392 "flags" : self.microFlagsText(microFlags), 393 "src1" : self.src1, "op2" : self.op2, 394 "dest" : self.dest, 395 "dataSize" : self.dataSize, 396 "ext" : self.ext} 397 return allocator 398 399 class LogicRegOp(RegOp): 400 abstract = True 401 flag_code = ''' 402 //Don't have genFlags handle the OF or CF bits 403 uint64_t mask = CFBit | OFBit; 404 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 405 //If a logic microop wants to set these, it wants to set them to 0. 406 ccFlagBits &= ~(CFBit & ext); 407 ccFlagBits &= ~(OFBit & ext); 408 ''' 409 410 class FlagRegOp(RegOp): 411 abstract = True 412 flag_code = \ 413 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 414 415 class SubRegOp(RegOp): 416 abstract = True 417 flag_code = \ 418 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 419 420 class CondRegOp(RegOp): 421 abstract = True 422 cond_check = "checkCondition(ccFlagBits)" 423
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