1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 210 unchanged lines hidden (view full) --- 219 MicroRegOpImmExecute) 220 221 regTemplates = ( 222 MicroRegOpDeclare, 223 MicroRegOpConstructor, 224 MicroRegOpExecute) 225 226 class RegOpMeta(type): |
227 def buildCppClasses(self, name, Name, suffix, code, big_code, \ 228 flag_code, cond_check, else_code, cond_control_flag_init): |
229 230 # Globals to stick the output in 231 global header_output 232 global decoder_output 233 global exec_output 234 235 # Stick all the code together so it can be searched at once 236 allCode = "|".join((code, flag_code, cond_check, else_code, 237 cond_control_flag_init)) |
238 allBigCode = "|".join((big_code, flag_code, cond_check, else_code, 239 cond_control_flag_init)) |
240 241 # If op2 is used anywhere, make register and immediate versions 242 # of this code. 243 matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") |
244 match = matcher.search(allCode + allBigCode) |
245 if match: 246 typeQual = "" 247 if match.group("typeQual"): 248 typeQual = match.group("typeQual") 249 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 250 self.buildCppClasses(name, Name, suffix, 251 matcher.sub(src2_name, code), |
252 matcher.sub(src2_name, big_code), |
253 matcher.sub(src2_name, flag_code), 254 matcher.sub(src2_name, cond_check), 255 matcher.sub(src2_name, else_code), 256 matcher.sub(src2_name, cond_control_flag_init)) 257 imm_name = "%simm8" % match.group("prefix") 258 self.buildCppClasses(name + "i", Name, suffix + "Imm", 259 matcher.sub(imm_name, code), |
260 matcher.sub(imm_name, big_code), |
261 matcher.sub(imm_name, flag_code), 262 matcher.sub(imm_name, cond_check), 263 matcher.sub(imm_name, else_code), 264 matcher.sub(imm_name, cond_control_flag_init)) 265 return 266 267 # If there's something optional to do with flags, generate 268 # a version without it and fix up this version to use it. 269 if flag_code != "" or cond_check != "true": 270 self.buildCppClasses(name, Name, suffix, |
271 code, big_code, "", "true", else_code, "") |
272 suffix = "Flags" + suffix 273 274 # If psrc1 or psrc2 is used, we need to actually insert code to 275 # compute it. |
276 for (big, all) in ((False, allCode), (True, allBigCode)): 277 prefix = "" 278 for (rex, decl) in ( 279 ("(?<!\w)psrc1(?!\w)", 280 "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"), 281 ("(?<!\w)psrc2(?!\w)", 282 "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"), 283 ("(?<!\w)spsrc1(?!\w)", 284 "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"), 285 ("(?<!\w)spsrc2(?!\w)", 286 "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"), 287 ("(?<!\w)simm8(?!\w)", 288 "int8_t simm8 = imm8;")): 289 matcher = re.compile(rex) 290 if matcher.search(all): 291 prefix += decl + "\n" 292 if big: 293 if big_code != "": 294 big_code = prefix + big_code 295 else: 296 code = prefix + code |
297 298 base = "X86ISA::RegOp" 299 300 # If imm8 shows up in the code, use the immediate templates, if 301 # not, hopefully the register ones will be correct. 302 templates = regTemplates 303 matcher = re.compile("(?<!\w)s?imm8(?!\w)") 304 if matcher.search(allCode): 305 base += "Imm" 306 templates = immTemplates 307 308 # Get everything ready for the substitution |
309 iops = [InstObjParams(name, Name + suffix, base, |
310 {"code" : code, 311 "flag_code" : flag_code, 312 "cond_check" : cond_check, 313 "else_code" : else_code, |
314 "cond_control_flag_init" : cond_control_flag_init})] 315 if big_code != "": 316 iops += [InstObjParams(name, Name + suffix + "Big", base, 317 {"code" : big_code, 318 "flag_code" : flag_code, 319 "cond_check" : cond_check, 320 "else_code" : else_code, 321 "cond_control_flag_init" : 322 cond_control_flag_init})] |
323 324 # Generate the actual code (finally!) |
325 for iop in iops: 326 header_output += templates[0].subst(iop) 327 decoder_output += templates[1].subst(iop) 328 exec_output += templates[2].subst(iop) |
329 330 331 def __new__(mcls, Name, bases, dict): 332 abstract = False 333 name = Name.lower() 334 if "abstract" in dict: 335 abstract = dict['abstract'] 336 del dict['abstract'] 337 338 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 339 if not abstract: 340 cls.className = Name 341 cls.base_mnemonic = name 342 code = cls.code |
343 big_code = cls.big_code |
344 flag_code = cls.flag_code 345 cond_check = cls.cond_check 346 else_code = cls.else_code 347 cond_control_flag_init = cls.cond_control_flag_init 348 349 # Set up the C++ classes |
350 mcls.buildCppClasses(cls, name, Name, "", code, big_code, 351 flag_code, cond_check, else_code, 352 cond_control_flag_init) |
353 354 # Hook into the microassembler dict 355 global microopClasses 356 microopClasses[name] = cls 357 358 allCode = "|".join((code, flag_code, cond_check, else_code, 359 cond_control_flag_init)) 360 --- 6 unchanged lines hidden (view full) --- 367 368 369 class RegOp(X86Microop): 370 __metaclass__ = RegOpMeta 371 # This class itself doesn't act as a microop 372 abstract = True 373 374 # Default template parameter values |
375 big_code = "" |
376 flag_code = "" 377 cond_check = "true" 378 else_code = ";" 379 cond_control_flag_init = "" 380 381 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 382 self.dest = dest 383 self.src1 = src1 --- 4 unchanged lines hidden (view full) --- 388 self.ext = 0 389 else: 390 if not isinstance(flags, (list, tuple)): 391 raise Exception, "flags must be a list or tuple of flags" 392 self.ext = " | ".join(flags) 393 self.className += "Flags" 394 395 def getAllocator(self, microFlags): |
396 if self.big_code != "": 397 className = self.className 398 if self.mnemonic == self.base_mnemonic + 'i': 399 className += "Imm" 400 allocString = ''' 401 (%(dataSize)s >= 4) ? 402 (StaticInstPtr)(new %(class_name)sBig(machInst, 403 macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 404 %(dest)s, %(dataSize)s, %(ext)s)) : 405 (StaticInstPtr)(new %(class_name)s(machInst, 406 macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 407 %(dest)s, %(dataSize)s, %(ext)s)) 408 ''' 409 allocator = allocString % { 410 "class_name" : className, 411 "flags" : self.microFlagsText(microFlags), 412 "src1" : self.src1, "op2" : self.op2, 413 "dest" : self.dest, 414 "dataSize" : self.dataSize, 415 "ext" : self.ext} 416 return allocator 417 else: 418 className = self.className 419 if self.mnemonic == self.base_mnemonic + 'i': 420 className += "Imm" 421 allocator = '''new %(class_name)s(machInst, macrocodeBlock, 422 %(flags)s, %(src1)s, %(op2)s, %(dest)s, 423 %(dataSize)s, %(ext)s)''' % { 424 "class_name" : className, 425 "flags" : self.microFlagsText(microFlags), 426 "src1" : self.src1, "op2" : self.op2, 427 "dest" : self.dest, 428 "dataSize" : self.dataSize, 429 "ext" : self.ext} 430 return allocator |
431 432 class LogicRegOp(RegOp): 433 abstract = True 434 flag_code = ''' 435 //Don't have genFlags handle the OF or CF bits 436 uint64_t mask = CFBit | ECFBit | OFBit; 437 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 438 //If a logic microop wants to set these, it wants to set them to 0. --- 28 unchanged lines hidden (view full) --- 467 class WrRegOp(RegOp): 468 abstract = True 469 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 470 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 471 src1, src2, flags, dataSize) 472 473 class Add(FlagRegOp): 474 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' |
475 big_code = 'DestReg = (psrc1 + op2) & mask(dataSize * 8);' |
476 477 class Or(LogicRegOp): 478 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' |
479 big_code = 'DestReg = (psrc1 | op2) & mask(dataSize * 8);' |
480 481 class Adc(FlagRegOp): 482 code = ''' 483 CCFlagBits flags = ccFlagBits; 484 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 485 ''' |
486 big_code = ''' 487 CCFlagBits flags = ccFlagBits; 488 DestReg = (psrc1 + op2 + flags.cf) & mask(dataSize * 8); 489 ''' |
490 491 class Sbb(SubRegOp): 492 code = ''' 493 CCFlagBits flags = ccFlagBits; 494 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 495 ''' |
496 big_code = ''' 497 CCFlagBits flags = ccFlagBits; 498 DestReg = (psrc1 - op2 - flags.cf) & mask(dataSize * 8); 499 ''' |
500 501 class And(LogicRegOp): 502 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' |
503 big_code = 'DestReg = (psrc1 & op2) & mask(dataSize * 8)' |
504 505 class Sub(SubRegOp): 506 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' |
507 big_code = 'DestReg = (psrc1 - op2) & mask(dataSize * 8)' |
508 509 class Xor(LogicRegOp): 510 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' |
511 big_code = 'DestReg = (psrc1 ^ op2) & mask(dataSize * 8)' |
512 513 class Mul1s(WrRegOp): 514 code = ''' 515 ProdLow = psrc1 * op2; 516 int halfSize = (dataSize * 8) / 2; 517 uint64_t shifter = (ULL(1) << halfSize); 518 uint64_t hiResult; 519 uint64_t psrc1_h = psrc1 / shifter; --- 36 unchanged lines hidden (view full) --- 556 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 557 } else { 558 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 559 } 560 ''' 561 562 class Mulel(RdRegOp): 563 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' |
564 big_code = 'DestReg = ProdLow & mask(dataSize * 8);' |
565 566 class Muleh(RdRegOp): 567 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 568 if not src1: 569 src1 = dest 570 super(RdRegOp, self).__init__(dest, src1, \ 571 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 572 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' |
573 big_code = 'DestReg = ProdHi & mask(dataSize * 8);' |
574 575 # One or two bit divide 576 class Div1(WrRegOp): 577 code = ''' 578 //These are temporaries so that modifying them later won't make 579 //the ISA parser think they're also sources. 580 uint64_t quotient = 0; 581 uint64_t remainder = psrc1; --- 11 unchanged lines hidden (view full) --- 593 Remainder = remainder; 594 Quotient = quotient; 595 Divisor = divisor; 596 } 597 ''' 598 599 # Step divide 600 class Div2(RegOp): |
601 divCode = ''' |
602 uint64_t dividend = Remainder; 603 uint64_t divisor = Divisor; 604 uint64_t quotient = Quotient; 605 uint64_t remainder = dividend; 606 int remaining = op2; 607 //If we overshot, do nothing. This lets us unrool division loops a 608 //little. 609 if (divisor == 0) { --- 30 unchanged lines hidden (view full) --- 640 remaining--; 641 } 642 remainder = dividend; 643 //Do the division. 644 divide(dividend, divisor, quotient, remainder); 645 } 646 } 647 //Keep track of how many bits there are still to pull in. |
648 %s |
649 //Record the final results 650 Remainder = remainder; 651 Quotient = quotient; 652 ''' |
653 code = divCode % "DestReg = merge(DestReg, remaining, dataSize);" 654 big_code = divCode % "DestReg = remaining & mask(dataSize * 8);" |
655 flag_code = ''' 656 if (remaining == 0) 657 ccFlagBits = ccFlagBits | (ext & EZFBit); 658 else 659 ccFlagBits = ccFlagBits & ~(ext & EZFBit); 660 ''' 661 662 class Divq(RdRegOp): 663 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' |
664 big_code = 'DestReg = Quotient & mask(dataSize * 8);' |
665 666 class Divr(RdRegOp): 667 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' |
668 big_code = 'DestReg = Remainder & mask(dataSize * 8);' |
669 670 class Mov(CondRegOp): 671 code = 'DestReg = merge(SrcReg1, op2, dataSize)' 672 else_code = 'DestReg = DestReg;' 673 674 # Shift instructions 675 676 class Sll(RegOp): 677 code = ''' 678 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 679 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 680 ''' |
681 big_code = ''' 682 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 683 DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8); 684 ''' |
685 flag_code = ''' 686 // If the shift amount is zero, no flags should be modified. 687 if (shiftAmt) { 688 //Zero out any flags we might modify. This way we only have to 689 //worry about setting them. 690 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 691 int CFBits = 0; 692 //Figure out if we -would- set the CF bits if requested. --- 9 unchanged lines hidden (view full) --- 702 ccFlagBits = ccFlagBits | OFBit; 703 //Use the regular mechanisms to calculate the other flags. 704 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 705 DestReg, psrc1, op2); 706 } 707 ''' 708 709 class Srl(RegOp): |
710 # Because what happens to the bits shift -in- on a right shift 711 # is not defined in the C/C++ standard, we have to mask them out 712 # to be sure they're zero. |
713 code = ''' 714 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); |
715 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 716 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 717 ''' |
718 big_code = ''' 719 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 720 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 721 DestReg = (psrc1 >> shiftAmt) & logicalMask; 722 ''' |
723 flag_code = ''' 724 // If the shift amount is zero, no flags should be modified. 725 if (shiftAmt) { 726 //Zero out any flags we might modify. This way we only have to 727 //worry about setting them. 728 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 729 //If some combination of the CF bits need to be set, set them. 730 if ((ext & (CFBit | ECFBit)) && --- 6 unchanged lines hidden (view full) --- 737 ccFlagBits = ccFlagBits | OFBit; 738 //Use the regular mechanisms to calculate the other flags. 739 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 740 DestReg, psrc1, op2); 741 } 742 ''' 743 744 class Sra(RegOp): |
745 # Because what happens to the bits shift -in- on a right shift 746 # is not defined in the C/C++ standard, we have to sign extend 747 # them manually to be sure. |
748 code = ''' 749 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); |
750 uint64_t arithMask = (shiftAmt == 0) ? 0 : 751 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 752 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 753 ''' |
754 big_code = ''' 755 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 756 uint64_t arithMask = (shiftAmt == 0) ? 0 : 757 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 758 DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8); 759 ''' |
760 flag_code = ''' 761 // If the shift amount is zero, no flags should be modified. 762 if (shiftAmt) { 763 //Zero out any flags we might modify. This way we only have to 764 //worry about setting them. 765 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 766 //If some combination of the CF bits need to be set, set them. 767 uint8_t effectiveShift = --- 8 unchanged lines hidden (view full) --- 776 } 777 ''' 778 779 class Ror(RegOp): 780 code = ''' 781 uint8_t shiftAmt = 782 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 783 uint8_t realShiftAmt = shiftAmt % (dataSize * 8); |
784 if (realShiftAmt) { |
785 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 786 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 787 DestReg = merge(DestReg, top | bottom, dataSize); |
788 } else |
789 DestReg = merge(DestReg, DestReg, dataSize); 790 ''' 791 flag_code = ''' 792 // If the shift amount is zero, no flags should be modified. 793 if (shiftAmt) { 794 //Zero out any flags we might modify. This way we only have to 795 //worry about setting them. 796 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); --- 12 unchanged lines hidden (view full) --- 809 } 810 ''' 811 812 class Rcr(RegOp): 813 code = ''' 814 uint8_t shiftAmt = 815 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 816 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); |
817 if (realShiftAmt) { |
818 CCFlagBits flags = ccFlagBits; 819 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 820 if (realShiftAmt > 1) 821 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 822 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 823 DestReg = merge(DestReg, top | bottom, dataSize); |
824 } else |
825 DestReg = merge(DestReg, DestReg, dataSize); 826 ''' 827 flag_code = ''' 828 // If the shift amount is zero, no flags should be modified. 829 if (shiftAmt) { 830 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 831 //Zero out any flags we might modify. This way we only have to 832 //worry about setting them. --- 15 unchanged lines hidden (view full) --- 848 } 849 ''' 850 851 class Rol(RegOp): 852 code = ''' 853 uint8_t shiftAmt = 854 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 855 uint8_t realShiftAmt = shiftAmt % (dataSize * 8); |
856 if (realShiftAmt) { |
857 uint64_t top = psrc1 << realShiftAmt; 858 uint64_t bottom = 859 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 860 DestReg = merge(DestReg, top | bottom, dataSize); |
861 } else |
862 DestReg = merge(DestReg, DestReg, dataSize); 863 ''' 864 flag_code = ''' 865 // If the shift amount is zero, no flags should be modified. 866 if (shiftAmt) { 867 //Zero out any flags we might modify. This way we only have to 868 //worry about setting them. 869 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); --- 12 unchanged lines hidden (view full) --- 882 } 883 ''' 884 885 class Rcl(RegOp): 886 code = ''' 887 uint8_t shiftAmt = 888 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 889 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); |
890 if (realShiftAmt) { |
891 CCFlagBits flags = ccFlagBits; 892 uint64_t top = psrc1 << realShiftAmt; 893 uint64_t bottom = flags.cf << (realShiftAmt - 1); 894 if(shiftAmt > 1) 895 bottom |= 896 bits(psrc1, dataSize * 8 - 1, 897 dataSize * 8 - realShiftAmt + 1); 898 DestReg = merge(DestReg, top | bottom, dataSize); |
899 } else |
900 DestReg = merge(DestReg, DestReg, dataSize); 901 ''' 902 flag_code = ''' 903 // If the shift amount is zero, no flags should be modified. 904 if (shiftAmt) { 905 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 906 //Zero out any flags we might modify. This way we only have to 907 //worry about setting them. --- 9 unchanged lines hidden (view full) --- 917 ccFlagBits = ccFlagBits | OFBit; 918 //Use the regular mechanisms to calculate the other flags. 919 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 920 DestReg, psrc1, op2); 921 } 922 ''' 923 924 class Sld(RegOp): |
925 sldCode = ''' |
926 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 927 uint8_t dataBits = dataSize * 8; |
928 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); |
929 uint64_t result; 930 if (realShiftAmt == 0) { 931 result = psrc1; 932 } else if (realShiftAmt < dataBits) { 933 result = (psrc1 << realShiftAmt) | 934 (DoubleBits >> (dataBits - realShiftAmt)); 935 } else { 936 result = (DoubleBits << (realShiftAmt - dataBits)) | 937 (psrc1 >> (2 * dataBits - realShiftAmt)); 938 } |
939 %s |
940 ''' |
941 code = sldCode % "DestReg = merge(DestReg, result, dataSize);" 942 big_code = sldCode % "DestReg = result & mask(dataSize * 8);" |
943 flag_code = ''' 944 // If the shift amount is zero, no flags should be modified. 945 if (shiftAmt) { 946 //Zero out any flags we might modify. This way we only have to 947 //worry about setting them. 948 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 949 int CFBits = 0; 950 //Figure out if we -would- set the CF bits if requested. --- 14 unchanged lines hidden (view full) --- 965 ccFlagBits = ccFlagBits | OFBit; 966 //Use the regular mechanisms to calculate the other flags. 967 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 968 DestReg, psrc1, op2); 969 } 970 ''' 971 972 class Srd(RegOp): |
973 srdCode = ''' |
974 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 975 uint8_t dataBits = dataSize * 8; |
976 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); |
977 uint64_t result; 978 if (realShiftAmt == 0) { 979 result = psrc1; 980 } else if (realShiftAmt < dataBits) { 981 // Because what happens to the bits shift -in- on a right 982 // shift is not defined in the C/C++ standard, we have to 983 // mask them out to be sure they're zero. 984 uint64_t logicalMask = mask(dataBits - realShiftAmt); 985 result = ((psrc1 >> realShiftAmt) & logicalMask) | 986 (DoubleBits << (dataBits - realShiftAmt)); 987 } else { 988 uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); 989 result = ((DoubleBits >> (realShiftAmt - dataBits)) & 990 logicalMask) | 991 (psrc1 << (2 * dataBits - realShiftAmt)); 992 } |
993 %s |
994 ''' |
995 code = srdCode % "DestReg = merge(DestReg, result, dataSize);" 996 big_code = srdCode % "DestReg = result & mask(dataSize * 8);" |
997 flag_code = ''' 998 // If the shift amount is zero, no flags should be modified. 999 if (shiftAmt) { 1000 //Zero out any flags we might modify. This way we only have to 1001 //worry about setting them. 1002 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 1003 int CFBits = 0; 1004 //If some combination of the CF bits need to be set, set them. --- 49 unchanged lines hidden (view full) --- 1054 1055 class Ruflag(RegOp): 1056 code = ''' 1057 int flag = bits(ccFlagBits, imm8); 1058 DestReg = merge(DestReg, flag, dataSize); 1059 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 1060 (ccFlagBits & ~EZFBit); 1061 ''' |
1062 big_code = ''' 1063 int flag = bits(ccFlagBits, imm8); 1064 DestReg = flag & mask(dataSize * 8); 1065 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 1066 (ccFlagBits & ~EZFBit); 1067 ''' |
1068 def __init__(self, dest, imm, flags=None, \ 1069 dataSize="env.dataSize"): 1070 super(Ruflag, self).__init__(dest, \ 1071 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 1072 1073 class Rflag(RegOp): 1074 code = ''' 1075 MiscReg flagMask = 0x3F7FDD5; 1076 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 1077 int flag = bits(flags, imm8); 1078 DestReg = merge(DestReg, flag, dataSize); 1079 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 1080 (ccFlagBits & ~EZFBit); 1081 ''' |
1082 big_code = ''' 1083 MiscReg flagMask = 0x3F7FDD5; 1084 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 1085 int flag = bits(flags, imm8); 1086 DestReg = flag & mask(dataSize * 8); 1087 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 1088 (ccFlagBits & ~EZFBit); 1089 ''' |
1090 def __init__(self, dest, imm, flags=None, \ 1091 dataSize="env.dataSize"): 1092 super(Rflag, self).__init__(dest, \ 1093 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 1094 1095 class Sext(RegOp): 1096 code = ''' 1097 IntReg val = psrc1; 1098 // Mask the bit position so that it wraps. 1099 int bitPos = op2 & (dataSize * 8 - 1); 1100 int sign_bit = bits(val, bitPos, bitPos); 1101 uint64_t maskVal = mask(bitPos+1); 1102 val = sign_bit ? (val | ~maskVal) : (val & maskVal); 1103 DestReg = merge(DestReg, val, dataSize); 1104 ''' |
1105 big_code = ''' 1106 IntReg val = psrc1; 1107 // Mask the bit position so that it wraps. 1108 int bitPos = op2 & (dataSize * 8 - 1); 1109 int sign_bit = bits(val, bitPos, bitPos); 1110 uint64_t maskVal = mask(bitPos+1); 1111 val = sign_bit ? (val | ~maskVal) : (val & maskVal); 1112 DestReg = val & mask(dataSize * 8); 1113 ''' |
1114 flag_code = ''' 1115 if (!sign_bit) 1116 ccFlagBits = ccFlagBits & 1117 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 1118 else 1119 ccFlagBits = ccFlagBits | 1120 (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 1121 ''' 1122 1123 class Zext(RegOp): 1124 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' |
1125 big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);' |
1126 1127 class Rddr(RegOp): 1128 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1129 super(Rddr, self).__init__(dest, \ 1130 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
1131 rdrCode = ''' |
1132 CR4 cr4 = CR4Op; 1133 DR7 dr7 = DR7Op; 1134 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 1135 fault = new InvalidOpcode(); 1136 } else if (dr7.gd) { 1137 fault = new DebugException(); 1138 } else { |
1139 %s |
1140 } 1141 ''' |
1142 code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);" 1143 big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);" |
1144 1145 class Wrdr(RegOp): 1146 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1147 super(Wrdr, self).__init__(dest, \ 1148 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1149 code = ''' 1150 CR4 cr4 = CR4Op; 1151 DR7 dr7 = DR7Op; --- 8 unchanged lines hidden (view full) --- 1160 DebugDest = psrc1; 1161 } 1162 ''' 1163 1164 class Rdcr(RegOp): 1165 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1166 super(Rdcr, self).__init__(dest, \ 1167 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
1168 rdcrCode = ''' |
1169 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 1170 fault = new InvalidOpcode(); 1171 } else { |
1172 %s |
1173 } 1174 ''' |
1175 code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);" 1176 big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);" |
1177 1178 class Wrcr(RegOp): 1179 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1180 super(Wrcr, self).__init__(dest, \ 1181 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1182 code = ''' 1183 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 1184 fault = new InvalidOpcode(); --- 65 unchanged lines hidden (view full) --- 1250 ''' 1251 1252 class WrAttr(SegOp): 1253 code = ''' 1254 SegAttrDest = psrc1; 1255 ''' 1256 1257 class Rdbase(SegOp): |
1258 code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);' 1259 big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);' |
1260 1261 class Rdlimit(SegOp): |
1262 code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);' 1263 big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);' |
1264 1265 class RdAttr(SegOp): |
1266 code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);' 1267 big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);' |
1268 1269 class Rdsel(SegOp): |
1270 code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);' 1271 big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);' |
1272 1273 class Rdval(RegOp): 1274 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1275 super(Rdval, self).__init__(dest, src1, \ 1276 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1277 code = ''' 1278 DestReg = MiscRegSrc1; 1279 ''' --- 215 unchanged lines hidden --- |