1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 112 unchanged lines hidden (view full) --- 121 { 122 protected: 123 void buildMe(); 124 125 public: 126 %(class_name)s(ExtMachInst _machInst, 127 const char * instMnem, 128 bool isMicro, bool isDelayed, bool isFirst, bool isLast, |
129 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, |
130 uint8_t _dataSize, uint16_t _ext); 131 132 %(class_name)s(ExtMachInst _machInst, 133 const char * instMnem, |
134 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, |
135 uint8_t _dataSize, uint16_t _ext); 136 137 %(BasicExecDeclare)s 138 }; 139}}; 140 141def template MicroRegOpImmDeclare {{ 142 143 class %(class_name)s : public %(base_class)s 144 { 145 protected: 146 void buildMe(); 147 148 public: 149 %(class_name)s(ExtMachInst _machInst, 150 const char * instMnem, 151 bool isMicro, bool isDelayed, bool isFirst, bool isLast, |
152 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, |
153 uint8_t _dataSize, uint16_t _ext); 154 155 %(class_name)s(ExtMachInst _machInst, 156 const char * instMnem, |
157 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, |
158 uint8_t _dataSize, uint16_t _ext); 159 160 %(BasicExecDeclare)s 161 }; 162}}; 163 164def template MicroRegOpConstructor {{ 165 166 inline void %(class_name)s::buildMe() 167 { 168 %(constructor)s; 169 } 170 171 inline %(class_name)s::%(class_name)s( 172 ExtMachInst machInst, const char * instMnem, |
173 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, |
174 uint8_t _dataSize, uint16_t _ext) : 175 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 176 false, false, false, false, 177 _src1, _src2, _dest, _dataSize, _ext, 178 %(op_class)s) 179 { 180 buildMe(); 181 } 182 183 inline %(class_name)s::%(class_name)s( 184 ExtMachInst machInst, const char * instMnem, 185 bool isMicro, bool isDelayed, bool isFirst, bool isLast, |
186 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, |
187 uint8_t _dataSize, uint16_t _ext) : 188 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 189 isMicro, isDelayed, isFirst, isLast, 190 _src1, _src2, _dest, _dataSize, _ext, 191 %(op_class)s) 192 { 193 buildMe(); 194 } 195}}; 196 197def template MicroRegOpImmConstructor {{ 198 199 inline void %(class_name)s::buildMe() 200 { 201 %(constructor)s; 202 } 203 204 inline %(class_name)s::%(class_name)s( 205 ExtMachInst machInst, const char * instMnem, |
206 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, |
207 uint8_t _dataSize, uint16_t _ext) : 208 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 209 false, false, false, false, 210 _src1, _imm8, _dest, _dataSize, _ext, 211 %(op_class)s) 212 { 213 buildMe(); 214 } 215 216 inline %(class_name)s::%(class_name)s( 217 ExtMachInst machInst, const char * instMnem, 218 bool isMicro, bool isDelayed, bool isFirst, bool isLast, |
219 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, |
220 uint8_t _dataSize, uint16_t _ext) : 221 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 222 isMicro, isDelayed, isFirst, isLast, 223 _src1, _imm8, _dest, _dataSize, _ext, 224 %(op_class)s) 225 { 226 buildMe(); 227 } --- 248 unchanged lines hidden (view full) --- 476 abstract = True 477 cond_check = "checkCondition(ccFlagBits, ext)" 478 479 class RdRegOp(RegOp): 480 abstract = True 481 def __init__(self, dest, src1=None, dataSize="env.dataSize"): 482 if not src1: 483 src1 = dest |
484 super(RdRegOp, self).__init__(dest, src1, \ 485 "InstRegIndex(NUM_INTREGS)", None, dataSize) |
486 487 class WrRegOp(RegOp): 488 abstract = True 489 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): |
490 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 491 src1, src2, flags, dataSize) |
492 493 class Add(FlagRegOp): 494 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 495 496 class Or(LogicRegOp): 497 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 498 499 class Adc(FlagRegOp): --- 50 unchanged lines hidden (view full) --- 550 551 class Mulel(RdRegOp): 552 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 553 554 class Muleh(RdRegOp): 555 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 556 if not src1: 557 src1 = dest |
558 super(RdRegOp, self).__init__(dest, src1, \ 559 "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
560 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 561 flag_code = ''' 562 if (ProdHi) 563 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 564 else 565 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 566 ''' 567 --- 315 unchanged lines hidden (view full) --- 883 int flag = bits(ccFlagBits, imm8); 884 DestReg = merge(DestReg, flag, dataSize); 885 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 886 (ccFlagBits & ~EZFBit); 887 ''' 888 def __init__(self, dest, imm, flags=None, \ 889 dataSize="env.dataSize"): 890 super(Ruflag, self).__init__(dest, \ |
891 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) |
892 893 class Rflag(RegOp): 894 code = ''' 895 MiscReg flagMask = 0x3F7FDD5; 896 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 897 int flag = bits(flags, imm8); 898 DestReg = merge(DestReg, flag, dataSize); 899 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 900 (ccFlagBits & ~EZFBit); 901 ''' 902 def __init__(self, dest, imm, flags=None, \ 903 dataSize="env.dataSize"): 904 super(Rflag, self).__init__(dest, \ |
905 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) |
906 907 class Sext(RegOp): 908 code = ''' 909 IntReg val = psrc1; 910 // Mask the bit position so that it wraps. 911 int bitPos = op2 & (dataSize * 8 - 1); 912 int sign_bit = bits(val, bitPos, bitPos); 913 uint64_t maskVal = mask(bitPos+1); --- 10 unchanged lines hidden (view full) --- 924 ''' 925 926 class Zext(RegOp): 927 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 928 929 class Rddr(RegOp): 930 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 931 super(Rddr, self).__init__(dest, \ |
932 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
933 code = ''' 934 CR4 cr4 = CR4Op; 935 DR7 dr7 = DR7Op; 936 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 937 fault = new InvalidOpcode(); 938 } else if (dr7.gd) { 939 fault = new DebugException(); 940 } else { 941 DestReg = merge(DestReg, DebugSrc1, dataSize); 942 } 943 ''' 944 945 class Wrdr(RegOp): 946 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 947 super(Wrdr, self).__init__(dest, \ |
948 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
949 code = ''' 950 CR4 cr4 = CR4Op; 951 DR7 dr7 = DR7Op; 952 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 953 fault = new InvalidOpcode(); |
954 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && |
955 machInst.mode.mode == LongMode) { 956 fault = new GeneralProtection(0); 957 } else if (dr7.gd) { 958 fault = new DebugException(); 959 } else { 960 DebugDest = psrc1; 961 } 962 ''' 963 964 class Rdcr(RegOp): 965 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 966 super(Rdcr, self).__init__(dest, \ |
967 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
968 code = ''' 969 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 970 fault = new InvalidOpcode(); 971 } else { 972 DestReg = merge(DestReg, ControlSrc1, dataSize); 973 } 974 ''' 975 976 class Wrcr(RegOp): 977 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 978 super(Wrcr, self).__init__(dest, \ |
979 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
980 code = ''' 981 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 982 fault = new InvalidOpcode(); 983 } else { 984 // There are *s in the line below so it doesn't confuse the 985 // parser. They may be unnecessary. 986 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 987 MiscReg newVal = psrc1; --- 37 unchanged lines hidden (view full) --- 1025 } 1026 ''' 1027 1028 # Microops for manipulating segmentation registers 1029 class SegOp(CondRegOp): 1030 abstract = True 1031 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1032 super(SegOp, self).__init__(dest, \ |
1033 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
1034 1035 class Wrbase(SegOp): 1036 code = ''' 1037 SegBaseDest = psrc1; 1038 ''' 1039 1040 class Wrlimit(SegOp): 1041 code = ''' --- 27 unchanged lines hidden (view full) --- 1069 1070 class Rdsel(SegOp): 1071 code = ''' 1072 DestReg = merge(DestReg, SegSelSrc1, dataSize); 1073 ''' 1074 1075 class Rdval(RegOp): 1076 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): |
1077 super(Rdval, self).__init__(dest, src1, \ 1078 "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
1079 code = ''' 1080 DestReg = MiscRegSrc1; 1081 ''' 1082 1083 class Wrval(RegOp): 1084 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): |
1085 super(Wrval, self).__init__(dest, src1, \ 1086 "InstRegIndex(NUM_INTREGS)", flags, dataSize) |
1087 code = ''' 1088 MiscRegDest = SrcReg1; 1089 ''' 1090 1091 class Chks(RegOp): 1092 def __init__(self, dest, src1, src2=0, 1093 flags=None, dataSize="env.dataSize"): 1094 super(Chks, self).__init__(dest, --- 202 unchanged lines hidden --- |