129c129
< RegIndex _src1, RegIndex _src2, RegIndex _dest,
---
> InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
134c134
< RegIndex _src1, RegIndex _src2, RegIndex _dest,
---
> InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
152c152
< RegIndex _src1, uint16_t _imm8, RegIndex _dest,
---
> InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
157c157
< RegIndex _src1, uint16_t _imm8, RegIndex _dest,
---
> InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
173c173
< RegIndex _src1, RegIndex _src2, RegIndex _dest,
---
> InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
186c186
< RegIndex _src1, RegIndex _src2, RegIndex _dest,
---
> InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
206c206
< RegIndex _src1, uint16_t _imm8, RegIndex _dest,
---
> InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
219c219
< RegIndex _src1, uint16_t _imm8, RegIndex _dest,
---
> InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
484c484,485
< super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
---
> super(RdRegOp, self).__init__(dest, src1, \
> "InstRegIndex(NUM_INTREGS)", None, dataSize)
489c490,491
< super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
---
> super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
> src1, src2, flags, dataSize)
556c558,559
< super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize)
---
> super(RdRegOp, self).__init__(dest, src1, \
> "InstRegIndex(NUM_INTREGS)", flags, dataSize)
888c891
< "NUM_INTREGS", imm, flags, dataSize)
---
> "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
902c905
< "NUM_INTREGS", imm, flags, dataSize)
---
> "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
929c932
< src1, "NUM_INTREGS", flags, dataSize)
---
> src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
945c948
< src1, "NUM_INTREGS", flags, dataSize)
---
> src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
951,952c954
< } else if ((dest == 6 || dest == 7) &&
< bits(psrc1, 63, 32) &&
---
> } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) &&
965c967
< src1, "NUM_INTREGS", flags, dataSize)
---
> src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
977c979
< src1, "NUM_INTREGS", flags, dataSize)
---
> src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1031c1033
< src1, "NUM_INTREGS", flags, dataSize)
---
> src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1075,1076c1077,1078
< super(Rdval, self).__init__(dest, \
< src1, "NUM_INTREGS", flags, dataSize)
---
> super(Rdval, self).__init__(dest, src1, \
> "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1083,1084c1085,1086
< super(Wrval, self).__init__(dest, \
< src1, "NUM_INTREGS", flags, dataSize)
---
> super(Wrval, self).__init__(dest, src1, \
> "InstRegIndex(NUM_INTREGS)", flags, dataSize)