423a424,435
> class RdRegOp(RegOp):
> abstract = True
> def __init__(self, dest, src1=None, dataSize="env.dataSize"):
> if not src1:
> src1 = dest
> super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
>
> class WrRegOp(RegOp):
> abstract = True
> def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
> super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
>
451c463
< class Mul1s(FlagRegOp):
---
> class Mul1s(WrRegOp):
453,456c465,473
< int signPos = (dataSize * 8) / 2 - 1;
< IntReg srcVal1 = psrc1 | (-bits(psrc1, signPos) << signPos);
< IntReg srcVal2 = op2 | (-bits(psrc1, signPos) << signPos);
< DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
---
> ProdLow = psrc1 * op2;
> int halfSize = (dataSize * 8) / 2;
> int64_t spsrc1_h = spsrc1 >> halfSize;
> int64_t spsrc1_l = spsrc1 & mask(halfSize);
> int64_t spsrc2_h = sop2 >> halfSize;
> int64_t spsrc2_l = sop2 & mask(halfSize);
> ProdHi = ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l +
> ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) +
> spsrc1_h * spsrc2_h;
459c476
< class Mul1u(FlagRegOp):
---
> class Mul1u(WrRegOp):
460a478
> ProdLow = psrc1 * op2;
462,464c480,486
< IntReg srcVal1 = psrc1 & mask(halfSize);
< IntReg srcVal2 = op2 & mask(halfSize);
< DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
---
> uint64_t psrc1_h = psrc1 >> halfSize;
> uint64_t psrc1_l = psrc1 & mask(halfSize);
> uint64_t psrc2_h = op2 >> halfSize;
> uint64_t psrc2_l = op2 & mask(halfSize);
> ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
> ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) +
> psrc1_h * psrc2_h;
467,468c489,490
< class Mulel(FlagRegOp):
< code = 'DestReg = merge(DestReg, psrc1 * op2, dataSize);'
---
> class Mulel(RdRegOp):
> code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
475,487c497,508
< class Muleh(FlagRegOp):
< code = '''
< int halfSize = (dataSize * 8) / 2;
< uint64_t psrc1_h = psrc1 >> halfSize;
< uint64_t psrc1_l = psrc1 & mask(halfSize);
< uint64_t psrc2_h = op2 >> halfSize;
< uint64_t psrc2_l = op2 & mask(halfSize);
< uint64_t result =
< ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
< ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) +
< psrc1_h * psrc2_h;
< DestReg = merge(DestReg, result, dataSize);
< '''
---
> class Muleh(RdRegOp):
> def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
> if not src1:
> src1 = dest
> super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize)
> code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
> flag_code = '''
> if (ProdHi)
> ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
> else
> ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
> '''
489,502d509
< class Mulehs(FlagRegOp):
< code = '''
< int halfSize = (dataSize * 8) / 2;
< int64_t spsrc1_h = spsrc1 >> halfSize;
< int64_t spsrc1_l = spsrc1 & mask(halfSize);
< int64_t spsrc2_h = sop2 >> halfSize;
< int64_t spsrc2_l = sop2 & mask(halfSize);
< int64_t result =
< ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l +
< ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) +
< spsrc1_h * spsrc2_h;
< DestReg = merge(DestReg, result, dataSize);
< '''
<
616,620d622
< class WrRegOp(RegOp):
< abstract = True
< def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
< super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
<
632,636d633
< class RdRegOp(RegOp):
< abstract = True
< def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
< super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
<