70,71d69
< %(code)s;
< %(flag_code)s;
72a71,76
> if(%(cond_check)s)
> {
> %(code)s;
> %(flag_code)s;
> }
>
90,91d93
< %(code)s;
< %(flag_code)s;
92a95,100
> if(%(cond_check)s)
> {
> %(code)s;
> %(flag_code)s;
> }
>
113c121
< bool _setStatus, uint8_t _dataSize, uint8_t _ext);
---
> uint8_t _dataSize, uint8_t _ext);
118c126
< bool _setStatus, uint8_t _dataSize, uint8_t _ext);
---
> uint8_t _dataSize, uint8_t _ext);
136c144
< bool _setStatus, uint8_t _dataSize, uint8_t _ext);
---
> uint8_t _dataSize, uint8_t _ext);
141c149
< bool _setStatus, uint8_t _dataSize, uint8_t _ext);
---
> uint8_t _dataSize, uint8_t _ext);
157c165
< bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
---
> uint8_t _dataSize, uint8_t _ext) :
160c168
< _src1, _src2, _dest, _setStatus, _dataSize, _ext,
---
> _src1, _src2, _dest, _dataSize, _ext,
170c178
< bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
---
> uint8_t _dataSize, uint8_t _ext) :
173c181
< _src1, _src2, _dest, _setStatus, _dataSize, _ext,
---
> _src1, _src2, _dest, _dataSize, _ext,
190c198
< bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
---
> uint8_t _dataSize, uint8_t _ext) :
193c201
< _src1, _imm8, _dest, _setStatus, _dataSize, _ext,
---
> _src1, _imm8, _dest, _dataSize, _ext,
203c211
< bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
---
> uint8_t _dataSize, uint8_t _ext) :
206c214
< _src1, _imm8, _dest, _setStatus, _dataSize, _ext,
---
> _src1, _imm8, _dest, _dataSize, _ext,
213a222,237
> class X86MicroMeta(type):
> def __new__(mcls, name, bases, dict):
> abstract = False
> if "abstract" in dict:
> abstract = dict['abstract']
> del dict['abstract']
>
> cls = type.__new__(mcls, name, bases, dict)
> if not abstract:
> allClasses[name] = cls
> return cls
>
> class XXX86Microop(object):
> __metaclass__ = X86MicroMeta
> abstract = True
>
215c239,240
< def __init__(self, dest, src1, src2, setStatus):
---
> abstract = True
> def __init__(self, dest, src1, src2, flags):
219c244
< self.setStatus = setStatus
---
> self.flags = flags
221c246,252
< self.ext = 0
---
> if flags is None:
> self.ext = 0
> else:
> if not isinstance(flags, (list, tuple)):
> raise Exception, "flags must be a list or tuple of flags"
> self.ext = " | ".join(flags)
> self.className += "Flags"
226c257
< %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
---
> %(dataSize)s, %(ext)s)''' % {
231d261
< "setStatus" : self.cppBool(self.setStatus),
237c267,268
< def __init__(self, dest, src1, imm8, setStatus):
---
> abstract = True
> def __init__(self, dest, src1, imm8, flags):
241c272
< self.setStatus = setStatus
---
> self.flags = flags
243c274,280
< self.ext = 0
---
> if flags is None:
> self.ext = 0
> else:
> if not isinstance(flags, (list, tuple)):
> raise Exception, "flags must be a list or tuple of flags"
> self.ext = " | ".join(flags)
> self.className += "Flags"
248c285
< %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
---
> %(dataSize)s, %(ext)s)''' % {
253d289
< "setStatus" : self.cppBool(self.setStatus),
267c303,304
< def setUpMicroRegOp(name, Name, base, code, child, flagCode):
---
> # A function which builds the C++ classes that implement the microops
> def setUpMicroRegOp(name, Name, base, code, flagCode, condCheck):
275c312,313
< "flag_code" : flagCode})
---
> "flag_code" : flagCode,
> "cond_check" : condCheck})
280d317
< microopClasses[name] = child
282c319,325
< def defineMicroRegOp(mnemonic, code, flagCode):
---
> checkCCFlagBits = "checkCondition(ccFlagBits)"
> genCCFlagBits = "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, %s);"
>
>
> # This creates a python representations of a microop which are a cross
> # product of reg/immediate and flag/no flag versions.
> def defineMicroRegOp(mnemonic, code, secondSrc = "op2", cc=False):
293c336,345
< # Build the all register version of this micro op
---
> if not cc:
> flagCode = genCCFlagBits % secondSrc
> condCode = "true"
> else:
> flagCode = ""
> condCode = checkCCFlagBits
>
> regFlagCode = matcher.sub("SrcReg2", flagCode)
> immFlagCode = matcher.sub("imm8", flagCode)
>
295,298c347,350
< def __init__(self, dest, src1, src2, setStatus=False):
< super(RegOpChild, self).__init__(dest, src1, src2, setStatus)
< self.className = Name
< self.mnemonic = name
---
> mnemonic = name
> className = Name
> def __init__(self, dest, src1, src2, flags=None):
> super(RegOpChild, self).__init__(dest, src1, src2, flags)
300,301c352
< setUpMicroRegOp(name, Name, "X86ISA::RegOp", \
< regCode, RegOpChild, flagCode);
---
> microopClasses[name] = RegOpChild
303c354,356
< # Build the immediate version of this micro op
---
> setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true");
> setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, regFlagCode, condCode);
>
305,308c358,361
< def __init__(self, dest, src1, src2, setStatus=False):
< super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus)
< self.className = Name + "Imm"
< self.mnemonic = name + "i"
---
> mnemonic = name + 'i'
> className = Name + 'Imm'
> def __init__(self, dest, src1, src2, flags=None):
> super(RegOpChildImm, self).__init__(dest, src1, src2, flags)
310,311c363
< setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
< immCode, RegOpChildImm, flagCode);
---
> microopClasses[name + 'i'] = RegOpChildImm
313,321c365,366
< defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF
< defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "")
< defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF
< defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF
< defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "")
< defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF
< defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "")
< defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', "") #Needs to set OF,CF,SF and not DestReg
< defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', "")
---
> setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true");
> setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, immFlagCode, condCode);
322a368,377
> defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
> defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
> defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
> defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2')
> defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
> defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2')
> defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
> defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', '-op2')
> defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', cc=True)
>
335d389
< # Build the all register version of this micro op
337,340c391,394
< def __init__(self, src1, src2):
< super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False)
< self.className = Name
< self.mnemonic = name
---
> mnemonic = name
> className = Name
> def __init__(self, src1, src2, flags=None):
> super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags)
342c396
< setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, RegOpChild, "");
---
> microopClasses[name] = RegOpChild
344c398,400
< # Build the immediate version of this micro op
---
> setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true");
> setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, "", checkCCFlagBits);
>
345a402,403
> mnemonic = name
> className = Name
347,349c405
< super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False)
< self.className = Name + "Imm"
< self.mnemonic = name + "i"
---
> super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, None)
351,352c407
< setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
< immCode, RegOpChildImm, "");
---
> microopClasses[name + 'i'] = RegOpChildImm
353a409,411
> setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true");
> setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, "", checkCCFlagBits);
>
363c421
< super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False)
---
> super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None)
367c425
< setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, RegOpChild, "");
---
> microopClasses[name] = RegOpChild
368a427,428
> setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, "", "true");
>
377c437
< super(RegOpChild, self).__init__(dest, src1, src2, False)
---
> super(RegOpChild, self).__init__(dest, src1, src2, None)
381c441
< setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, RegOpChild, "");
---
> microopClasses[name] = RegOpChild
382a443,444
> setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, "", "true");
>
< %(code)s;
< %(flag_code)s;
72a71,76
> if(%(cond_check)s)
> {
> %(code)s;
> %(flag_code)s;
> }
>
90,91d93
< %(code)s;
< %(flag_code)s;
92a95,100
> if(%(cond_check)s)
> {
> %(code)s;
> %(flag_code)s;
> }
>
113c121
< bool _setStatus, uint8_t _dataSize, uint8_t _ext);
---
> uint8_t _dataSize, uint8_t _ext);
118c126
< bool _setStatus, uint8_t _dataSize, uint8_t _ext);
---
> uint8_t _dataSize, uint8_t _ext);
136c144
< bool _setStatus, uint8_t _dataSize, uint8_t _ext);
---
> uint8_t _dataSize, uint8_t _ext);
141c149
< bool _setStatus, uint8_t _dataSize, uint8_t _ext);
---
> uint8_t _dataSize, uint8_t _ext);
157c165
< bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
---
> uint8_t _dataSize, uint8_t _ext) :
160c168
< _src1, _src2, _dest, _setStatus, _dataSize, _ext,
---
> _src1, _src2, _dest, _dataSize, _ext,
170c178
< bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
---
> uint8_t _dataSize, uint8_t _ext) :
173c181
< _src1, _src2, _dest, _setStatus, _dataSize, _ext,
---
> _src1, _src2, _dest, _dataSize, _ext,
190c198
< bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
---
> uint8_t _dataSize, uint8_t _ext) :
193c201
< _src1, _imm8, _dest, _setStatus, _dataSize, _ext,
---
> _src1, _imm8, _dest, _dataSize, _ext,
203c211
< bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
---
> uint8_t _dataSize, uint8_t _ext) :
206c214
< _src1, _imm8, _dest, _setStatus, _dataSize, _ext,
---
> _src1, _imm8, _dest, _dataSize, _ext,
213a222,237
> class X86MicroMeta(type):
> def __new__(mcls, name, bases, dict):
> abstract = False
> if "abstract" in dict:
> abstract = dict['abstract']
> del dict['abstract']
>
> cls = type.__new__(mcls, name, bases, dict)
> if not abstract:
> allClasses[name] = cls
> return cls
>
> class XXX86Microop(object):
> __metaclass__ = X86MicroMeta
> abstract = True
>
215c239,240
< def __init__(self, dest, src1, src2, setStatus):
---
> abstract = True
> def __init__(self, dest, src1, src2, flags):
219c244
< self.setStatus = setStatus
---
> self.flags = flags
221c246,252
< self.ext = 0
---
> if flags is None:
> self.ext = 0
> else:
> if not isinstance(flags, (list, tuple)):
> raise Exception, "flags must be a list or tuple of flags"
> self.ext = " | ".join(flags)
> self.className += "Flags"
226c257
< %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
---
> %(dataSize)s, %(ext)s)''' % {
231d261
< "setStatus" : self.cppBool(self.setStatus),
237c267,268
< def __init__(self, dest, src1, imm8, setStatus):
---
> abstract = True
> def __init__(self, dest, src1, imm8, flags):
241c272
< self.setStatus = setStatus
---
> self.flags = flags
243c274,280
< self.ext = 0
---
> if flags is None:
> self.ext = 0
> else:
> if not isinstance(flags, (list, tuple)):
> raise Exception, "flags must be a list or tuple of flags"
> self.ext = " | ".join(flags)
> self.className += "Flags"
248c285
< %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
---
> %(dataSize)s, %(ext)s)''' % {
253d289
< "setStatus" : self.cppBool(self.setStatus),
267c303,304
< def setUpMicroRegOp(name, Name, base, code, child, flagCode):
---
> # A function which builds the C++ classes that implement the microops
> def setUpMicroRegOp(name, Name, base, code, flagCode, condCheck):
275c312,313
< "flag_code" : flagCode})
---
> "flag_code" : flagCode,
> "cond_check" : condCheck})
280d317
< microopClasses[name] = child
282c319,325
< def defineMicroRegOp(mnemonic, code, flagCode):
---
> checkCCFlagBits = "checkCondition(ccFlagBits)"
> genCCFlagBits = "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, %s);"
>
>
> # This creates a python representations of a microop which are a cross
> # product of reg/immediate and flag/no flag versions.
> def defineMicroRegOp(mnemonic, code, secondSrc = "op2", cc=False):
293c336,345
< # Build the all register version of this micro op
---
> if not cc:
> flagCode = genCCFlagBits % secondSrc
> condCode = "true"
> else:
> flagCode = ""
> condCode = checkCCFlagBits
>
> regFlagCode = matcher.sub("SrcReg2", flagCode)
> immFlagCode = matcher.sub("imm8", flagCode)
>
295,298c347,350
< def __init__(self, dest, src1, src2, setStatus=False):
< super(RegOpChild, self).__init__(dest, src1, src2, setStatus)
< self.className = Name
< self.mnemonic = name
---
> mnemonic = name
> className = Name
> def __init__(self, dest, src1, src2, flags=None):
> super(RegOpChild, self).__init__(dest, src1, src2, flags)
300,301c352
< setUpMicroRegOp(name, Name, "X86ISA::RegOp", \
< regCode, RegOpChild, flagCode);
---
> microopClasses[name] = RegOpChild
303c354,356
< # Build the immediate version of this micro op
---
> setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true");
> setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, regFlagCode, condCode);
>
305,308c358,361
< def __init__(self, dest, src1, src2, setStatus=False):
< super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus)
< self.className = Name + "Imm"
< self.mnemonic = name + "i"
---
> mnemonic = name + 'i'
> className = Name + 'Imm'
> def __init__(self, dest, src1, src2, flags=None):
> super(RegOpChildImm, self).__init__(dest, src1, src2, flags)
310,311c363
< setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
< immCode, RegOpChildImm, flagCode);
---
> microopClasses[name + 'i'] = RegOpChildImm
313,321c365,366
< defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF
< defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "")
< defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF
< defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF
< defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "")
< defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF
< defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "")
< defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', "") #Needs to set OF,CF,SF and not DestReg
< defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', "")
---
> setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true");
> setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, immFlagCode, condCode);
322a368,377
> defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
> defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
> defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
> defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2')
> defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
> defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2')
> defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
> defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', '-op2')
> defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', cc=True)
>
335d389
< # Build the all register version of this micro op
337,340c391,394
< def __init__(self, src1, src2):
< super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False)
< self.className = Name
< self.mnemonic = name
---
> mnemonic = name
> className = Name
> def __init__(self, src1, src2, flags=None):
> super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags)
342c396
< setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, RegOpChild, "");
---
> microopClasses[name] = RegOpChild
344c398,400
< # Build the immediate version of this micro op
---
> setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true");
> setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, "", checkCCFlagBits);
>
345a402,403
> mnemonic = name
> className = Name
347,349c405
< super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False)
< self.className = Name + "Imm"
< self.mnemonic = name + "i"
---
> super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, None)
351,352c407
< setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
< immCode, RegOpChildImm, "");
---
> microopClasses[name + 'i'] = RegOpChildImm
353a409,411
> setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true");
> setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, "", checkCCFlagBits);
>
363c421
< super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False)
---
> super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None)
367c425
< setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, RegOpChild, "");
---
> microopClasses[name] = RegOpChild
368a427,428
> setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, "", "true");
>
377c437
< super(RegOpChild, self).__init__(dest, src1, src2, False)
---
> super(RegOpChild, self).__init__(dest, src1, src2, None)
381c441
< setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, RegOpChild, "");
---
> microopClasses[name] = RegOpChild
382a443,444
> setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, "", "true");
>