1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38//////////////////////////////////////////////////////////////////////////
39//
40// RegOp Microop templates
41//
42//////////////////////////////////////////////////////////////////////////
43
44def template MicroRegOpExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
47 {
48 Fault fault = NoFault;
49
50 DPRINTF(X86, "The data size is %d\n", dataSize);
51 %(op_decl)s;
52 %(op_rd)s;
53
54 IntReg result M5_VAR_USED;
55
56 if(%(cond_check)s)
57 {
58 %(code)s;
59 %(flag_code)s;
60 }
61 else
62 {
63 %(else_code)s;
64 }
65
66 //Write the resulting state to the execution context
67 if(fault == NoFault)
68 {
69 %(op_wb)s;
70 }
71 return fault;
72 }
73}};
74
75def template MicroRegOpImmExecute {{
76 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
77 Trace::InstRecord *traceData) const
78 {
79 Fault fault = NoFault;
80
81 %(op_decl)s;
82 %(op_rd)s;
83
84 IntReg result M5_VAR_USED;
85
86 if(%(cond_check)s)
87 {
88 %(code)s;
89 %(flag_code)s;
90 }
91 else
92 {
93 %(else_code)s;
94 }
95
96 //Write the resulting state to the execution context
97 if(fault == NoFault)
98 {
99 %(op_wb)s;
100 }
101 return fault;
102 }
103}};
104
105def template MicroRegOpDeclare {{
106 class %(class_name)s : public %(base_class)s
107 {
108 public:
109 %(class_name)s(ExtMachInst _machInst,
110 const char * instMnem, uint64_t setFlags,
111 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
112 uint8_t _dataSize, uint16_t _ext);
113
114 %(BasicExecDeclare)s
115 };
116}};
117
118def template MicroRegOpImmDeclare {{
119
120 class %(class_name)s : public %(base_class)s
121 {
122 public:
123 %(class_name)s(ExtMachInst _machInst,
124 const char * instMnem, uint64_t setFlags,
125 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
126 uint8_t _dataSize, uint16_t _ext);
127
128 %(BasicExecDeclare)s
129 };
130}};
131
132def template MicroRegOpConstructor {{
133 inline %(class_name)s::%(class_name)s(
134 ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
135 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
136 uint8_t _dataSize, uint16_t _ext) :
137 %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
138 _src1, _src2, _dest, _dataSize, _ext,
139 %(op_class)s)
140 {
141 %(constructor)s;
142 %(cond_control_flag_init)s;
143 }
144}};
145
146def template MicroRegOpImmConstructor {{
147 inline %(class_name)s::%(class_name)s(
148 ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
149 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
150 uint8_t _dataSize, uint16_t _ext) :
151 %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
152 _src1, _imm8, _dest, _dataSize, _ext,
153 %(op_class)s)
154 {
155 %(constructor)s;
156 %(cond_control_flag_init)s;
157 }
158}};
159
160output header {{
161 void
162 divide(uint64_t dividend, uint64_t divisor,
163 uint64_t "ient, uint64_t &remainder);
164
165 enum SegmentSelectorCheck {
166 SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck,
167 SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck,
168 SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck
169 };
170
171 enum LongModeDescriptorType {
172 LDT64 = 2,
173 AvailableTSS64 = 9,
174 BusyTSS64 = 0xb,
175 CallGate64 = 0xc,
176 IntGate64 = 0xe,
177 TrapGate64 = 0xf
178 };
179}};
180
181output decoder {{
182 void
183 divide(uint64_t dividend, uint64_t divisor,
184 uint64_t "ient, uint64_t &remainder)
185 {
186 //Check for divide by zero.
187 assert(divisor != 0);
188 //If the divisor is bigger than the dividend, don't do anything.
189 if (divisor <= dividend) {
190 //Shift the divisor so it's msb lines up with the dividend.
191 int dividendMsb = findMsbSet(dividend);
192 int divisorMsb = findMsbSet(divisor);
193 int shift = dividendMsb - divisorMsb;
194 divisor <<= shift;
195 //Compute what we'll add to the quotient if the divisor isn't
196 //now larger than the dividend.
197 uint64_t quotientBit = 1;
198 quotientBit <<= shift;
199 //If we need to step back a bit (no pun intended) because the
200 //divisor got too to large, do that here. This is the "or two"
201 //part of one or two bit division.
202 if (divisor > dividend) {
203 quotientBit >>= 1;
204 divisor >>= 1;
205 }
206 //Decrement the remainder and increment the quotient.
207 quotient += quotientBit;
208 remainder -= divisor;
209 }
210 }
211}};
212
213let {{
214 # Make these empty strings so that concatenating onto
215 # them will always work.
216 header_output = ""
217 decoder_output = ""
218 exec_output = ""
219
220 immTemplates = (
221 MicroRegOpImmDeclare,
222 MicroRegOpImmConstructor,
223 MicroRegOpImmExecute)
224
225 regTemplates = (
226 MicroRegOpDeclare,
227 MicroRegOpConstructor,
228 MicroRegOpExecute)
229
230 class RegOpMeta(type):
231 def buildCppClasses(self, name, Name, suffix, code, big_code, \
232 flag_code, cond_check, else_code, cond_control_flag_init):
233
234 # Globals to stick the output in
235 global header_output
236 global decoder_output
237 global exec_output
238
239 # Stick all the code together so it can be searched at once
240 allCode = "|".join((code, flag_code, cond_check, else_code,
241 cond_control_flag_init))
242 allBigCode = "|".join((big_code, flag_code, cond_check, else_code,
243 cond_control_flag_init))
244
245 # If op2 is used anywhere, make register and immediate versions
246 # of this code.
| 1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38//////////////////////////////////////////////////////////////////////////
39//
40// RegOp Microop templates
41//
42//////////////////////////////////////////////////////////////////////////
43
44def template MicroRegOpExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
47 {
48 Fault fault = NoFault;
49
50 DPRINTF(X86, "The data size is %d\n", dataSize);
51 %(op_decl)s;
52 %(op_rd)s;
53
54 IntReg result M5_VAR_USED;
55
56 if(%(cond_check)s)
57 {
58 %(code)s;
59 %(flag_code)s;
60 }
61 else
62 {
63 %(else_code)s;
64 }
65
66 //Write the resulting state to the execution context
67 if(fault == NoFault)
68 {
69 %(op_wb)s;
70 }
71 return fault;
72 }
73}};
74
75def template MicroRegOpImmExecute {{
76 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
77 Trace::InstRecord *traceData) const
78 {
79 Fault fault = NoFault;
80
81 %(op_decl)s;
82 %(op_rd)s;
83
84 IntReg result M5_VAR_USED;
85
86 if(%(cond_check)s)
87 {
88 %(code)s;
89 %(flag_code)s;
90 }
91 else
92 {
93 %(else_code)s;
94 }
95
96 //Write the resulting state to the execution context
97 if(fault == NoFault)
98 {
99 %(op_wb)s;
100 }
101 return fault;
102 }
103}};
104
105def template MicroRegOpDeclare {{
106 class %(class_name)s : public %(base_class)s
107 {
108 public:
109 %(class_name)s(ExtMachInst _machInst,
110 const char * instMnem, uint64_t setFlags,
111 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
112 uint8_t _dataSize, uint16_t _ext);
113
114 %(BasicExecDeclare)s
115 };
116}};
117
118def template MicroRegOpImmDeclare {{
119
120 class %(class_name)s : public %(base_class)s
121 {
122 public:
123 %(class_name)s(ExtMachInst _machInst,
124 const char * instMnem, uint64_t setFlags,
125 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
126 uint8_t _dataSize, uint16_t _ext);
127
128 %(BasicExecDeclare)s
129 };
130}};
131
132def template MicroRegOpConstructor {{
133 inline %(class_name)s::%(class_name)s(
134 ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
135 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
136 uint8_t _dataSize, uint16_t _ext) :
137 %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
138 _src1, _src2, _dest, _dataSize, _ext,
139 %(op_class)s)
140 {
141 %(constructor)s;
142 %(cond_control_flag_init)s;
143 }
144}};
145
146def template MicroRegOpImmConstructor {{
147 inline %(class_name)s::%(class_name)s(
148 ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
149 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
150 uint8_t _dataSize, uint16_t _ext) :
151 %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
152 _src1, _imm8, _dest, _dataSize, _ext,
153 %(op_class)s)
154 {
155 %(constructor)s;
156 %(cond_control_flag_init)s;
157 }
158}};
159
160output header {{
161 void
162 divide(uint64_t dividend, uint64_t divisor,
163 uint64_t "ient, uint64_t &remainder);
164
165 enum SegmentSelectorCheck {
166 SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck,
167 SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck,
168 SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck
169 };
170
171 enum LongModeDescriptorType {
172 LDT64 = 2,
173 AvailableTSS64 = 9,
174 BusyTSS64 = 0xb,
175 CallGate64 = 0xc,
176 IntGate64 = 0xe,
177 TrapGate64 = 0xf
178 };
179}};
180
181output decoder {{
182 void
183 divide(uint64_t dividend, uint64_t divisor,
184 uint64_t "ient, uint64_t &remainder)
185 {
186 //Check for divide by zero.
187 assert(divisor != 0);
188 //If the divisor is bigger than the dividend, don't do anything.
189 if (divisor <= dividend) {
190 //Shift the divisor so it's msb lines up with the dividend.
191 int dividendMsb = findMsbSet(dividend);
192 int divisorMsb = findMsbSet(divisor);
193 int shift = dividendMsb - divisorMsb;
194 divisor <<= shift;
195 //Compute what we'll add to the quotient if the divisor isn't
196 //now larger than the dividend.
197 uint64_t quotientBit = 1;
198 quotientBit <<= shift;
199 //If we need to step back a bit (no pun intended) because the
200 //divisor got too to large, do that here. This is the "or two"
201 //part of one or two bit division.
202 if (divisor > dividend) {
203 quotientBit >>= 1;
204 divisor >>= 1;
205 }
206 //Decrement the remainder and increment the quotient.
207 quotient += quotientBit;
208 remainder -= divisor;
209 }
210 }
211}};
212
213let {{
214 # Make these empty strings so that concatenating onto
215 # them will always work.
216 header_output = ""
217 decoder_output = ""
218 exec_output = ""
219
220 immTemplates = (
221 MicroRegOpImmDeclare,
222 MicroRegOpImmConstructor,
223 MicroRegOpImmExecute)
224
225 regTemplates = (
226 MicroRegOpDeclare,
227 MicroRegOpConstructor,
228 MicroRegOpExecute)
229
230 class RegOpMeta(type):
231 def buildCppClasses(self, name, Name, suffix, code, big_code, \
232 flag_code, cond_check, else_code, cond_control_flag_init):
233
234 # Globals to stick the output in
235 global header_output
236 global decoder_output
237 global exec_output
238
239 # Stick all the code together so it can be searched at once
240 allCode = "|".join((code, flag_code, cond_check, else_code,
241 cond_control_flag_init))
242 allBigCode = "|".join((big_code, flag_code, cond_check, else_code,
243 cond_control_flag_init))
244
245 # If op2 is used anywhere, make register and immediate versions
246 # of this code.
|
248 match = matcher.search(allCode + allBigCode)
249 if match:
250 typeQual = ""
251 if match.group("typeQual"):
252 typeQual = match.group("typeQual")
253 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
254 self.buildCppClasses(name, Name, suffix,
255 matcher.sub(src2_name, code),
256 matcher.sub(src2_name, big_code),
257 matcher.sub(src2_name, flag_code),
258 matcher.sub(src2_name, cond_check),
259 matcher.sub(src2_name, else_code),
260 matcher.sub(src2_name, cond_control_flag_init))
261 imm_name = "%simm8" % match.group("prefix")
262 self.buildCppClasses(name + "i", Name, suffix + "Imm",
263 matcher.sub(imm_name, code),
264 matcher.sub(imm_name, big_code),
265 matcher.sub(imm_name, flag_code),
266 matcher.sub(imm_name, cond_check),
267 matcher.sub(imm_name, else_code),
268 matcher.sub(imm_name, cond_control_flag_init))
269 return
270
271 # If there's something optional to do with flags, generate
272 # a version without it and fix up this version to use it.
273 if flag_code != "" or cond_check != "true":
274 self.buildCppClasses(name, Name, suffix,
275 code, big_code, "", "true", else_code, "")
276 suffix = "Flags" + suffix
277
278 # If psrc1 or psrc2 is used, we need to actually insert code to
279 # compute it.
280 for (big, all) in ((False, allCode), (True, allBigCode)):
281 prefix = ""
282 for (rex, decl) in (
283 ("(?<!\w)psrc1(?!\w)",
284 "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"),
285 ("(?<!\w)psrc2(?!\w)",
286 "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"),
287 ("(?<!\w)spsrc1(?!\w)",
288 "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"),
289 ("(?<!\w)spsrc2(?!\w)",
290 "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"),
291 ("(?<!\w)simm8(?!\w)",
292 "int8_t simm8 = imm8;")):
293 matcher = re.compile(rex)
294 if matcher.search(all):
295 prefix += decl + "\n"
296 if big:
297 if big_code != "":
298 big_code = prefix + big_code
299 else:
300 code = prefix + code
301
302 base = "X86ISA::RegOp"
303
304 # If imm8 shows up in the code, use the immediate templates, if
305 # not, hopefully the register ones will be correct.
306 templates = regTemplates
307 matcher = re.compile("(?<!\w)s?imm8(?!\w)")
308 if matcher.search(allCode):
309 base += "Imm"
310 templates = immTemplates
311
312 # Get everything ready for the substitution
313 iops = [InstObjParams(name, Name + suffix, base,
314 {"code" : code,
315 "flag_code" : flag_code,
316 "cond_check" : cond_check,
317 "else_code" : else_code,
318 "cond_control_flag_init" : cond_control_flag_init})]
319 if big_code != "":
320 iops += [InstObjParams(name, Name + suffix + "Big", base,
321 {"code" : big_code,
322 "flag_code" : flag_code,
323 "cond_check" : cond_check,
324 "else_code" : else_code,
325 "cond_control_flag_init" :
326 cond_control_flag_init})]
327
328 # Generate the actual code (finally!)
329 for iop in iops:
330 header_output += templates[0].subst(iop)
331 decoder_output += templates[1].subst(iop)
332 exec_output += templates[2].subst(iop)
333
334
335 def __new__(mcls, Name, bases, dict):
336 abstract = False
337 name = Name.lower()
338 if "abstract" in dict:
339 abstract = dict['abstract']
340 del dict['abstract']
341
342 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
343 if not abstract:
344 cls.className = Name
345 cls.base_mnemonic = name
346 code = cls.code
347 big_code = cls.big_code
348 flag_code = cls.flag_code
349 cond_check = cls.cond_check
350 else_code = cls.else_code
351 cond_control_flag_init = cls.cond_control_flag_init
352
353 # Set up the C++ classes
354 mcls.buildCppClasses(cls, name, Name, "", code, big_code,
355 flag_code, cond_check, else_code,
356 cond_control_flag_init)
357
358 # Hook into the microassembler dict
359 global microopClasses
360 microopClasses[name] = cls
361
362 allCode = "|".join((code, flag_code, cond_check, else_code,
363 cond_control_flag_init))
364
365 # If op2 is used anywhere, make register and immediate versions
366 # of this code.
| 248 match = matcher.search(allCode + allBigCode)
249 if match:
250 typeQual = ""
251 if match.group("typeQual"):
252 typeQual = match.group("typeQual")
253 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
254 self.buildCppClasses(name, Name, suffix,
255 matcher.sub(src2_name, code),
256 matcher.sub(src2_name, big_code),
257 matcher.sub(src2_name, flag_code),
258 matcher.sub(src2_name, cond_check),
259 matcher.sub(src2_name, else_code),
260 matcher.sub(src2_name, cond_control_flag_init))
261 imm_name = "%simm8" % match.group("prefix")
262 self.buildCppClasses(name + "i", Name, suffix + "Imm",
263 matcher.sub(imm_name, code),
264 matcher.sub(imm_name, big_code),
265 matcher.sub(imm_name, flag_code),
266 matcher.sub(imm_name, cond_check),
267 matcher.sub(imm_name, else_code),
268 matcher.sub(imm_name, cond_control_flag_init))
269 return
270
271 # If there's something optional to do with flags, generate
272 # a version without it and fix up this version to use it.
273 if flag_code != "" or cond_check != "true":
274 self.buildCppClasses(name, Name, suffix,
275 code, big_code, "", "true", else_code, "")
276 suffix = "Flags" + suffix
277
278 # If psrc1 or psrc2 is used, we need to actually insert code to
279 # compute it.
280 for (big, all) in ((False, allCode), (True, allBigCode)):
281 prefix = ""
282 for (rex, decl) in (
283 ("(?<!\w)psrc1(?!\w)",
284 "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"),
285 ("(?<!\w)psrc2(?!\w)",
286 "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"),
287 ("(?<!\w)spsrc1(?!\w)",
288 "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"),
289 ("(?<!\w)spsrc2(?!\w)",
290 "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"),
291 ("(?<!\w)simm8(?!\w)",
292 "int8_t simm8 = imm8;")):
293 matcher = re.compile(rex)
294 if matcher.search(all):
295 prefix += decl + "\n"
296 if big:
297 if big_code != "":
298 big_code = prefix + big_code
299 else:
300 code = prefix + code
301
302 base = "X86ISA::RegOp"
303
304 # If imm8 shows up in the code, use the immediate templates, if
305 # not, hopefully the register ones will be correct.
306 templates = regTemplates
307 matcher = re.compile("(?<!\w)s?imm8(?!\w)")
308 if matcher.search(allCode):
309 base += "Imm"
310 templates = immTemplates
311
312 # Get everything ready for the substitution
313 iops = [InstObjParams(name, Name + suffix, base,
314 {"code" : code,
315 "flag_code" : flag_code,
316 "cond_check" : cond_check,
317 "else_code" : else_code,
318 "cond_control_flag_init" : cond_control_flag_init})]
319 if big_code != "":
320 iops += [InstObjParams(name, Name + suffix + "Big", base,
321 {"code" : big_code,
322 "flag_code" : flag_code,
323 "cond_check" : cond_check,
324 "else_code" : else_code,
325 "cond_control_flag_init" :
326 cond_control_flag_init})]
327
328 # Generate the actual code (finally!)
329 for iop in iops:
330 header_output += templates[0].subst(iop)
331 decoder_output += templates[1].subst(iop)
332 exec_output += templates[2].subst(iop)
333
334
335 def __new__(mcls, Name, bases, dict):
336 abstract = False
337 name = Name.lower()
338 if "abstract" in dict:
339 abstract = dict['abstract']
340 del dict['abstract']
341
342 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
343 if not abstract:
344 cls.className = Name
345 cls.base_mnemonic = name
346 code = cls.code
347 big_code = cls.big_code
348 flag_code = cls.flag_code
349 cond_check = cls.cond_check
350 else_code = cls.else_code
351 cond_control_flag_init = cls.cond_control_flag_init
352
353 # Set up the C++ classes
354 mcls.buildCppClasses(cls, name, Name, "", code, big_code,
355 flag_code, cond_check, else_code,
356 cond_control_flag_init)
357
358 # Hook into the microassembler dict
359 global microopClasses
360 microopClasses[name] = cls
361
362 allCode = "|".join((code, flag_code, cond_check, else_code,
363 cond_control_flag_init))
364
365 # If op2 is used anywhere, make register and immediate versions
366 # of this code.
|
368 if matcher.search(allCode):
369 microopClasses[name + 'i'] = cls
370 return cls
371
372
373 class RegOp(X86Microop):
374 __metaclass__ = RegOpMeta
375 # This class itself doesn't act as a microop
376 abstract = True
377
378 # Default template parameter values
379 big_code = ""
380 flag_code = ""
381 cond_check = "true"
382 else_code = ";"
383 cond_control_flag_init = ""
384
385 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
386 self.dest = dest
387 self.src1 = src1
388 self.op2 = op2
389 self.flags = flags
390 self.dataSize = dataSize
391 if flags is None:
392 self.ext = 0
393 else:
394 if not isinstance(flags, (list, tuple)):
395 raise Exception, "flags must be a list or tuple of flags"
396 self.ext = " | ".join(flags)
397 self.className += "Flags"
398
399 def getAllocator(self, microFlags):
400 if self.big_code != "":
401 className = self.className
402 if self.mnemonic == self.base_mnemonic + 'i':
403 className += "Imm"
404 allocString = '''
405 (%(dataSize)s >= 4) ?
406 (StaticInstPtr)(new %(class_name)sBig(machInst,
407 macrocodeBlock, %(flags)s, %(src1)s, %(op2)s,
408 %(dest)s, %(dataSize)s, %(ext)s)) :
409 (StaticInstPtr)(new %(class_name)s(machInst,
410 macrocodeBlock, %(flags)s, %(src1)s, %(op2)s,
411 %(dest)s, %(dataSize)s, %(ext)s))
412 '''
413 allocator = allocString % {
414 "class_name" : className,
415 "flags" : self.microFlagsText(microFlags),
416 "src1" : self.src1, "op2" : self.op2,
417 "dest" : self.dest,
418 "dataSize" : self.dataSize,
419 "ext" : self.ext}
420 return allocator
421 else:
422 className = self.className
423 if self.mnemonic == self.base_mnemonic + 'i':
424 className += "Imm"
425 allocator = '''new %(class_name)s(machInst, macrocodeBlock,
426 %(flags)s, %(src1)s, %(op2)s, %(dest)s,
427 %(dataSize)s, %(ext)s)''' % {
428 "class_name" : className,
429 "flags" : self.microFlagsText(microFlags),
430 "src1" : self.src1, "op2" : self.op2,
431 "dest" : self.dest,
432 "dataSize" : self.dataSize,
433 "ext" : self.ext}
434 return allocator
435
436 class LogicRegOp(RegOp):
437 abstract = True
438 flag_code = '''
439 //Don't have genFlags handle the OF or CF bits
440 uint64_t mask = CFBit | ECFBit | OFBit;
441 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, result, psrc1, op2);
442 //If a logic microop wants to set these, it wants to set them to 0.
443 ccFlagBits &= ~(CFBit & ext);
444 ccFlagBits &= ~(ECFBit & ext);
445 ccFlagBits &= ~(OFBit & ext);
446 '''
447
448 class FlagRegOp(RegOp):
449 abstract = True
450 flag_code = \
451 "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);"
452
453 class SubRegOp(RegOp):
454 abstract = True
455 flag_code = \
456 "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);"
457
458 class CondRegOp(RegOp):
459 abstract = True
460 cond_check = "checkCondition(ccFlagBits, ext)"
461 cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];"
462
463 class RdRegOp(RegOp):
464 abstract = True
465 def __init__(self, dest, src1=None, dataSize="env.dataSize"):
466 if not src1:
467 src1 = dest
468 super(RdRegOp, self).__init__(dest, src1, \
469 "InstRegIndex(NUM_INTREGS)", None, dataSize)
470
471 class WrRegOp(RegOp):
472 abstract = True
473 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
474 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
475 src1, src2, flags, dataSize)
476
477 class Add(FlagRegOp):
478 code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);'
479 big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);'
480
481 class Or(LogicRegOp):
482 code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);'
483 big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);'
484
485 class Adc(FlagRegOp):
486 code = '''
487 CCFlagBits flags = ccFlagBits;
488 DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize);
489 '''
490 big_code = '''
491 CCFlagBits flags = ccFlagBits;
492 DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
493 '''
494
495 class Sbb(SubRegOp):
496 code = '''
497 CCFlagBits flags = ccFlagBits;
498 DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize);
499 '''
500 big_code = '''
501 CCFlagBits flags = ccFlagBits;
502 DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
503 '''
504
505 class And(LogicRegOp):
506 code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)'
507 big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)'
508
509 class Sub(SubRegOp):
510 code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)'
511 big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)'
512
513 class Xor(LogicRegOp):
514 code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)'
515 big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)'
516
517 class Mul1s(WrRegOp):
518 code = '''
519 ProdLow = psrc1 * op2;
520 int halfSize = (dataSize * 8) / 2;
521 uint64_t shifter = (ULL(1) << halfSize);
522 uint64_t hiResult;
523 uint64_t psrc1_h = psrc1 / shifter;
524 uint64_t psrc1_l = psrc1 & mask(halfSize);
525 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
526 uint64_t psrc2_l = op2 & mask(halfSize);
527 hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
528 ((psrc1_l * psrc2_l) / shifter)) /shifter) +
529 psrc1_h * psrc2_h;
530 if (bits(psrc1, dataSize * 8 - 1))
531 hiResult -= op2;
532 if (bits(op2, dataSize * 8 - 1))
533 hiResult -= psrc1;
534 ProdHi = hiResult;
535 '''
536 flag_code = '''
537 if ((-ProdHi & mask(dataSize * 8)) !=
538 bits(ProdLow, dataSize * 8 - 1)) {
539 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
540 } else {
541 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
542 }
543 '''
544
545 class Mul1u(WrRegOp):
546 code = '''
547 ProdLow = psrc1 * op2;
548 int halfSize = (dataSize * 8) / 2;
549 uint64_t shifter = (ULL(1) << halfSize);
550 uint64_t psrc1_h = psrc1 / shifter;
551 uint64_t psrc1_l = psrc1 & mask(halfSize);
552 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
553 uint64_t psrc2_l = op2 & mask(halfSize);
554 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
555 ((psrc1_l * psrc2_l) / shifter)) / shifter) +
556 psrc1_h * psrc2_h;
557 '''
558 flag_code = '''
559 if (ProdHi) {
560 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
561 } else {
562 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
563 }
564 '''
565
566 class Mulel(RdRegOp):
567 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
568 big_code = 'DestReg = ProdLow & mask(dataSize * 8);'
569
570 class Muleh(RdRegOp):
571 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
572 if not src1:
573 src1 = dest
574 super(RdRegOp, self).__init__(dest, src1, \
575 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
576 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
577 big_code = 'DestReg = ProdHi & mask(dataSize * 8);'
578
579 # One or two bit divide
580 class Div1(WrRegOp):
581 code = '''
582 //These are temporaries so that modifying them later won't make
583 //the ISA parser think they're also sources.
584 uint64_t quotient = 0;
585 uint64_t remainder = psrc1;
586 //Similarly, this is a temporary so changing it doesn't make it
587 //a source.
588 uint64_t divisor = op2;
589 //This is a temporary just for consistency and clarity.
590 uint64_t dividend = remainder;
591 //Do the division.
592 if (divisor == 0) {
593 fault = new DivideByZero;
594 } else {
595 divide(dividend, divisor, quotient, remainder);
596 //Record the final results.
597 Remainder = remainder;
598 Quotient = quotient;
599 Divisor = divisor;
600 }
601 '''
602
603 # Step divide
604 class Div2(RegOp):
605 divCode = '''
606 uint64_t dividend = Remainder;
607 uint64_t divisor = Divisor;
608 uint64_t quotient = Quotient;
609 uint64_t remainder = dividend;
610 int remaining = op2;
611 //If we overshot, do nothing. This lets us unrool division loops a
612 //little.
613 if (divisor == 0) {
614 fault = new DivideByZero;
615 } else if (remaining) {
616 if (divisor & (ULL(1) << 63)) {
617 while (remaining && !(dividend & (ULL(1) << 63))) {
618 dividend = (dividend << 1) |
619 bits(SrcReg1, remaining - 1);
620 quotient <<= 1;
621 remaining--;
622 }
623 if (dividend & (ULL(1) << 63)) {
624 bool highBit = false;
625 if (dividend < divisor && remaining) {
626 highBit = true;
627 dividend = (dividend << 1) |
628 bits(SrcReg1, remaining - 1);
629 quotient <<= 1;
630 remaining--;
631 }
632 if (highBit || divisor <= dividend) {
633 quotient++;
634 dividend -= divisor;
635 }
636 }
637 remainder = dividend;
638 } else {
639 //Shift in bits from the low order portion of the dividend
640 while (dividend < divisor && remaining) {
641 dividend = (dividend << 1) |
642 bits(SrcReg1, remaining - 1);
643 quotient <<= 1;
644 remaining--;
645 }
646 remainder = dividend;
647 //Do the division.
648 divide(dividend, divisor, quotient, remainder);
649 }
650 }
651 //Keep track of how many bits there are still to pull in.
652 %s
653 //Record the final results
654 Remainder = remainder;
655 Quotient = quotient;
656 '''
657 code = divCode % "DestReg = merge(DestReg, remaining, dataSize);"
658 big_code = divCode % "DestReg = remaining & mask(dataSize * 8);"
659 flag_code = '''
660 if (remaining == 0)
661 ccFlagBits = ccFlagBits | (ext & EZFBit);
662 else
663 ccFlagBits = ccFlagBits & ~(ext & EZFBit);
664 '''
665
666 class Divq(RdRegOp):
667 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
668 big_code = 'DestReg = Quotient & mask(dataSize * 8);'
669
670 class Divr(RdRegOp):
671 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
672 big_code = 'DestReg = Remainder & mask(dataSize * 8);'
673
674 class Mov(CondRegOp):
675 code = 'DestReg = merge(SrcReg1, op2, dataSize)'
676 else_code = 'DestReg = DestReg;'
677
678 # Shift instructions
679
680 class Sll(RegOp):
681 code = '''
682 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
683 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
684 '''
685 big_code = '''
686 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
687 DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8);
688 '''
689 flag_code = '''
690 // If the shift amount is zero, no flags should be modified.
691 if (shiftAmt) {
692 //Zero out any flags we might modify. This way we only have to
693 //worry about setting them.
694 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
695 int CFBits = 0;
696 //Figure out if we -would- set the CF bits if requested.
697 if (shiftAmt <= dataSize * 8 &&
698 bits(SrcReg1, dataSize * 8 - shiftAmt)) {
699 CFBits = 1;
700 }
701 //If some combination of the CF bits need to be set, set them.
702 if ((ext & (CFBit | ECFBit)) && CFBits)
703 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
704 //Figure out what the OF bit should be.
705 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
706 ccFlagBits = ccFlagBits | OFBit;
707 //Use the regular mechanisms to calculate the other flags.
708 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
709 DestReg, psrc1, op2);
710 }
711 '''
712
713 class Srl(RegOp):
714 # Because what happens to the bits shift -in- on a right shift
715 # is not defined in the C/C++ standard, we have to mask them out
716 # to be sure they're zero.
717 code = '''
718 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
719 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
720 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
721 '''
722 big_code = '''
723 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
724 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
725 DestReg = (psrc1 >> shiftAmt) & logicalMask;
726 '''
727 flag_code = '''
728 // If the shift amount is zero, no flags should be modified.
729 if (shiftAmt) {
730 //Zero out any flags we might modify. This way we only have to
731 //worry about setting them.
732 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
733 //If some combination of the CF bits need to be set, set them.
734 if ((ext & (CFBit | ECFBit)) &&
735 shiftAmt <= dataSize * 8 &&
736 bits(SrcReg1, shiftAmt - 1)) {
737 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
738 }
739 //Figure out what the OF bit should be.
740 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
741 ccFlagBits = ccFlagBits | OFBit;
742 //Use the regular mechanisms to calculate the other flags.
743 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
744 DestReg, psrc1, op2);
745 }
746 '''
747
748 class Sra(RegOp):
749 # Because what happens to the bits shift -in- on a right shift
750 # is not defined in the C/C++ standard, we have to sign extend
751 # them manually to be sure.
752 code = '''
753 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
754 uint64_t arithMask = (shiftAmt == 0) ? 0 :
755 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
756 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
757 '''
758 big_code = '''
759 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
760 uint64_t arithMask = (shiftAmt == 0) ? 0 :
761 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
762 DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8);
763 '''
764 flag_code = '''
765 // If the shift amount is zero, no flags should be modified.
766 if (shiftAmt) {
767 //Zero out any flags we might modify. This way we only have to
768 //worry about setting them.
769 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
770 //If some combination of the CF bits need to be set, set them.
771 uint8_t effectiveShift =
772 (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8);
773 if ((ext & (CFBit | ECFBit)) &&
774 bits(SrcReg1, effectiveShift - 1)) {
775 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
776 }
777 //Use the regular mechanisms to calculate the other flags.
778 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
779 DestReg, psrc1, op2);
780 }
781 '''
782
783 class Ror(RegOp):
784 code = '''
785 uint8_t shiftAmt =
786 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
787 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
788 if (realShiftAmt) {
789 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt);
790 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt);
791 DestReg = merge(DestReg, top | bottom, dataSize);
792 } else
793 DestReg = merge(DestReg, DestReg, dataSize);
794 '''
795 flag_code = '''
796 // If the shift amount is zero, no flags should be modified.
797 if (shiftAmt) {
798 //Zero out any flags we might modify. This way we only have to
799 //worry about setting them.
800 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
801 //Find the most and second most significant bits of the result.
802 int msb = bits(DestReg, dataSize * 8 - 1);
803 int smsb = bits(DestReg, dataSize * 8 - 2);
804 //If some combination of the CF bits need to be set, set them.
805 if ((ext & (CFBit | ECFBit)) && msb)
806 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
807 //Figure out what the OF bit should be.
808 if ((ext & OFBit) && (msb ^ smsb))
809 ccFlagBits = ccFlagBits | OFBit;
810 //Use the regular mechanisms to calculate the other flags.
811 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
812 DestReg, psrc1, op2);
813 }
814 '''
815
816 class Rcr(RegOp):
817 code = '''
818 uint8_t shiftAmt =
819 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
820 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
821 if (realShiftAmt) {
822 CCFlagBits flags = ccFlagBits;
823 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt);
824 if (realShiftAmt > 1)
825 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1);
826 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt);
827 DestReg = merge(DestReg, top | bottom, dataSize);
828 } else
829 DestReg = merge(DestReg, DestReg, dataSize);
830 '''
831 flag_code = '''
832 // If the shift amount is zero, no flags should be modified.
833 if (shiftAmt) {
834 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
835 //Zero out any flags we might modify. This way we only have to
836 //worry about setting them.
837 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
838 //Figure out what the OF bit should be.
839 if ((ext & OFBit) && (origCFBit ^
840 bits(SrcReg1, dataSize * 8 - 1))) {
841 ccFlagBits = ccFlagBits | OFBit;
842 }
843 //If some combination of the CF bits need to be set, set them.
844 if ((ext & (CFBit | ECFBit)) &&
845 (realShiftAmt == 0) ? origCFBit :
846 bits(SrcReg1, realShiftAmt - 1)) {
847 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
848 }
849 //Use the regular mechanisms to calculate the other flags.
850 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
851 DestReg, psrc1, op2);
852 }
853 '''
854
855 class Rol(RegOp):
856 code = '''
857 uint8_t shiftAmt =
858 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
859 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
860 if (realShiftAmt) {
861 uint64_t top = psrc1 << realShiftAmt;
862 uint64_t bottom =
863 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt);
864 DestReg = merge(DestReg, top | bottom, dataSize);
865 } else
866 DestReg = merge(DestReg, DestReg, dataSize);
867 '''
868 flag_code = '''
869 // If the shift amount is zero, no flags should be modified.
870 if (shiftAmt) {
871 //Zero out any flags we might modify. This way we only have to
872 //worry about setting them.
873 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
874 //The CF bits, if set, would be set to the lsb of the result.
875 int lsb = DestReg & 0x1;
876 int msb = bits(DestReg, dataSize * 8 - 1);
877 //If some combination of the CF bits need to be set, set them.
878 if ((ext & (CFBit | ECFBit)) && lsb)
879 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
880 //Figure out what the OF bit should be.
881 if ((ext & OFBit) && (msb ^ lsb))
882 ccFlagBits = ccFlagBits | OFBit;
883 //Use the regular mechanisms to calculate the other flags.
884 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
885 DestReg, psrc1, op2);
886 }
887 '''
888
889 class Rcl(RegOp):
890 code = '''
891 uint8_t shiftAmt =
892 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
893 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
894 if (realShiftAmt) {
895 CCFlagBits flags = ccFlagBits;
896 uint64_t top = psrc1 << realShiftAmt;
897 uint64_t bottom = flags.cf << (realShiftAmt - 1);
898 if(shiftAmt > 1)
899 bottom |=
900 bits(psrc1, dataSize * 8 - 1,
901 dataSize * 8 - realShiftAmt + 1);
902 DestReg = merge(DestReg, top | bottom, dataSize);
903 } else
904 DestReg = merge(DestReg, DestReg, dataSize);
905 '''
906 flag_code = '''
907 // If the shift amount is zero, no flags should be modified.
908 if (shiftAmt) {
909 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
910 //Zero out any flags we might modify. This way we only have to
911 //worry about setting them.
912 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
913 int msb = bits(DestReg, dataSize * 8 - 1);
914 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt);
915 //If some combination of the CF bits need to be set, set them.
916 if ((ext & (CFBit | ECFBit)) &&
917 (realShiftAmt == 0) ? origCFBit : CFBits)
918 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
919 //Figure out what the OF bit should be.
920 if ((ext & OFBit) && (msb ^ CFBits))
921 ccFlagBits = ccFlagBits | OFBit;
922 //Use the regular mechanisms to calculate the other flags.
923 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
924 DestReg, psrc1, op2);
925 }
926 '''
927
928 class Sld(RegOp):
929 sldCode = '''
930 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
931 uint8_t dataBits = dataSize * 8;
932 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);
933 uint64_t result;
934 if (realShiftAmt == 0) {
935 result = psrc1;
936 } else if (realShiftAmt < dataBits) {
937 result = (psrc1 << realShiftAmt) |
938 (DoubleBits >> (dataBits - realShiftAmt));
939 } else {
940 result = (DoubleBits << (realShiftAmt - dataBits)) |
941 (psrc1 >> (2 * dataBits - realShiftAmt));
942 }
943 %s
944 '''
945 code = sldCode % "DestReg = merge(DestReg, result, dataSize);"
946 big_code = sldCode % "DestReg = result & mask(dataSize * 8);"
947 flag_code = '''
948 // If the shift amount is zero, no flags should be modified.
949 if (shiftAmt) {
950 //Zero out any flags we might modify. This way we only have to
951 //worry about setting them.
952 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
953 int CFBits = 0;
954 //Figure out if we -would- set the CF bits if requested.
955 if ((realShiftAmt == 0 &&
956 bits(DoubleBits, 0)) ||
957 (realShiftAmt <= dataBits &&
958 bits(SrcReg1, dataBits - realShiftAmt)) ||
959 (realShiftAmt > dataBits &&
960 bits(DoubleBits, 2 * dataBits - realShiftAmt))) {
961 CFBits = 1;
962 }
963 //If some combination of the CF bits need to be set, set them.
964 if ((ext & (CFBit | ECFBit)) && CFBits)
965 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
966 //Figure out what the OF bit should be.
967 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
968 bits(result, dataBits - 1)))
969 ccFlagBits = ccFlagBits | OFBit;
970 //Use the regular mechanisms to calculate the other flags.
971 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
972 DestReg, psrc1, op2);
973 }
974 '''
975
976 class Srd(RegOp):
977 srdCode = '''
978 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
979 uint8_t dataBits = dataSize * 8;
980 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);
981 uint64_t result;
982 if (realShiftAmt == 0) {
983 result = psrc1;
984 } else if (realShiftAmt < dataBits) {
985 // Because what happens to the bits shift -in- on a right
986 // shift is not defined in the C/C++ standard, we have to
987 // mask them out to be sure they're zero.
988 uint64_t logicalMask = mask(dataBits - realShiftAmt);
989 result = ((psrc1 >> realShiftAmt) & logicalMask) |
990 (DoubleBits << (dataBits - realShiftAmt));
991 } else {
992 uint64_t logicalMask = mask(2 * dataBits - realShiftAmt);
993 result = ((DoubleBits >> (realShiftAmt - dataBits)) &
994 logicalMask) |
995 (psrc1 << (2 * dataBits - realShiftAmt));
996 }
997 %s
998 '''
999 code = srdCode % "DestReg = merge(DestReg, result, dataSize);"
1000 big_code = srdCode % "DestReg = result & mask(dataSize * 8);"
1001 flag_code = '''
1002 // If the shift amount is zero, no flags should be modified.
1003 if (shiftAmt) {
1004 //Zero out any flags we might modify. This way we only have to
1005 //worry about setting them.
1006 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
1007 int CFBits = 0;
1008 //If some combination of the CF bits need to be set, set them.
1009 if ((realShiftAmt == 0 &&
1010 bits(DoubleBits, dataBits - 1)) ||
1011 (realShiftAmt <= dataBits &&
1012 bits(SrcReg1, realShiftAmt - 1)) ||
1013 (realShiftAmt > dataBits &&
1014 bits(DoubleBits, realShiftAmt - dataBits - 1))) {
1015 CFBits = 1;
1016 }
1017 //If some combination of the CF bits need to be set, set them.
1018 if ((ext & (CFBit | ECFBit)) && CFBits)
1019 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
1020 //Figure out what the OF bit should be.
1021 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
1022 bits(result, dataBits - 1)))
1023 ccFlagBits = ccFlagBits | OFBit;
1024 //Use the regular mechanisms to calculate the other flags.
1025 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
1026 DestReg, psrc1, op2);
1027 }
1028 '''
1029
1030 class Mdb(WrRegOp):
1031 code = 'DoubleBits = psrc1 ^ op2;'
1032
1033 class Wrip(WrRegOp, CondRegOp):
1034 code = 'NRIP = psrc1 + sop2 + CSBase;'
1035 else_code = "NRIP = NRIP;"
1036
1037 class Wruflags(WrRegOp):
1038 code = 'ccFlagBits = psrc1 ^ op2'
1039
1040 class Wrflags(WrRegOp):
1041 code = '''
1042 MiscReg newFlags = psrc1 ^ op2;
1043 MiscReg userFlagMask = 0xDD5;
1044 // Get only the user flags
1045 ccFlagBits = newFlags & userFlagMask;
1046 // Get everything else
1047 nccFlagBits = newFlags & ~userFlagMask;
1048 '''
1049
1050 class Rdip(RdRegOp):
1051 code = 'DestReg = NRIP - CSBase;'
1052
1053 class Ruflags(RdRegOp):
1054 code = 'DestReg = ccFlagBits'
1055
1056 class Rflags(RdRegOp):
1057 code = 'DestReg = ccFlagBits | nccFlagBits'
1058
1059 class Ruflag(RegOp):
1060 code = '''
1061 int flag = bits(ccFlagBits, imm8);
1062 DestReg = merge(DestReg, flag, dataSize);
1063 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1064 (ccFlagBits & ~EZFBit);
1065 '''
1066 big_code = '''
1067 int flag = bits(ccFlagBits, imm8);
1068 DestReg = flag & mask(dataSize * 8);
1069 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1070 (ccFlagBits & ~EZFBit);
1071 '''
1072 def __init__(self, dest, imm, flags=None, \
1073 dataSize="env.dataSize"):
1074 super(Ruflag, self).__init__(dest, \
1075 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1076
1077 class Rflag(RegOp):
1078 code = '''
1079 MiscReg flagMask = 0x3F7FDD5;
1080 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
1081 int flag = bits(flags, imm8);
1082 DestReg = merge(DestReg, flag, dataSize);
1083 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1084 (ccFlagBits & ~EZFBit);
1085 '''
1086 big_code = '''
1087 MiscReg flagMask = 0x3F7FDD5;
1088 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
1089 int flag = bits(flags, imm8);
1090 DestReg = flag & mask(dataSize * 8);
1091 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1092 (ccFlagBits & ~EZFBit);
1093 '''
1094 def __init__(self, dest, imm, flags=None, \
1095 dataSize="env.dataSize"):
1096 super(Rflag, self).__init__(dest, \
1097 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1098
1099 class Sext(RegOp):
1100 code = '''
1101 IntReg val = psrc1;
1102 // Mask the bit position so that it wraps.
1103 int bitPos = op2 & (dataSize * 8 - 1);
1104 int sign_bit = bits(val, bitPos, bitPos);
1105 uint64_t maskVal = mask(bitPos+1);
1106 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1107 DestReg = merge(DestReg, val, dataSize);
1108 '''
1109 big_code = '''
1110 IntReg val = psrc1;
1111 // Mask the bit position so that it wraps.
1112 int bitPos = op2 & (dataSize * 8 - 1);
1113 int sign_bit = bits(val, bitPos, bitPos);
1114 uint64_t maskVal = mask(bitPos+1);
1115 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1116 DestReg = val & mask(dataSize * 8);
1117 '''
1118 flag_code = '''
1119 if (!sign_bit)
1120 ccFlagBits = ccFlagBits &
1121 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
1122 else
1123 ccFlagBits = ccFlagBits |
1124 (ext & (CFBit | ECFBit | ZFBit | EZFBit));
1125 '''
1126
1127 class Zext(RegOp):
1128 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
1129 big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);'
1130
1131 class Rddr(RegOp):
1132 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1133 super(Rddr, self).__init__(dest, \
1134 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1135 rdrCode = '''
1136 CR4 cr4 = CR4Op;
1137 DR7 dr7 = DR7Op;
1138 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
1139 fault = new InvalidOpcode();
1140 } else if (dr7.gd) {
1141 fault = new DebugException();
1142 } else {
1143 %s
1144 }
1145 '''
1146 code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);"
1147 big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);"
1148
1149 class Wrdr(RegOp):
1150 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1151 super(Wrdr, self).__init__(dest, \
1152 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1153 code = '''
1154 CR4 cr4 = CR4Op;
1155 DR7 dr7 = DR7Op;
1156 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) {
1157 fault = new InvalidOpcode();
1158 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) &&
1159 machInst.mode.mode == LongMode) {
1160 fault = new GeneralProtection(0);
1161 } else if (dr7.gd) {
1162 fault = new DebugException();
1163 } else {
1164 DebugDest = psrc1;
1165 }
1166 '''
1167
1168 class Rdcr(RegOp):
1169 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1170 super(Rdcr, self).__init__(dest, \
1171 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1172 rdcrCode = '''
1173 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
1174 fault = new InvalidOpcode();
1175 } else {
1176 %s
1177 }
1178 '''
1179 code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);"
1180 big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);"
1181
1182 class Wrcr(RegOp):
1183 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1184 super(Wrcr, self).__init__(dest, \
1185 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1186 code = '''
1187 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
1188 fault = new InvalidOpcode();
1189 } else {
1190 // There are *s in the line below so it doesn't confuse the
1191 // parser. They may be unnecessary.
1192 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize);
1193 MiscReg newVal = psrc1;
1194
1195 // Check for any modifications that would cause a fault.
1196 switch(dest) {
1197 case 0:
1198 {
1199 Efer efer = EferOp;
1200 CR0 cr0 = newVal;
1201 CR4 oldCr4 = CR4Op;
1202 if (bits(newVal, 63, 32) ||
1203 (!cr0.pe && cr0.pg) ||
1204 (!cr0.cd && cr0.nw) ||
1205 (cr0.pg && efer.lme && !oldCr4.pae))
1206 fault = new GeneralProtection(0);
1207 }
1208 break;
1209 case 2:
1210 break;
1211 case 3:
1212 break;
1213 case 4:
1214 {
1215 CR4 cr4 = newVal;
1216 // PAE can't be disabled in long mode.
1217 if (bits(newVal, 63, 11) ||
1218 (machInst.mode.mode == LongMode && !cr4.pae))
1219 fault = new GeneralProtection(0);
1220 }
1221 break;
1222 case 8:
1223 {
1224 if (bits(newVal, 63, 4))
1225 fault = new GeneralProtection(0);
1226 }
1227 default:
1228 panic("Unrecognized control register %d.\\n", dest);
1229 }
1230 ControlDest = newVal;
1231 }
1232 '''
1233
1234 # Microops for manipulating segmentation registers
1235 class SegOp(CondRegOp):
1236 abstract = True
1237 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1238 super(SegOp, self).__init__(dest, \
1239 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1240
1241 class Wrbase(SegOp):
1242 code = '''
1243 SegBaseDest = psrc1;
1244 '''
1245
1246 class Wrlimit(SegOp):
1247 code = '''
1248 SegLimitDest = psrc1;
1249 '''
1250
1251 class Wrsel(SegOp):
1252 code = '''
1253 SegSelDest = psrc1;
1254 '''
1255
1256 class WrAttr(SegOp):
1257 code = '''
1258 SegAttrDest = psrc1;
1259 '''
1260
1261 class Rdbase(SegOp):
1262 code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);'
1263 big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);'
1264
1265 class Rdlimit(SegOp):
1266 code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);'
1267 big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);'
1268
1269 class RdAttr(SegOp):
1270 code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);'
1271 big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);'
1272
1273 class Rdsel(SegOp):
1274 code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);'
1275 big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);'
1276
1277 class Rdval(RegOp):
1278 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1279 super(Rdval, self).__init__(dest, src1, \
1280 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1281 code = '''
1282 DestReg = MiscRegSrc1;
1283 '''
1284
1285 class Wrval(RegOp):
1286 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1287 super(Wrval, self).__init__(dest, src1, \
1288 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1289 code = '''
1290 MiscRegDest = SrcReg1;
1291 '''
1292
1293 class Chks(RegOp):
1294 def __init__(self, dest, src1, src2=0,
1295 flags=None, dataSize="env.dataSize"):
1296 super(Chks, self).__init__(dest,
1297 src1, src2, flags, dataSize)
1298 code = '''
1299 // The selector is in source 1 and can be at most 16 bits.
1300 SegSelector selector = DestReg;
1301 SegDescriptor desc = SrcReg1;
1302 HandyM5Reg m5reg = M5Reg;
1303
1304 switch (imm8)
1305 {
1306 case SegNoCheck:
1307 break;
1308 case SegCSCheck:
1309 // Make sure it's the right type
1310 if (desc.s == 0 || desc.type.codeOrData != 1) {
1311 fault = new GeneralProtection(0);
1312 } else if (m5reg.cpl != desc.dpl) {
1313 fault = new GeneralProtection(0);
1314 }
1315 break;
1316 case SegCallGateCheck:
1317 panic("CS checks for far calls/jumps through call gates"
1318 "not implemented.\\n");
1319 break;
1320 case SegSoftIntGateCheck:
1321 // Check permissions.
1322 if (desc.dpl < m5reg.cpl) {
1323 fault = new GeneralProtection(selector);
1324 break;
1325 }
1326 // Fall through on purpose
1327 case SegIntGateCheck:
1328 // Make sure the gate's the right type.
1329 if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||
1330 ((desc.type & 0x6) != 0x6)) {
1331 fault = new GeneralProtection(0);
1332 }
1333 break;
1334 case SegSSCheck:
1335 if (selector.si || selector.ti) {
1336 if (!desc.p) {
1337 fault = new StackFault(selector);
1338 }
1339 } else {
1340 if ((m5reg.submode != SixtyFourBitMode ||
1341 m5reg.cpl == 3) ||
1342 !(desc.s == 1 &&
1343 desc.type.codeOrData == 0 && desc.type.w) ||
1344 (desc.dpl != m5reg.cpl) ||
1345 (selector.rpl != m5reg.cpl)) {
1346 fault = new GeneralProtection(selector);
1347 }
1348 }
1349 break;
1350 case SegIretCheck:
1351 {
1352 if ((!selector.si && !selector.ti) ||
1353 (selector.rpl < m5reg.cpl) ||
1354 !(desc.s == 1 && desc.type.codeOrData == 1) ||
1355 (!desc.type.c && desc.dpl != selector.rpl) ||
1356 (desc.type.c && desc.dpl > selector.rpl)) {
1357 fault = new GeneralProtection(selector);
1358 } else if (!desc.p) {
1359 fault = new SegmentNotPresent(selector);
1360 }
1361 break;
1362 }
1363 case SegIntCSCheck:
1364 if (m5reg.mode == LongMode) {
1365 if (desc.l != 1 || desc.d != 0) {
1366 fault = new GeneralProtection(selector);
1367 }
1368 } else {
1369 panic("Interrupt CS checks not implemented "
1370 "in legacy mode.\\n");
1371 }
1372 break;
1373 case SegTRCheck:
1374 if (!selector.si || selector.ti) {
1375 fault = new GeneralProtection(selector);
1376 }
1377 break;
1378 case SegTSSCheck:
1379 if (!desc.p) {
1380 fault = new SegmentNotPresent(selector);
1381 } else if (!(desc.type == 0x9 ||
1382 (desc.type == 1 &&
1383 m5reg.mode != LongMode))) {
1384 fault = new GeneralProtection(selector);
1385 }
1386 break;
1387 case SegInGDTCheck:
1388 if (selector.ti) {
1389 fault = new GeneralProtection(selector);
1390 }
1391 break;
1392 case SegLDTCheck:
1393 if (!desc.p) {
1394 fault = new SegmentNotPresent(selector);
1395 } else if (desc.type != 0x2) {
1396 fault = new GeneralProtection(selector);
1397 }
1398 break;
1399 default:
1400 panic("Undefined segment check type.\\n");
1401 }
1402 '''
1403 flag_code = '''
1404 // Check for a NULL selector and set ZF,EZF appropriately.
1405 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit));
1406 if (!selector.si && !selector.ti)
1407 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit));
1408 '''
1409
1410 class Wrdh(RegOp):
1411 code = '''
1412 SegDescriptor desc = SrcReg1;
1413
1414 uint64_t target = bits(SrcReg2, 31, 0) << 32;
1415 switch(desc.type) {
1416 case LDT64:
1417 case AvailableTSS64:
1418 case BusyTSS64:
1419 replaceBits(target, 23, 0, desc.baseLow);
1420 replaceBits(target, 31, 24, desc.baseHigh);
1421 break;
1422 case CallGate64:
1423 case IntGate64:
1424 case TrapGate64:
1425 replaceBits(target, 15, 0, bits(desc, 15, 0));
1426 replaceBits(target, 31, 16, bits(desc, 63, 48));
1427 break;
1428 default:
1429 panic("Wrdh used with wrong descriptor type!\\n");
1430 }
1431 DestReg = target;
1432 '''
1433
1434 class Wrtsc(WrRegOp):
1435 code = '''
1436 TscOp = psrc1;
1437 '''
1438
1439 class Rdtsc(RdRegOp):
1440 code = '''
1441 DestReg = TscOp;
1442 '''
1443
1444 class Rdm5reg(RdRegOp):
1445 code = '''
1446 DestReg = M5Reg;
1447 '''
1448
1449 class Wrdl(RegOp):
1450 code = '''
1451 SegDescriptor desc = SrcReg1;
1452 SegSelector selector = SrcReg2;
1453 if (selector.si || selector.ti) {
1454 if (!desc.p)
1455 panic("Segment not present.\\n");
1456 SegAttr attr = 0;
1457 attr.dpl = desc.dpl;
1458 attr.unusable = 0;
1459 attr.defaultSize = desc.d;
1460 attr.longMode = desc.l;
1461 attr.avl = desc.avl;
1462 attr.granularity = desc.g;
1463 attr.present = desc.p;
1464 attr.system = desc.s;
1465 attr.type = desc.type;
1466 if (!desc.s) {
1467 // The expand down bit happens to be set for gates.
1468 if (desc.type.e) {
1469 panic("Gate descriptor encountered.\\n");
1470 }
1471 attr.readable = 1;
1472 attr.writable = 1;
1473 attr.expandDown = 0;
1474 } else {
1475 if (desc.type.codeOrData) {
1476 attr.expandDown = 0;
1477 attr.readable = desc.type.r;
1478 attr.writable = 0;
1479 } else {
1480 attr.expandDown = desc.type.e;
1481 attr.readable = 1;
1482 attr.writable = desc.type.w;
1483 }
1484 }
1485 Addr base = desc.baseLow | (desc.baseHigh << 24);
1486 Addr limit = desc.limitLow | (desc.limitHigh << 16);
1487 if (desc.g)
1488 limit = (limit << 12) | mask(12);
1489 SegBaseDest = base;
1490 SegLimitDest = limit;
1491 SegAttrDest = attr;
1492 } else {
1493 SegBaseDest = SegBaseDest;
1494 SegLimitDest = SegLimitDest;
1495 SegAttrDest = SegAttrDest;
1496 }
1497 '''
1498}};
| 368 if matcher.search(allCode):
369 microopClasses[name + 'i'] = cls
370 return cls
371
372
373 class RegOp(X86Microop):
374 __metaclass__ = RegOpMeta
375 # This class itself doesn't act as a microop
376 abstract = True
377
378 # Default template parameter values
379 big_code = ""
380 flag_code = ""
381 cond_check = "true"
382 else_code = ";"
383 cond_control_flag_init = ""
384
385 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
386 self.dest = dest
387 self.src1 = src1
388 self.op2 = op2
389 self.flags = flags
390 self.dataSize = dataSize
391 if flags is None:
392 self.ext = 0
393 else:
394 if not isinstance(flags, (list, tuple)):
395 raise Exception, "flags must be a list or tuple of flags"
396 self.ext = " | ".join(flags)
397 self.className += "Flags"
398
399 def getAllocator(self, microFlags):
400 if self.big_code != "":
401 className = self.className
402 if self.mnemonic == self.base_mnemonic + 'i':
403 className += "Imm"
404 allocString = '''
405 (%(dataSize)s >= 4) ?
406 (StaticInstPtr)(new %(class_name)sBig(machInst,
407 macrocodeBlock, %(flags)s, %(src1)s, %(op2)s,
408 %(dest)s, %(dataSize)s, %(ext)s)) :
409 (StaticInstPtr)(new %(class_name)s(machInst,
410 macrocodeBlock, %(flags)s, %(src1)s, %(op2)s,
411 %(dest)s, %(dataSize)s, %(ext)s))
412 '''
413 allocator = allocString % {
414 "class_name" : className,
415 "flags" : self.microFlagsText(microFlags),
416 "src1" : self.src1, "op2" : self.op2,
417 "dest" : self.dest,
418 "dataSize" : self.dataSize,
419 "ext" : self.ext}
420 return allocator
421 else:
422 className = self.className
423 if self.mnemonic == self.base_mnemonic + 'i':
424 className += "Imm"
425 allocator = '''new %(class_name)s(machInst, macrocodeBlock,
426 %(flags)s, %(src1)s, %(op2)s, %(dest)s,
427 %(dataSize)s, %(ext)s)''' % {
428 "class_name" : className,
429 "flags" : self.microFlagsText(microFlags),
430 "src1" : self.src1, "op2" : self.op2,
431 "dest" : self.dest,
432 "dataSize" : self.dataSize,
433 "ext" : self.ext}
434 return allocator
435
436 class LogicRegOp(RegOp):
437 abstract = True
438 flag_code = '''
439 //Don't have genFlags handle the OF or CF bits
440 uint64_t mask = CFBit | ECFBit | OFBit;
441 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, result, psrc1, op2);
442 //If a logic microop wants to set these, it wants to set them to 0.
443 ccFlagBits &= ~(CFBit & ext);
444 ccFlagBits &= ~(ECFBit & ext);
445 ccFlagBits &= ~(OFBit & ext);
446 '''
447
448 class FlagRegOp(RegOp):
449 abstract = True
450 flag_code = \
451 "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);"
452
453 class SubRegOp(RegOp):
454 abstract = True
455 flag_code = \
456 "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);"
457
458 class CondRegOp(RegOp):
459 abstract = True
460 cond_check = "checkCondition(ccFlagBits, ext)"
461 cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];"
462
463 class RdRegOp(RegOp):
464 abstract = True
465 def __init__(self, dest, src1=None, dataSize="env.dataSize"):
466 if not src1:
467 src1 = dest
468 super(RdRegOp, self).__init__(dest, src1, \
469 "InstRegIndex(NUM_INTREGS)", None, dataSize)
470
471 class WrRegOp(RegOp):
472 abstract = True
473 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
474 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
475 src1, src2, flags, dataSize)
476
477 class Add(FlagRegOp):
478 code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);'
479 big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);'
480
481 class Or(LogicRegOp):
482 code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);'
483 big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);'
484
485 class Adc(FlagRegOp):
486 code = '''
487 CCFlagBits flags = ccFlagBits;
488 DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize);
489 '''
490 big_code = '''
491 CCFlagBits flags = ccFlagBits;
492 DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
493 '''
494
495 class Sbb(SubRegOp):
496 code = '''
497 CCFlagBits flags = ccFlagBits;
498 DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize);
499 '''
500 big_code = '''
501 CCFlagBits flags = ccFlagBits;
502 DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
503 '''
504
505 class And(LogicRegOp):
506 code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)'
507 big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)'
508
509 class Sub(SubRegOp):
510 code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)'
511 big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)'
512
513 class Xor(LogicRegOp):
514 code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)'
515 big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)'
516
517 class Mul1s(WrRegOp):
518 code = '''
519 ProdLow = psrc1 * op2;
520 int halfSize = (dataSize * 8) / 2;
521 uint64_t shifter = (ULL(1) << halfSize);
522 uint64_t hiResult;
523 uint64_t psrc1_h = psrc1 / shifter;
524 uint64_t psrc1_l = psrc1 & mask(halfSize);
525 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
526 uint64_t psrc2_l = op2 & mask(halfSize);
527 hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
528 ((psrc1_l * psrc2_l) / shifter)) /shifter) +
529 psrc1_h * psrc2_h;
530 if (bits(psrc1, dataSize * 8 - 1))
531 hiResult -= op2;
532 if (bits(op2, dataSize * 8 - 1))
533 hiResult -= psrc1;
534 ProdHi = hiResult;
535 '''
536 flag_code = '''
537 if ((-ProdHi & mask(dataSize * 8)) !=
538 bits(ProdLow, dataSize * 8 - 1)) {
539 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
540 } else {
541 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
542 }
543 '''
544
545 class Mul1u(WrRegOp):
546 code = '''
547 ProdLow = psrc1 * op2;
548 int halfSize = (dataSize * 8) / 2;
549 uint64_t shifter = (ULL(1) << halfSize);
550 uint64_t psrc1_h = psrc1 / shifter;
551 uint64_t psrc1_l = psrc1 & mask(halfSize);
552 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
553 uint64_t psrc2_l = op2 & mask(halfSize);
554 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
555 ((psrc1_l * psrc2_l) / shifter)) / shifter) +
556 psrc1_h * psrc2_h;
557 '''
558 flag_code = '''
559 if (ProdHi) {
560 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
561 } else {
562 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
563 }
564 '''
565
566 class Mulel(RdRegOp):
567 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
568 big_code = 'DestReg = ProdLow & mask(dataSize * 8);'
569
570 class Muleh(RdRegOp):
571 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
572 if not src1:
573 src1 = dest
574 super(RdRegOp, self).__init__(dest, src1, \
575 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
576 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
577 big_code = 'DestReg = ProdHi & mask(dataSize * 8);'
578
579 # One or two bit divide
580 class Div1(WrRegOp):
581 code = '''
582 //These are temporaries so that modifying them later won't make
583 //the ISA parser think they're also sources.
584 uint64_t quotient = 0;
585 uint64_t remainder = psrc1;
586 //Similarly, this is a temporary so changing it doesn't make it
587 //a source.
588 uint64_t divisor = op2;
589 //This is a temporary just for consistency and clarity.
590 uint64_t dividend = remainder;
591 //Do the division.
592 if (divisor == 0) {
593 fault = new DivideByZero;
594 } else {
595 divide(dividend, divisor, quotient, remainder);
596 //Record the final results.
597 Remainder = remainder;
598 Quotient = quotient;
599 Divisor = divisor;
600 }
601 '''
602
603 # Step divide
604 class Div2(RegOp):
605 divCode = '''
606 uint64_t dividend = Remainder;
607 uint64_t divisor = Divisor;
608 uint64_t quotient = Quotient;
609 uint64_t remainder = dividend;
610 int remaining = op2;
611 //If we overshot, do nothing. This lets us unrool division loops a
612 //little.
613 if (divisor == 0) {
614 fault = new DivideByZero;
615 } else if (remaining) {
616 if (divisor & (ULL(1) << 63)) {
617 while (remaining && !(dividend & (ULL(1) << 63))) {
618 dividend = (dividend << 1) |
619 bits(SrcReg1, remaining - 1);
620 quotient <<= 1;
621 remaining--;
622 }
623 if (dividend & (ULL(1) << 63)) {
624 bool highBit = false;
625 if (dividend < divisor && remaining) {
626 highBit = true;
627 dividend = (dividend << 1) |
628 bits(SrcReg1, remaining - 1);
629 quotient <<= 1;
630 remaining--;
631 }
632 if (highBit || divisor <= dividend) {
633 quotient++;
634 dividend -= divisor;
635 }
636 }
637 remainder = dividend;
638 } else {
639 //Shift in bits from the low order portion of the dividend
640 while (dividend < divisor && remaining) {
641 dividend = (dividend << 1) |
642 bits(SrcReg1, remaining - 1);
643 quotient <<= 1;
644 remaining--;
645 }
646 remainder = dividend;
647 //Do the division.
648 divide(dividend, divisor, quotient, remainder);
649 }
650 }
651 //Keep track of how many bits there are still to pull in.
652 %s
653 //Record the final results
654 Remainder = remainder;
655 Quotient = quotient;
656 '''
657 code = divCode % "DestReg = merge(DestReg, remaining, dataSize);"
658 big_code = divCode % "DestReg = remaining & mask(dataSize * 8);"
659 flag_code = '''
660 if (remaining == 0)
661 ccFlagBits = ccFlagBits | (ext & EZFBit);
662 else
663 ccFlagBits = ccFlagBits & ~(ext & EZFBit);
664 '''
665
666 class Divq(RdRegOp):
667 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
668 big_code = 'DestReg = Quotient & mask(dataSize * 8);'
669
670 class Divr(RdRegOp):
671 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
672 big_code = 'DestReg = Remainder & mask(dataSize * 8);'
673
674 class Mov(CondRegOp):
675 code = 'DestReg = merge(SrcReg1, op2, dataSize)'
676 else_code = 'DestReg = DestReg;'
677
678 # Shift instructions
679
680 class Sll(RegOp):
681 code = '''
682 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
683 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
684 '''
685 big_code = '''
686 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
687 DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8);
688 '''
689 flag_code = '''
690 // If the shift amount is zero, no flags should be modified.
691 if (shiftAmt) {
692 //Zero out any flags we might modify. This way we only have to
693 //worry about setting them.
694 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
695 int CFBits = 0;
696 //Figure out if we -would- set the CF bits if requested.
697 if (shiftAmt <= dataSize * 8 &&
698 bits(SrcReg1, dataSize * 8 - shiftAmt)) {
699 CFBits = 1;
700 }
701 //If some combination of the CF bits need to be set, set them.
702 if ((ext & (CFBit | ECFBit)) && CFBits)
703 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
704 //Figure out what the OF bit should be.
705 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
706 ccFlagBits = ccFlagBits | OFBit;
707 //Use the regular mechanisms to calculate the other flags.
708 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
709 DestReg, psrc1, op2);
710 }
711 '''
712
713 class Srl(RegOp):
714 # Because what happens to the bits shift -in- on a right shift
715 # is not defined in the C/C++ standard, we have to mask them out
716 # to be sure they're zero.
717 code = '''
718 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
719 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
720 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
721 '''
722 big_code = '''
723 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
724 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
725 DestReg = (psrc1 >> shiftAmt) & logicalMask;
726 '''
727 flag_code = '''
728 // If the shift amount is zero, no flags should be modified.
729 if (shiftAmt) {
730 //Zero out any flags we might modify. This way we only have to
731 //worry about setting them.
732 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
733 //If some combination of the CF bits need to be set, set them.
734 if ((ext & (CFBit | ECFBit)) &&
735 shiftAmt <= dataSize * 8 &&
736 bits(SrcReg1, shiftAmt - 1)) {
737 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
738 }
739 //Figure out what the OF bit should be.
740 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
741 ccFlagBits = ccFlagBits | OFBit;
742 //Use the regular mechanisms to calculate the other flags.
743 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
744 DestReg, psrc1, op2);
745 }
746 '''
747
748 class Sra(RegOp):
749 # Because what happens to the bits shift -in- on a right shift
750 # is not defined in the C/C++ standard, we have to sign extend
751 # them manually to be sure.
752 code = '''
753 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
754 uint64_t arithMask = (shiftAmt == 0) ? 0 :
755 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
756 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
757 '''
758 big_code = '''
759 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
760 uint64_t arithMask = (shiftAmt == 0) ? 0 :
761 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
762 DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8);
763 '''
764 flag_code = '''
765 // If the shift amount is zero, no flags should be modified.
766 if (shiftAmt) {
767 //Zero out any flags we might modify. This way we only have to
768 //worry about setting them.
769 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
770 //If some combination of the CF bits need to be set, set them.
771 uint8_t effectiveShift =
772 (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8);
773 if ((ext & (CFBit | ECFBit)) &&
774 bits(SrcReg1, effectiveShift - 1)) {
775 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
776 }
777 //Use the regular mechanisms to calculate the other flags.
778 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
779 DestReg, psrc1, op2);
780 }
781 '''
782
783 class Ror(RegOp):
784 code = '''
785 uint8_t shiftAmt =
786 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
787 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
788 if (realShiftAmt) {
789 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt);
790 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt);
791 DestReg = merge(DestReg, top | bottom, dataSize);
792 } else
793 DestReg = merge(DestReg, DestReg, dataSize);
794 '''
795 flag_code = '''
796 // If the shift amount is zero, no flags should be modified.
797 if (shiftAmt) {
798 //Zero out any flags we might modify. This way we only have to
799 //worry about setting them.
800 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
801 //Find the most and second most significant bits of the result.
802 int msb = bits(DestReg, dataSize * 8 - 1);
803 int smsb = bits(DestReg, dataSize * 8 - 2);
804 //If some combination of the CF bits need to be set, set them.
805 if ((ext & (CFBit | ECFBit)) && msb)
806 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
807 //Figure out what the OF bit should be.
808 if ((ext & OFBit) && (msb ^ smsb))
809 ccFlagBits = ccFlagBits | OFBit;
810 //Use the regular mechanisms to calculate the other flags.
811 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
812 DestReg, psrc1, op2);
813 }
814 '''
815
816 class Rcr(RegOp):
817 code = '''
818 uint8_t shiftAmt =
819 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
820 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
821 if (realShiftAmt) {
822 CCFlagBits flags = ccFlagBits;
823 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt);
824 if (realShiftAmt > 1)
825 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1);
826 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt);
827 DestReg = merge(DestReg, top | bottom, dataSize);
828 } else
829 DestReg = merge(DestReg, DestReg, dataSize);
830 '''
831 flag_code = '''
832 // If the shift amount is zero, no flags should be modified.
833 if (shiftAmt) {
834 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
835 //Zero out any flags we might modify. This way we only have to
836 //worry about setting them.
837 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
838 //Figure out what the OF bit should be.
839 if ((ext & OFBit) && (origCFBit ^
840 bits(SrcReg1, dataSize * 8 - 1))) {
841 ccFlagBits = ccFlagBits | OFBit;
842 }
843 //If some combination of the CF bits need to be set, set them.
844 if ((ext & (CFBit | ECFBit)) &&
845 (realShiftAmt == 0) ? origCFBit :
846 bits(SrcReg1, realShiftAmt - 1)) {
847 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
848 }
849 //Use the regular mechanisms to calculate the other flags.
850 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
851 DestReg, psrc1, op2);
852 }
853 '''
854
855 class Rol(RegOp):
856 code = '''
857 uint8_t shiftAmt =
858 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
859 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
860 if (realShiftAmt) {
861 uint64_t top = psrc1 << realShiftAmt;
862 uint64_t bottom =
863 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt);
864 DestReg = merge(DestReg, top | bottom, dataSize);
865 } else
866 DestReg = merge(DestReg, DestReg, dataSize);
867 '''
868 flag_code = '''
869 // If the shift amount is zero, no flags should be modified.
870 if (shiftAmt) {
871 //Zero out any flags we might modify. This way we only have to
872 //worry about setting them.
873 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
874 //The CF bits, if set, would be set to the lsb of the result.
875 int lsb = DestReg & 0x1;
876 int msb = bits(DestReg, dataSize * 8 - 1);
877 //If some combination of the CF bits need to be set, set them.
878 if ((ext & (CFBit | ECFBit)) && lsb)
879 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
880 //Figure out what the OF bit should be.
881 if ((ext & OFBit) && (msb ^ lsb))
882 ccFlagBits = ccFlagBits | OFBit;
883 //Use the regular mechanisms to calculate the other flags.
884 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
885 DestReg, psrc1, op2);
886 }
887 '''
888
889 class Rcl(RegOp):
890 code = '''
891 uint8_t shiftAmt =
892 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
893 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
894 if (realShiftAmt) {
895 CCFlagBits flags = ccFlagBits;
896 uint64_t top = psrc1 << realShiftAmt;
897 uint64_t bottom = flags.cf << (realShiftAmt - 1);
898 if(shiftAmt > 1)
899 bottom |=
900 bits(psrc1, dataSize * 8 - 1,
901 dataSize * 8 - realShiftAmt + 1);
902 DestReg = merge(DestReg, top | bottom, dataSize);
903 } else
904 DestReg = merge(DestReg, DestReg, dataSize);
905 '''
906 flag_code = '''
907 // If the shift amount is zero, no flags should be modified.
908 if (shiftAmt) {
909 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
910 //Zero out any flags we might modify. This way we only have to
911 //worry about setting them.
912 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
913 int msb = bits(DestReg, dataSize * 8 - 1);
914 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt);
915 //If some combination of the CF bits need to be set, set them.
916 if ((ext & (CFBit | ECFBit)) &&
917 (realShiftAmt == 0) ? origCFBit : CFBits)
918 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
919 //Figure out what the OF bit should be.
920 if ((ext & OFBit) && (msb ^ CFBits))
921 ccFlagBits = ccFlagBits | OFBit;
922 //Use the regular mechanisms to calculate the other flags.
923 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
924 DestReg, psrc1, op2);
925 }
926 '''
927
928 class Sld(RegOp):
929 sldCode = '''
930 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
931 uint8_t dataBits = dataSize * 8;
932 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);
933 uint64_t result;
934 if (realShiftAmt == 0) {
935 result = psrc1;
936 } else if (realShiftAmt < dataBits) {
937 result = (psrc1 << realShiftAmt) |
938 (DoubleBits >> (dataBits - realShiftAmt));
939 } else {
940 result = (DoubleBits << (realShiftAmt - dataBits)) |
941 (psrc1 >> (2 * dataBits - realShiftAmt));
942 }
943 %s
944 '''
945 code = sldCode % "DestReg = merge(DestReg, result, dataSize);"
946 big_code = sldCode % "DestReg = result & mask(dataSize * 8);"
947 flag_code = '''
948 // If the shift amount is zero, no flags should be modified.
949 if (shiftAmt) {
950 //Zero out any flags we might modify. This way we only have to
951 //worry about setting them.
952 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
953 int CFBits = 0;
954 //Figure out if we -would- set the CF bits if requested.
955 if ((realShiftAmt == 0 &&
956 bits(DoubleBits, 0)) ||
957 (realShiftAmt <= dataBits &&
958 bits(SrcReg1, dataBits - realShiftAmt)) ||
959 (realShiftAmt > dataBits &&
960 bits(DoubleBits, 2 * dataBits - realShiftAmt))) {
961 CFBits = 1;
962 }
963 //If some combination of the CF bits need to be set, set them.
964 if ((ext & (CFBit | ECFBit)) && CFBits)
965 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
966 //Figure out what the OF bit should be.
967 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
968 bits(result, dataBits - 1)))
969 ccFlagBits = ccFlagBits | OFBit;
970 //Use the regular mechanisms to calculate the other flags.
971 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
972 DestReg, psrc1, op2);
973 }
974 '''
975
976 class Srd(RegOp):
977 srdCode = '''
978 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
979 uint8_t dataBits = dataSize * 8;
980 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);
981 uint64_t result;
982 if (realShiftAmt == 0) {
983 result = psrc1;
984 } else if (realShiftAmt < dataBits) {
985 // Because what happens to the bits shift -in- on a right
986 // shift is not defined in the C/C++ standard, we have to
987 // mask them out to be sure they're zero.
988 uint64_t logicalMask = mask(dataBits - realShiftAmt);
989 result = ((psrc1 >> realShiftAmt) & logicalMask) |
990 (DoubleBits << (dataBits - realShiftAmt));
991 } else {
992 uint64_t logicalMask = mask(2 * dataBits - realShiftAmt);
993 result = ((DoubleBits >> (realShiftAmt - dataBits)) &
994 logicalMask) |
995 (psrc1 << (2 * dataBits - realShiftAmt));
996 }
997 %s
998 '''
999 code = srdCode % "DestReg = merge(DestReg, result, dataSize);"
1000 big_code = srdCode % "DestReg = result & mask(dataSize * 8);"
1001 flag_code = '''
1002 // If the shift amount is zero, no flags should be modified.
1003 if (shiftAmt) {
1004 //Zero out any flags we might modify. This way we only have to
1005 //worry about setting them.
1006 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
1007 int CFBits = 0;
1008 //If some combination of the CF bits need to be set, set them.
1009 if ((realShiftAmt == 0 &&
1010 bits(DoubleBits, dataBits - 1)) ||
1011 (realShiftAmt <= dataBits &&
1012 bits(SrcReg1, realShiftAmt - 1)) ||
1013 (realShiftAmt > dataBits &&
1014 bits(DoubleBits, realShiftAmt - dataBits - 1))) {
1015 CFBits = 1;
1016 }
1017 //If some combination of the CF bits need to be set, set them.
1018 if ((ext & (CFBit | ECFBit)) && CFBits)
1019 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
1020 //Figure out what the OF bit should be.
1021 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
1022 bits(result, dataBits - 1)))
1023 ccFlagBits = ccFlagBits | OFBit;
1024 //Use the regular mechanisms to calculate the other flags.
1025 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
1026 DestReg, psrc1, op2);
1027 }
1028 '''
1029
1030 class Mdb(WrRegOp):
1031 code = 'DoubleBits = psrc1 ^ op2;'
1032
1033 class Wrip(WrRegOp, CondRegOp):
1034 code = 'NRIP = psrc1 + sop2 + CSBase;'
1035 else_code = "NRIP = NRIP;"
1036
1037 class Wruflags(WrRegOp):
1038 code = 'ccFlagBits = psrc1 ^ op2'
1039
1040 class Wrflags(WrRegOp):
1041 code = '''
1042 MiscReg newFlags = psrc1 ^ op2;
1043 MiscReg userFlagMask = 0xDD5;
1044 // Get only the user flags
1045 ccFlagBits = newFlags & userFlagMask;
1046 // Get everything else
1047 nccFlagBits = newFlags & ~userFlagMask;
1048 '''
1049
1050 class Rdip(RdRegOp):
1051 code = 'DestReg = NRIP - CSBase;'
1052
1053 class Ruflags(RdRegOp):
1054 code = 'DestReg = ccFlagBits'
1055
1056 class Rflags(RdRegOp):
1057 code = 'DestReg = ccFlagBits | nccFlagBits'
1058
1059 class Ruflag(RegOp):
1060 code = '''
1061 int flag = bits(ccFlagBits, imm8);
1062 DestReg = merge(DestReg, flag, dataSize);
1063 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1064 (ccFlagBits & ~EZFBit);
1065 '''
1066 big_code = '''
1067 int flag = bits(ccFlagBits, imm8);
1068 DestReg = flag & mask(dataSize * 8);
1069 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1070 (ccFlagBits & ~EZFBit);
1071 '''
1072 def __init__(self, dest, imm, flags=None, \
1073 dataSize="env.dataSize"):
1074 super(Ruflag, self).__init__(dest, \
1075 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1076
1077 class Rflag(RegOp):
1078 code = '''
1079 MiscReg flagMask = 0x3F7FDD5;
1080 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
1081 int flag = bits(flags, imm8);
1082 DestReg = merge(DestReg, flag, dataSize);
1083 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1084 (ccFlagBits & ~EZFBit);
1085 '''
1086 big_code = '''
1087 MiscReg flagMask = 0x3F7FDD5;
1088 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
1089 int flag = bits(flags, imm8);
1090 DestReg = flag & mask(dataSize * 8);
1091 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1092 (ccFlagBits & ~EZFBit);
1093 '''
1094 def __init__(self, dest, imm, flags=None, \
1095 dataSize="env.dataSize"):
1096 super(Rflag, self).__init__(dest, \
1097 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1098
1099 class Sext(RegOp):
1100 code = '''
1101 IntReg val = psrc1;
1102 // Mask the bit position so that it wraps.
1103 int bitPos = op2 & (dataSize * 8 - 1);
1104 int sign_bit = bits(val, bitPos, bitPos);
1105 uint64_t maskVal = mask(bitPos+1);
1106 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1107 DestReg = merge(DestReg, val, dataSize);
1108 '''
1109 big_code = '''
1110 IntReg val = psrc1;
1111 // Mask the bit position so that it wraps.
1112 int bitPos = op2 & (dataSize * 8 - 1);
1113 int sign_bit = bits(val, bitPos, bitPos);
1114 uint64_t maskVal = mask(bitPos+1);
1115 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1116 DestReg = val & mask(dataSize * 8);
1117 '''
1118 flag_code = '''
1119 if (!sign_bit)
1120 ccFlagBits = ccFlagBits &
1121 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
1122 else
1123 ccFlagBits = ccFlagBits |
1124 (ext & (CFBit | ECFBit | ZFBit | EZFBit));
1125 '''
1126
1127 class Zext(RegOp):
1128 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
1129 big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);'
1130
1131 class Rddr(RegOp):
1132 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1133 super(Rddr, self).__init__(dest, \
1134 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1135 rdrCode = '''
1136 CR4 cr4 = CR4Op;
1137 DR7 dr7 = DR7Op;
1138 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
1139 fault = new InvalidOpcode();
1140 } else if (dr7.gd) {
1141 fault = new DebugException();
1142 } else {
1143 %s
1144 }
1145 '''
1146 code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);"
1147 big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);"
1148
1149 class Wrdr(RegOp):
1150 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1151 super(Wrdr, self).__init__(dest, \
1152 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1153 code = '''
1154 CR4 cr4 = CR4Op;
1155 DR7 dr7 = DR7Op;
1156 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) {
1157 fault = new InvalidOpcode();
1158 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) &&
1159 machInst.mode.mode == LongMode) {
1160 fault = new GeneralProtection(0);
1161 } else if (dr7.gd) {
1162 fault = new DebugException();
1163 } else {
1164 DebugDest = psrc1;
1165 }
1166 '''
1167
1168 class Rdcr(RegOp):
1169 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1170 super(Rdcr, self).__init__(dest, \
1171 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1172 rdcrCode = '''
1173 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
1174 fault = new InvalidOpcode();
1175 } else {
1176 %s
1177 }
1178 '''
1179 code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);"
1180 big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);"
1181
1182 class Wrcr(RegOp):
1183 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1184 super(Wrcr, self).__init__(dest, \
1185 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1186 code = '''
1187 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
1188 fault = new InvalidOpcode();
1189 } else {
1190 // There are *s in the line below so it doesn't confuse the
1191 // parser. They may be unnecessary.
1192 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize);
1193 MiscReg newVal = psrc1;
1194
1195 // Check for any modifications that would cause a fault.
1196 switch(dest) {
1197 case 0:
1198 {
1199 Efer efer = EferOp;
1200 CR0 cr0 = newVal;
1201 CR4 oldCr4 = CR4Op;
1202 if (bits(newVal, 63, 32) ||
1203 (!cr0.pe && cr0.pg) ||
1204 (!cr0.cd && cr0.nw) ||
1205 (cr0.pg && efer.lme && !oldCr4.pae))
1206 fault = new GeneralProtection(0);
1207 }
1208 break;
1209 case 2:
1210 break;
1211 case 3:
1212 break;
1213 case 4:
1214 {
1215 CR4 cr4 = newVal;
1216 // PAE can't be disabled in long mode.
1217 if (bits(newVal, 63, 11) ||
1218 (machInst.mode.mode == LongMode && !cr4.pae))
1219 fault = new GeneralProtection(0);
1220 }
1221 break;
1222 case 8:
1223 {
1224 if (bits(newVal, 63, 4))
1225 fault = new GeneralProtection(0);
1226 }
1227 default:
1228 panic("Unrecognized control register %d.\\n", dest);
1229 }
1230 ControlDest = newVal;
1231 }
1232 '''
1233
1234 # Microops for manipulating segmentation registers
1235 class SegOp(CondRegOp):
1236 abstract = True
1237 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1238 super(SegOp, self).__init__(dest, \
1239 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1240
1241 class Wrbase(SegOp):
1242 code = '''
1243 SegBaseDest = psrc1;
1244 '''
1245
1246 class Wrlimit(SegOp):
1247 code = '''
1248 SegLimitDest = psrc1;
1249 '''
1250
1251 class Wrsel(SegOp):
1252 code = '''
1253 SegSelDest = psrc1;
1254 '''
1255
1256 class WrAttr(SegOp):
1257 code = '''
1258 SegAttrDest = psrc1;
1259 '''
1260
1261 class Rdbase(SegOp):
1262 code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);'
1263 big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);'
1264
1265 class Rdlimit(SegOp):
1266 code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);'
1267 big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);'
1268
1269 class RdAttr(SegOp):
1270 code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);'
1271 big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);'
1272
1273 class Rdsel(SegOp):
1274 code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);'
1275 big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);'
1276
1277 class Rdval(RegOp):
1278 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1279 super(Rdval, self).__init__(dest, src1, \
1280 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1281 code = '''
1282 DestReg = MiscRegSrc1;
1283 '''
1284
1285 class Wrval(RegOp):
1286 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1287 super(Wrval, self).__init__(dest, src1, \
1288 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1289 code = '''
1290 MiscRegDest = SrcReg1;
1291 '''
1292
1293 class Chks(RegOp):
1294 def __init__(self, dest, src1, src2=0,
1295 flags=None, dataSize="env.dataSize"):
1296 super(Chks, self).__init__(dest,
1297 src1, src2, flags, dataSize)
1298 code = '''
1299 // The selector is in source 1 and can be at most 16 bits.
1300 SegSelector selector = DestReg;
1301 SegDescriptor desc = SrcReg1;
1302 HandyM5Reg m5reg = M5Reg;
1303
1304 switch (imm8)
1305 {
1306 case SegNoCheck:
1307 break;
1308 case SegCSCheck:
1309 // Make sure it's the right type
1310 if (desc.s == 0 || desc.type.codeOrData != 1) {
1311 fault = new GeneralProtection(0);
1312 } else if (m5reg.cpl != desc.dpl) {
1313 fault = new GeneralProtection(0);
1314 }
1315 break;
1316 case SegCallGateCheck:
1317 panic("CS checks for far calls/jumps through call gates"
1318 "not implemented.\\n");
1319 break;
1320 case SegSoftIntGateCheck:
1321 // Check permissions.
1322 if (desc.dpl < m5reg.cpl) {
1323 fault = new GeneralProtection(selector);
1324 break;
1325 }
1326 // Fall through on purpose
1327 case SegIntGateCheck:
1328 // Make sure the gate's the right type.
1329 if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||
1330 ((desc.type & 0x6) != 0x6)) {
1331 fault = new GeneralProtection(0);
1332 }
1333 break;
1334 case SegSSCheck:
1335 if (selector.si || selector.ti) {
1336 if (!desc.p) {
1337 fault = new StackFault(selector);
1338 }
1339 } else {
1340 if ((m5reg.submode != SixtyFourBitMode ||
1341 m5reg.cpl == 3) ||
1342 !(desc.s == 1 &&
1343 desc.type.codeOrData == 0 && desc.type.w) ||
1344 (desc.dpl != m5reg.cpl) ||
1345 (selector.rpl != m5reg.cpl)) {
1346 fault = new GeneralProtection(selector);
1347 }
1348 }
1349 break;
1350 case SegIretCheck:
1351 {
1352 if ((!selector.si && !selector.ti) ||
1353 (selector.rpl < m5reg.cpl) ||
1354 !(desc.s == 1 && desc.type.codeOrData == 1) ||
1355 (!desc.type.c && desc.dpl != selector.rpl) ||
1356 (desc.type.c && desc.dpl > selector.rpl)) {
1357 fault = new GeneralProtection(selector);
1358 } else if (!desc.p) {
1359 fault = new SegmentNotPresent(selector);
1360 }
1361 break;
1362 }
1363 case SegIntCSCheck:
1364 if (m5reg.mode == LongMode) {
1365 if (desc.l != 1 || desc.d != 0) {
1366 fault = new GeneralProtection(selector);
1367 }
1368 } else {
1369 panic("Interrupt CS checks not implemented "
1370 "in legacy mode.\\n");
1371 }
1372 break;
1373 case SegTRCheck:
1374 if (!selector.si || selector.ti) {
1375 fault = new GeneralProtection(selector);
1376 }
1377 break;
1378 case SegTSSCheck:
1379 if (!desc.p) {
1380 fault = new SegmentNotPresent(selector);
1381 } else if (!(desc.type == 0x9 ||
1382 (desc.type == 1 &&
1383 m5reg.mode != LongMode))) {
1384 fault = new GeneralProtection(selector);
1385 }
1386 break;
1387 case SegInGDTCheck:
1388 if (selector.ti) {
1389 fault = new GeneralProtection(selector);
1390 }
1391 break;
1392 case SegLDTCheck:
1393 if (!desc.p) {
1394 fault = new SegmentNotPresent(selector);
1395 } else if (desc.type != 0x2) {
1396 fault = new GeneralProtection(selector);
1397 }
1398 break;
1399 default:
1400 panic("Undefined segment check type.\\n");
1401 }
1402 '''
1403 flag_code = '''
1404 // Check for a NULL selector and set ZF,EZF appropriately.
1405 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit));
1406 if (!selector.si && !selector.ti)
1407 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit));
1408 '''
1409
1410 class Wrdh(RegOp):
1411 code = '''
1412 SegDescriptor desc = SrcReg1;
1413
1414 uint64_t target = bits(SrcReg2, 31, 0) << 32;
1415 switch(desc.type) {
1416 case LDT64:
1417 case AvailableTSS64:
1418 case BusyTSS64:
1419 replaceBits(target, 23, 0, desc.baseLow);
1420 replaceBits(target, 31, 24, desc.baseHigh);
1421 break;
1422 case CallGate64:
1423 case IntGate64:
1424 case TrapGate64:
1425 replaceBits(target, 15, 0, bits(desc, 15, 0));
1426 replaceBits(target, 31, 16, bits(desc, 63, 48));
1427 break;
1428 default:
1429 panic("Wrdh used with wrong descriptor type!\\n");
1430 }
1431 DestReg = target;
1432 '''
1433
1434 class Wrtsc(WrRegOp):
1435 code = '''
1436 TscOp = psrc1;
1437 '''
1438
1439 class Rdtsc(RdRegOp):
1440 code = '''
1441 DestReg = TscOp;
1442 '''
1443
1444 class Rdm5reg(RdRegOp):
1445 code = '''
1446 DestReg = M5Reg;
1447 '''
1448
1449 class Wrdl(RegOp):
1450 code = '''
1451 SegDescriptor desc = SrcReg1;
1452 SegSelector selector = SrcReg2;
1453 if (selector.si || selector.ti) {
1454 if (!desc.p)
1455 panic("Segment not present.\\n");
1456 SegAttr attr = 0;
1457 attr.dpl = desc.dpl;
1458 attr.unusable = 0;
1459 attr.defaultSize = desc.d;
1460 attr.longMode = desc.l;
1461 attr.avl = desc.avl;
1462 attr.granularity = desc.g;
1463 attr.present = desc.p;
1464 attr.system = desc.s;
1465 attr.type = desc.type;
1466 if (!desc.s) {
1467 // The expand down bit happens to be set for gates.
1468 if (desc.type.e) {
1469 panic("Gate descriptor encountered.\\n");
1470 }
1471 attr.readable = 1;
1472 attr.writable = 1;
1473 attr.expandDown = 0;
1474 } else {
1475 if (desc.type.codeOrData) {
1476 attr.expandDown = 0;
1477 attr.readable = desc.type.r;
1478 attr.writable = 0;
1479 } else {
1480 attr.expandDown = desc.type.e;
1481 attr.readable = 1;
1482 attr.writable = desc.type.w;
1483 }
1484 }
1485 Addr base = desc.baseLow | (desc.baseHigh << 24);
1486 Addr limit = desc.limitLow | (desc.limitHigh << 16);
1487 if (desc.g)
1488 limit = (limit << 12) | mask(12);
1489 SegBaseDest = base;
1490 SegLimitDest = limit;
1491 SegAttrDest = attr;
1492 } else {
1493 SegBaseDest = SegBaseDest;
1494 SegLimitDest = SegLimitDest;
1495 SegAttrDest = SegAttrDest;
1496 }
1497 '''
1498}};
|