1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any
9// use which is NOT directed to receiving any direct monetary
10// compensation for, or commercial advantage from such use. Illustrative
11// examples of non-commercial use are academic research, personal study,
12// teaching, education and corporate research & development.
13// Illustrative examples of commercial use are distributing products for
14// commercial advantage and providing services using the software for
15// commercial advantage.
16//
17// If you wish to use this software or functionality therein that may be
18// covered by patents for commercial use, please contact:
19// Director of Intellectual Property Licensing
20// Office of Strategy and Technology
21// Hewlett-Packard Company
22// 1501 Page Mill Road
23// Palo Alto, California 94304
24//
25// Redistributions of source code must retain the above copyright notice,
26// this list of conditions and the following disclaimer. Redistributions
27// in binary form must reproduce the above copyright notice, this list of
28// conditions and the following disclaimer in the documentation and/or
29// other materials provided with the distribution. Neither the name of
30// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
31// contributors may be used to endorse or promote products derived from
32// this software without specific prior written permission. No right of
33// sublicense is granted herewith. Derivatives of the software and
34// output created using the software may be prepared, but only for
35// Non-Commercial Uses. Derivatives of the software may be shared with
36// others provided: (i) the others agree to abide by the list of
37// conditions herein which includes the Non-Commercial Use restrictions;
38// and (ii) such Derivatives of the software include the above copyright
39// notice to acknowledge the contribution from this software where
40// applicable, this list of conditions and the disclaimer below.
41//
42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
45// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
46// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
47// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
48// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
50// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53//
54// Authors: Gabe Black
55
56//////////////////////////////////////////////////////////////////////////
57//
58// RegOp Microop templates
59//
60//////////////////////////////////////////////////////////////////////////
61
62def template MicroRegOpExecute {{
63 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
64 Trace::InstRecord *traceData) const
65 {
66 Fault fault = NoFault;
67
68 DPRINTF(X86, "The data size is %d\n", dataSize);
69 %(op_decl)s;
70 %(op_rd)s;
71
72 if(%(cond_check)s)
73 {
74 %(code)s;
75 %(flag_code)s;
76 }
77 else
78 {
79 %(else_code)s;
80 }
81
82 //Write the resulting state to the execution context
83 if(fault == NoFault)
84 {
85 %(op_wb)s;
86 }
87 return fault;
88 }
89}};
90
91def template MicroRegOpImmExecute {{
92 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
93 Trace::InstRecord *traceData) const
94 {
95 Fault fault = NoFault;
96
97 %(op_decl)s;
98 %(op_rd)s;
99
100 if(%(cond_check)s)
101 {
102 %(code)s;
103 %(flag_code)s;
104 }
105 else
106 {
107 %(else_code)s;
108 }
109
110 //Write the resulting state to the execution context
111 if(fault == NoFault)
112 {
113 %(op_wb)s;
114 }
115 return fault;
116 }
117}};
118
119def template MicroRegOpDeclare {{
120 class %(class_name)s : public %(base_class)s
121 {
122 protected:
123 void buildMe();
124
125 public:
126 %(class_name)s(ExtMachInst _machInst,
127 const char * instMnem,
128 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
129 RegIndex _src1, RegIndex _src2, RegIndex _dest,
130 uint8_t _dataSize, uint16_t _ext);
131
132 %(class_name)s(ExtMachInst _machInst,
133 const char * instMnem,
134 RegIndex _src1, RegIndex _src2, RegIndex _dest,
135 uint8_t _dataSize, uint16_t _ext);
136
137 %(BasicExecDeclare)s
138 };
139}};
140
141def template MicroRegOpImmDeclare {{
142
143 class %(class_name)s : public %(base_class)s
144 {
145 protected:
146 void buildMe();
147
148 public:
149 %(class_name)s(ExtMachInst _machInst,
150 const char * instMnem,
151 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
152 RegIndex _src1, uint16_t _imm8, RegIndex _dest,
153 uint8_t _dataSize, uint16_t _ext);
154
155 %(class_name)s(ExtMachInst _machInst,
156 const char * instMnem,
157 RegIndex _src1, uint16_t _imm8, RegIndex _dest,
158 uint8_t _dataSize, uint16_t _ext);
159
160 %(BasicExecDeclare)s
161 };
162}};
163
164def template MicroRegOpConstructor {{
165
166 inline void %(class_name)s::buildMe()
167 {
168 %(constructor)s;
169 }
170
171 inline %(class_name)s::%(class_name)s(
172 ExtMachInst machInst, const char * instMnem,
173 RegIndex _src1, RegIndex _src2, RegIndex _dest,
174 uint8_t _dataSize, uint16_t _ext) :
175 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
176 false, false, false, false,
177 _src1, _src2, _dest, _dataSize, _ext,
178 %(op_class)s)
179 {
180 buildMe();
181 }
182
183 inline %(class_name)s::%(class_name)s(
184 ExtMachInst machInst, const char * instMnem,
185 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
186 RegIndex _src1, RegIndex _src2, RegIndex _dest,
187 uint8_t _dataSize, uint16_t _ext) :
188 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
189 isMicro, isDelayed, isFirst, isLast,
190 _src1, _src2, _dest, _dataSize, _ext,
191 %(op_class)s)
192 {
193 buildMe();
194 }
195}};
196
197def template MicroRegOpImmConstructor {{
198
199 inline void %(class_name)s::buildMe()
200 {
201 %(constructor)s;
202 }
203
204 inline %(class_name)s::%(class_name)s(
205 ExtMachInst machInst, const char * instMnem,
206 RegIndex _src1, uint16_t _imm8, RegIndex _dest,
207 uint8_t _dataSize, uint16_t _ext) :
208 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
209 false, false, false, false,
210 _src1, _imm8, _dest, _dataSize, _ext,
211 %(op_class)s)
212 {
213 buildMe();
214 }
215
216 inline %(class_name)s::%(class_name)s(
217 ExtMachInst machInst, const char * instMnem,
218 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
219 RegIndex _src1, uint16_t _imm8, RegIndex _dest,
220 uint8_t _dataSize, uint16_t _ext) :
221 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
222 isMicro, isDelayed, isFirst, isLast,
223 _src1, _imm8, _dest, _dataSize, _ext,
224 %(op_class)s)
225 {
226 buildMe();
227 }
228}};
229
230output header {{
231 void
232 divide(uint64_t dividend, uint64_t divisor,
233 uint64_t "ient, uint64_t &remainder);
234
235 enum SegmentSelectorCheck {
236 SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck,
237 SegSSCheck, SegIretCheck, SegIntCSCheck
238 };
| 1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any
9// use which is NOT directed to receiving any direct monetary
10// compensation for, or commercial advantage from such use. Illustrative
11// examples of non-commercial use are academic research, personal study,
12// teaching, education and corporate research & development.
13// Illustrative examples of commercial use are distributing products for
14// commercial advantage and providing services using the software for
15// commercial advantage.
16//
17// If you wish to use this software or functionality therein that may be
18// covered by patents for commercial use, please contact:
19// Director of Intellectual Property Licensing
20// Office of Strategy and Technology
21// Hewlett-Packard Company
22// 1501 Page Mill Road
23// Palo Alto, California 94304
24//
25// Redistributions of source code must retain the above copyright notice,
26// this list of conditions and the following disclaimer. Redistributions
27// in binary form must reproduce the above copyright notice, this list of
28// conditions and the following disclaimer in the documentation and/or
29// other materials provided with the distribution. Neither the name of
30// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
31// contributors may be used to endorse or promote products derived from
32// this software without specific prior written permission. No right of
33// sublicense is granted herewith. Derivatives of the software and
34// output created using the software may be prepared, but only for
35// Non-Commercial Uses. Derivatives of the software may be shared with
36// others provided: (i) the others agree to abide by the list of
37// conditions herein which includes the Non-Commercial Use restrictions;
38// and (ii) such Derivatives of the software include the above copyright
39// notice to acknowledge the contribution from this software where
40// applicable, this list of conditions and the disclaimer below.
41//
42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
45// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
46// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
47// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
48// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
50// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53//
54// Authors: Gabe Black
55
56//////////////////////////////////////////////////////////////////////////
57//
58// RegOp Microop templates
59//
60//////////////////////////////////////////////////////////////////////////
61
62def template MicroRegOpExecute {{
63 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
64 Trace::InstRecord *traceData) const
65 {
66 Fault fault = NoFault;
67
68 DPRINTF(X86, "The data size is %d\n", dataSize);
69 %(op_decl)s;
70 %(op_rd)s;
71
72 if(%(cond_check)s)
73 {
74 %(code)s;
75 %(flag_code)s;
76 }
77 else
78 {
79 %(else_code)s;
80 }
81
82 //Write the resulting state to the execution context
83 if(fault == NoFault)
84 {
85 %(op_wb)s;
86 }
87 return fault;
88 }
89}};
90
91def template MicroRegOpImmExecute {{
92 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
93 Trace::InstRecord *traceData) const
94 {
95 Fault fault = NoFault;
96
97 %(op_decl)s;
98 %(op_rd)s;
99
100 if(%(cond_check)s)
101 {
102 %(code)s;
103 %(flag_code)s;
104 }
105 else
106 {
107 %(else_code)s;
108 }
109
110 //Write the resulting state to the execution context
111 if(fault == NoFault)
112 {
113 %(op_wb)s;
114 }
115 return fault;
116 }
117}};
118
119def template MicroRegOpDeclare {{
120 class %(class_name)s : public %(base_class)s
121 {
122 protected:
123 void buildMe();
124
125 public:
126 %(class_name)s(ExtMachInst _machInst,
127 const char * instMnem,
128 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
129 RegIndex _src1, RegIndex _src2, RegIndex _dest,
130 uint8_t _dataSize, uint16_t _ext);
131
132 %(class_name)s(ExtMachInst _machInst,
133 const char * instMnem,
134 RegIndex _src1, RegIndex _src2, RegIndex _dest,
135 uint8_t _dataSize, uint16_t _ext);
136
137 %(BasicExecDeclare)s
138 };
139}};
140
141def template MicroRegOpImmDeclare {{
142
143 class %(class_name)s : public %(base_class)s
144 {
145 protected:
146 void buildMe();
147
148 public:
149 %(class_name)s(ExtMachInst _machInst,
150 const char * instMnem,
151 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
152 RegIndex _src1, uint16_t _imm8, RegIndex _dest,
153 uint8_t _dataSize, uint16_t _ext);
154
155 %(class_name)s(ExtMachInst _machInst,
156 const char * instMnem,
157 RegIndex _src1, uint16_t _imm8, RegIndex _dest,
158 uint8_t _dataSize, uint16_t _ext);
159
160 %(BasicExecDeclare)s
161 };
162}};
163
164def template MicroRegOpConstructor {{
165
166 inline void %(class_name)s::buildMe()
167 {
168 %(constructor)s;
169 }
170
171 inline %(class_name)s::%(class_name)s(
172 ExtMachInst machInst, const char * instMnem,
173 RegIndex _src1, RegIndex _src2, RegIndex _dest,
174 uint8_t _dataSize, uint16_t _ext) :
175 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
176 false, false, false, false,
177 _src1, _src2, _dest, _dataSize, _ext,
178 %(op_class)s)
179 {
180 buildMe();
181 }
182
183 inline %(class_name)s::%(class_name)s(
184 ExtMachInst machInst, const char * instMnem,
185 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
186 RegIndex _src1, RegIndex _src2, RegIndex _dest,
187 uint8_t _dataSize, uint16_t _ext) :
188 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
189 isMicro, isDelayed, isFirst, isLast,
190 _src1, _src2, _dest, _dataSize, _ext,
191 %(op_class)s)
192 {
193 buildMe();
194 }
195}};
196
197def template MicroRegOpImmConstructor {{
198
199 inline void %(class_name)s::buildMe()
200 {
201 %(constructor)s;
202 }
203
204 inline %(class_name)s::%(class_name)s(
205 ExtMachInst machInst, const char * instMnem,
206 RegIndex _src1, uint16_t _imm8, RegIndex _dest,
207 uint8_t _dataSize, uint16_t _ext) :
208 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
209 false, false, false, false,
210 _src1, _imm8, _dest, _dataSize, _ext,
211 %(op_class)s)
212 {
213 buildMe();
214 }
215
216 inline %(class_name)s::%(class_name)s(
217 ExtMachInst machInst, const char * instMnem,
218 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
219 RegIndex _src1, uint16_t _imm8, RegIndex _dest,
220 uint8_t _dataSize, uint16_t _ext) :
221 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
222 isMicro, isDelayed, isFirst, isLast,
223 _src1, _imm8, _dest, _dataSize, _ext,
224 %(op_class)s)
225 {
226 buildMe();
227 }
228}};
229
230output header {{
231 void
232 divide(uint64_t dividend, uint64_t divisor,
233 uint64_t "ient, uint64_t &remainder);
234
235 enum SegmentSelectorCheck {
236 SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck,
237 SegSSCheck, SegIretCheck, SegIntCSCheck
238 };
|
239}};
240
241output decoder {{
242 void
243 divide(uint64_t dividend, uint64_t divisor,
244 uint64_t "ient, uint64_t &remainder)
245 {
246 //Check for divide by zero.
247 if (divisor == 0)
248 panic("Divide by zero!\\n");
249 //If the divisor is bigger than the dividend, don't do anything.
250 if (divisor <= dividend) {
251 //Shift the divisor so it's msb lines up with the dividend.
252 int dividendMsb = findMsbSet(dividend);
253 int divisorMsb = findMsbSet(divisor);
254 int shift = dividendMsb - divisorMsb;
255 divisor <<= shift;
256 //Compute what we'll add to the quotient if the divisor isn't
257 //now larger than the dividend.
258 uint64_t quotientBit = 1;
259 quotientBit <<= shift;
260 //If we need to step back a bit (no pun intended) because the
261 //divisor got too to large, do that here. This is the "or two"
262 //part of one or two bit division.
263 if (divisor > dividend) {
264 quotientBit >>= 1;
265 divisor >>= 1;
266 }
267 //Decrement the remainder and increment the quotient.
268 quotient += quotientBit;
269 remainder -= divisor;
270 }
271 }
272}};
273
274let {{
275 # Make these empty strings so that concatenating onto
276 # them will always work.
277 header_output = ""
278 decoder_output = ""
279 exec_output = ""
280
281 immTemplates = (
282 MicroRegOpImmDeclare,
283 MicroRegOpImmConstructor,
284 MicroRegOpImmExecute)
285
286 regTemplates = (
287 MicroRegOpDeclare,
288 MicroRegOpConstructor,
289 MicroRegOpExecute)
290
291 class RegOpMeta(type):
292 def buildCppClasses(self, name, Name, suffix, \
293 code, flag_code, cond_check, else_code):
294
295 # Globals to stick the output in
296 global header_output
297 global decoder_output
298 global exec_output
299
300 # Stick all the code together so it can be searched at once
301 allCode = "|".join((code, flag_code, cond_check, else_code))
302
303 # If op2 is used anywhere, make register and immediate versions
304 # of this code.
305 matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?")
306 match = matcher.search(allCode)
307 if match:
308 typeQual = ""
309 if match.group("typeQual"):
310 typeQual = match.group("typeQual")
311 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
312 self.buildCppClasses(name, Name, suffix,
313 matcher.sub(src2_name, code),
314 matcher.sub(src2_name, flag_code),
315 matcher.sub(src2_name, cond_check),
316 matcher.sub(src2_name, else_code))
317 self.buildCppClasses(name + "i", Name, suffix + "Imm",
318 matcher.sub("imm8", code),
319 matcher.sub("imm8", flag_code),
320 matcher.sub("imm8", cond_check),
321 matcher.sub("imm8", else_code))
322 return
323
324 # If there's something optional to do with flags, generate
325 # a version without it and fix up this version to use it.
326 if flag_code != "" or cond_check != "true":
327 self.buildCppClasses(name, Name, suffix,
328 code, "", "true", else_code)
329 suffix = "Flags" + suffix
330
331 # If psrc1 or psrc2 is used, we need to actually insert code to
332 # compute it.
333 matcher = re.compile("(?<!\w)psrc1(?!\w)")
334 if matcher.search(allCode):
335 code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code
336 matcher = re.compile("(?<!\w)psrc2(?!\w)")
337 if matcher.search(allCode):
338 code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code
339 # Also make available versions which do sign extension
340 matcher = re.compile("(?<!\w)spsrc1(?!\w)")
341 if matcher.search(allCode):
342 code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code
343 matcher = re.compile("(?<!\w)spsrc2(?!\w)")
344 if matcher.search(allCode):
345 code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
346
347 base = "X86ISA::RegOp"
348
349 # If imm8 shows up in the code, use the immediate templates, if
350 # not, hopefully the register ones will be correct.
351 templates = regTemplates
352 matcher = re.compile("(?<!\w)imm8(?!\w)")
353 if matcher.search(allCode):
354 base += "Imm"
355 templates = immTemplates
356
357 # Get everything ready for the substitution
358 iop = InstObjParams(name, Name + suffix, base,
359 {"code" : code,
360 "flag_code" : flag_code,
361 "cond_check" : cond_check,
362 "else_code" : else_code})
363
364 # Generate the actual code (finally!)
365 header_output += templates[0].subst(iop)
366 decoder_output += templates[1].subst(iop)
367 exec_output += templates[2].subst(iop)
368
369
370 def __new__(mcls, Name, bases, dict):
371 abstract = False
372 name = Name.lower()
373 if "abstract" in dict:
374 abstract = dict['abstract']
375 del dict['abstract']
376
377 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
378 if not abstract:
379 cls.className = Name
380 cls.base_mnemonic = name
381 code = cls.code
382 flag_code = cls.flag_code
383 cond_check = cls.cond_check
384 else_code = cls.else_code
385
386 # Set up the C++ classes
387 mcls.buildCppClasses(cls, name, Name, "",
388 code, flag_code, cond_check, else_code)
389
390 # Hook into the microassembler dict
391 global microopClasses
392 microopClasses[name] = cls
393
394 allCode = "|".join((code, flag_code, cond_check, else_code))
395
396 # If op2 is used anywhere, make register and immediate versions
397 # of this code.
398 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
399 if matcher.search(allCode):
400 microopClasses[name + 'i'] = cls
401 return cls
402
403
404 class RegOp(X86Microop):
405 __metaclass__ = RegOpMeta
406 # This class itself doesn't act as a microop
407 abstract = True
408
409 # Default template parameter values
410 flag_code = ""
411 cond_check = "true"
412 else_code = ";"
413
414 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
415 self.dest = dest
416 self.src1 = src1
417 self.op2 = op2
418 self.flags = flags
419 self.dataSize = dataSize
420 if flags is None:
421 self.ext = 0
422 else:
423 if not isinstance(flags, (list, tuple)):
424 raise Exception, "flags must be a list or tuple of flags"
425 self.ext = " | ".join(flags)
426 self.className += "Flags"
427
428 def getAllocator(self, *microFlags):
429 className = self.className
430 if self.mnemonic == self.base_mnemonic + 'i':
431 className += "Imm"
432 allocator = '''new %(class_name)s(machInst, mnemonic
433 %(flags)s, %(src1)s, %(op2)s, %(dest)s,
434 %(dataSize)s, %(ext)s)''' % {
435 "class_name" : className,
436 "flags" : self.microFlagsText(microFlags),
437 "src1" : self.src1, "op2" : self.op2,
438 "dest" : self.dest,
439 "dataSize" : self.dataSize,
440 "ext" : self.ext}
441 return allocator
442
443 class LogicRegOp(RegOp):
444 abstract = True
445 flag_code = '''
446 //Don't have genFlags handle the OF or CF bits
447 uint64_t mask = CFBit | ECFBit | OFBit;
448 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
449 //If a logic microop wants to set these, it wants to set them to 0.
450 ccFlagBits &= ~(CFBit & ext);
451 ccFlagBits &= ~(ECFBit & ext);
452 ccFlagBits &= ~(OFBit & ext);
453 '''
454
455 class FlagRegOp(RegOp):
456 abstract = True
457 flag_code = \
458 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
459
460 class SubRegOp(RegOp):
461 abstract = True
462 flag_code = \
463 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
464
465 class CondRegOp(RegOp):
466 abstract = True
467 cond_check = "checkCondition(ccFlagBits, ext)"
468
469 class RdRegOp(RegOp):
470 abstract = True
471 def __init__(self, dest, src1=None, dataSize="env.dataSize"):
472 if not src1:
473 src1 = dest
474 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
475
476 class WrRegOp(RegOp):
477 abstract = True
478 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
479 super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
480
481 class Add(FlagRegOp):
482 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
483
484 class Or(LogicRegOp):
485 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
486
487 class Adc(FlagRegOp):
488 code = '''
489 CCFlagBits flags = ccFlagBits;
490 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
491 '''
492
493 class Sbb(SubRegOp):
494 code = '''
495 CCFlagBits flags = ccFlagBits;
496 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
497 '''
498
499 class And(LogicRegOp):
500 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
501
502 class Sub(SubRegOp):
503 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
504
505 class Xor(LogicRegOp):
506 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
507
508 # Neither of these is quite correct because it assumes that right shifting
509 # a signed or unsigned value does sign or zero extension respectively.
510 # The C standard says that what happens on a right shift with a 1 in the
511 # MSB position is undefined. On x86 and under likely most compilers the
512 # "right thing" happens, but this isn't a guarantee.
513 class Mul1s(WrRegOp):
514 code = '''
515 ProdLow = psrc1 * op2;
516 int halfSize = (dataSize * 8) / 2;
517 int64_t spsrc1_h = spsrc1 >> halfSize;
518 int64_t spsrc1_l = spsrc1 & mask(halfSize);
519 int64_t spsrc2_h = sop2 >> halfSize;
520 int64_t spsrc2_l = sop2 & mask(halfSize);
521 ProdHi = ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l +
522 ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) +
523 spsrc1_h * spsrc2_h;
524 '''
525
526 class Mul1u(WrRegOp):
527 code = '''
528 ProdLow = psrc1 * op2;
529 int halfSize = (dataSize * 8) / 2;
530 uint64_t psrc1_h = psrc1 >> halfSize;
531 uint64_t psrc1_l = psrc1 & mask(halfSize);
532 uint64_t psrc2_h = op2 >> halfSize;
533 uint64_t psrc2_l = op2 & mask(halfSize);
534 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
535 ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) +
536 psrc1_h * psrc2_h;
537 '''
538
539 class Mulel(RdRegOp):
540 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
541
542 class Muleh(RdRegOp):
543 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
544 if not src1:
545 src1 = dest
546 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize)
547 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
548 flag_code = '''
549 if (ProdHi)
550 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
551 else
552 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
553 '''
554
555 # One or two bit divide
556 class Div1(WrRegOp):
557 code = '''
558 //These are temporaries so that modifying them later won't make
559 //the ISA parser think they're also sources.
560 uint64_t quotient = 0;
561 uint64_t remainder = psrc1;
562 //Similarly, this is a temporary so changing it doesn't make it
563 //a source.
564 uint64_t divisor = op2;
565 //This is a temporary just for consistency and clarity.
566 uint64_t dividend = remainder;
567 //Do the division.
568 divide(dividend, divisor, quotient, remainder);
569 //Record the final results.
570 Remainder = remainder;
571 Quotient = quotient;
572 Divisor = divisor;
573 '''
574
575 # Step divide
576 class Div2(RegOp):
577 code = '''
578 uint64_t dividend = Remainder;
579 uint64_t divisor = Divisor;
580 uint64_t quotient = Quotient;
581 uint64_t remainder = dividend;
582 int remaining = op2;
583 //If we overshot, do nothing. This lets us unrool division loops a
584 //little.
585 if (remaining) {
586 //Shift in bits from the low order portion of the dividend
587 while(dividend < divisor && remaining) {
588 dividend = (dividend << 1) | bits(SrcReg1, remaining - 1);
589 quotient <<= 1;
590 remaining--;
591 }
592 remainder = dividend;
593 //Do the division.
594 divide(dividend, divisor, quotient, remainder);
595 }
596 //Keep track of how many bits there are still to pull in.
597 DestReg = merge(DestReg, remaining, dataSize);
598 //Record the final results
599 Remainder = remainder;
600 Quotient = quotient;
601 '''
602 flag_code = '''
603 if (DestReg == 0)
604 ccFlagBits = ccFlagBits | (ext & EZFBit);
605 else
606 ccFlagBits = ccFlagBits & ~(ext & EZFBit);
607 '''
608
609 class Divq(RdRegOp):
610 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
611
612 class Divr(RdRegOp):
613 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
614
615 class Mov(CondRegOp):
616 code = 'DestReg = merge(SrcReg1, op2, dataSize)'
617 else_code = 'DestReg=DestReg;'
618
619 # Shift instructions
620
621 class Sll(RegOp):
622 code = '''
623 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
624 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
625 '''
626 flag_code = '''
627 // If the shift amount is zero, no flags should be modified.
628 if (shiftAmt) {
629 //Zero out any flags we might modify. This way we only have to
630 //worry about setting them.
631 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
632 int CFBits = 0;
633 //Figure out if we -would- set the CF bits if requested.
634 if (bits(SrcReg1, dataSize * 8 - shiftAmt))
635 CFBits = 1;
636 //If some combination of the CF bits need to be set, set them.
637 if ((ext & (CFBit | ECFBit)) && CFBits)
638 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
639 //Figure out what the OF bit should be.
640 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
641 ccFlagBits = ccFlagBits | OFBit;
642 //Use the regular mechanisms to calculate the other flags.
643 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
644 DestReg, psrc1, op2);
645 }
646 '''
647
648 class Srl(RegOp):
649 code = '''
650 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
651 // Because what happens to the bits shift -in- on a right shift
652 // is not defined in the C/C++ standard, we have to mask them out
653 // to be sure they're zero.
654 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
655 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
656 '''
657 flag_code = '''
658 // If the shift amount is zero, no flags should be modified.
659 if (shiftAmt) {
660 //Zero out any flags we might modify. This way we only have to
661 //worry about setting them.
662 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
663 //If some combination of the CF bits need to be set, set them.
664 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
665 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
666 //Figure out what the OF bit should be.
667 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
668 ccFlagBits = ccFlagBits | OFBit;
669 //Use the regular mechanisms to calculate the other flags.
670 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
671 DestReg, psrc1, op2);
672 }
673 '''
674
675 class Sra(RegOp):
676 code = '''
677 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
678 // Because what happens to the bits shift -in- on a right shift
679 // is not defined in the C/C++ standard, we have to sign extend
680 // them manually to be sure.
681 uint64_t arithMask =
682 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
683 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
684 '''
685 flag_code = '''
686 // If the shift amount is zero, no flags should be modified.
687 if (shiftAmt) {
688 //Zero out any flags we might modify. This way we only have to
689 //worry about setting them.
690 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
691 //If some combination of the CF bits need to be set, set them.
692 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
693 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
694 //Use the regular mechanisms to calculate the other flags.
695 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
696 DestReg, psrc1, op2);
697 }
698 '''
699
700 class Ror(RegOp):
701 code = '''
702 uint8_t shiftAmt =
703 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
704 if(shiftAmt)
705 {
706 uint64_t top = psrc1 << (dataSize * 8 - shiftAmt);
707 uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
708 DestReg = merge(DestReg, top | bottom, dataSize);
709 }
710 else
711 DestReg = DestReg;
712 '''
713 flag_code = '''
714 // If the shift amount is zero, no flags should be modified.
715 if (shiftAmt) {
716 //Zero out any flags we might modify. This way we only have to
717 //worry about setting them.
718 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
719 //Find the most and second most significant bits of the result.
720 int msb = bits(DestReg, dataSize * 8 - 1);
721 int smsb = bits(DestReg, dataSize * 8 - 2);
722 //If some combination of the CF bits need to be set, set them.
723 if ((ext & (CFBit | ECFBit)) && msb)
724 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
725 //Figure out what the OF bit should be.
726 if ((ext & OFBit) && (msb ^ smsb))
727 ccFlagBits = ccFlagBits | OFBit;
728 //Use the regular mechanisms to calculate the other flags.
729 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
730 DestReg, psrc1, op2);
731 }
732 '''
733
734 class Rcr(RegOp):
735 code = '''
736 uint8_t shiftAmt =
737 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
738 if(shiftAmt)
739 {
740 CCFlagBits flags = ccFlagBits;
741 uint64_t top = flags.cf << (dataSize * 8 - shiftAmt);
742 if(shiftAmt > 1)
743 top |= psrc1 << (dataSize * 8 - shiftAmt - 1);
744 uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
745 DestReg = merge(DestReg, top | bottom, dataSize);
746 }
747 else
748 DestReg = DestReg;
749 '''
750 flag_code = '''
751 // If the shift amount is zero, no flags should be modified.
752 if (shiftAmt) {
753 //Zero out any flags we might modify. This way we only have to
754 //worry about setting them.
755 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
756 //Figure out what the OF bit should be.
757 if ((ext & OFBit) && ((ccFlagBits & CFBit) ^
758 bits(SrcReg1, dataSize * 8 - 1)))
759 ccFlagBits = ccFlagBits | OFBit;
760 //If some combination of the CF bits need to be set, set them.
761 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
762 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
763 //Use the regular mechanisms to calculate the other flags.
764 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
765 DestReg, psrc1, op2);
766 }
767 '''
768
769 class Rol(RegOp):
770 code = '''
771 uint8_t shiftAmt =
772 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
773 if(shiftAmt)
774 {
775 uint64_t top = psrc1 << shiftAmt;
776 uint64_t bottom =
777 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
778 DestReg = merge(DestReg, top | bottom, dataSize);
779 }
780 else
781 DestReg = DestReg;
782 '''
783 flag_code = '''
784 // If the shift amount is zero, no flags should be modified.
785 if (shiftAmt) {
786 //Zero out any flags we might modify. This way we only have to
787 //worry about setting them.
788 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
789 //The CF bits, if set, would be set to the lsb of the result.
790 int lsb = DestReg & 0x1;
791 int msb = bits(DestReg, dataSize * 8 - 1);
792 //If some combination of the CF bits need to be set, set them.
793 if ((ext & (CFBit | ECFBit)) && lsb)
794 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
795 //Figure out what the OF bit should be.
796 if ((ext & OFBit) && (msb ^ lsb))
797 ccFlagBits = ccFlagBits | OFBit;
798 //Use the regular mechanisms to calculate the other flags.
799 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
800 DestReg, psrc1, op2);
801 }
802 '''
803
804 class Rcl(RegOp):
805 code = '''
806 uint8_t shiftAmt =
807 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
808 if(shiftAmt)
809 {
810 CCFlagBits flags = ccFlagBits;
811 uint64_t top = psrc1 << shiftAmt;
812 uint64_t bottom = flags.cf << (shiftAmt - 1);
813 if(shiftAmt > 1)
814 bottom |=
815 bits(psrc1, dataSize * 8 - 1,
816 dataSize * 8 - shiftAmt + 1);
817 DestReg = merge(DestReg, top | bottom, dataSize);
818 }
819 else
820 DestReg = DestReg;
821 '''
822 flag_code = '''
823 // If the shift amount is zero, no flags should be modified.
824 if (shiftAmt) {
825 //Zero out any flags we might modify. This way we only have to
826 //worry about setting them.
827 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
828 int msb = bits(DestReg, dataSize * 8 - 1);
829 int CFBits = bits(SrcReg1, dataSize * 8 - shiftAmt);
830 //If some combination of the CF bits need to be set, set them.
831 if ((ext & (CFBit | ECFBit)) && CFBits)
832 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
833 //Figure out what the OF bit should be.
834 if ((ext & OFBit) && (msb ^ CFBits))
835 ccFlagBits = ccFlagBits | OFBit;
836 //Use the regular mechanisms to calculate the other flags.
837 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
838 DestReg, psrc1, op2);
839 }
840 '''
841
842 class Wrip(WrRegOp, CondRegOp):
843 code = 'RIP = psrc1 + sop2 + CSBase'
844 else_code="RIP = RIP;"
845
846 class Wruflags(WrRegOp):
847 code = 'ccFlagBits = psrc1 ^ op2'
848
849 class Wrflags(WrRegOp):
850 code = '''
851 MiscReg newFlags = psrc1 ^ op2;
852 MiscReg userFlagMask = 0xDD5;
853 // Get only the user flags
854 ccFlagBits = newFlags & userFlagMask;
855 // Get everything else
856 nccFlagBits = newFlags & ~userFlagMask;
857 '''
858
859 class Rdip(RdRegOp):
860 code = 'DestReg = RIP - CSBase'
861
862 class Ruflags(RdRegOp):
863 code = 'DestReg = ccFlagBits'
864
865 class Rflags(RdRegOp):
866 code = 'DestReg = ccFlagBits | nccFlagBits'
867
868 class Ruflag(RegOp):
869 code = '''
870 int flag = bits(ccFlagBits, imm8);
871 DestReg = merge(DestReg, flag, dataSize);
872 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
873 (ccFlagBits & ~EZFBit);
874 '''
875 def __init__(self, dest, imm, flags=None, \
876 dataSize="env.dataSize"):
877 super(Ruflag, self).__init__(dest, \
878 "NUM_INTREGS", imm, flags, dataSize)
879
880 class Rflag(RegOp):
881 code = '''
882 MiscReg flagMask = 0x3F7FDD5;
883 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
884 int flag = bits(flags, imm8);
885 DestReg = merge(DestReg, flag, dataSize);
886 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
887 (ccFlagBits & ~EZFBit);
888 '''
889 def __init__(self, dest, imm, flags=None, \
890 dataSize="env.dataSize"):
891 super(Rflag, self).__init__(dest, \
892 "NUM_INTREGS", imm, flags, dataSize)
893
894 class Sext(RegOp):
895 code = '''
896 IntReg val = psrc1;
897 // Mask the bit position so that it wraps.
898 int bitPos = op2 & (dataSize * 8 - 1);
899 int sign_bit = bits(val, bitPos, bitPos);
900 uint64_t maskVal = mask(bitPos+1);
901 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
902 DestReg = merge(DestReg, val, dataSize);
903 '''
904 flag_code = '''
905 if (!sign_bit)
906 ccFlagBits = ccFlagBits &
907 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
908 else
909 ccFlagBits = ccFlagBits |
910 (ext & (CFBit | ECFBit | ZFBit | EZFBit));
911 '''
912
913 class Zext(RegOp):
914 code = 'DestReg = bits(psrc1, op2, 0);'
915
916 class Rdcr(RegOp):
917 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
918 super(Rdcr, self).__init__(dest, \
919 src1, "NUM_INTREGS", flags, dataSize)
920 code = '''
921 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
922 fault = new InvalidOpcode();
923 } else {
924 DestReg = ControlSrc1;
925 }
926 '''
927
928 class Wrcr(RegOp):
929 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
930 super(Wrcr, self).__init__(dest, \
931 src1, "NUM_INTREGS", flags, dataSize)
932 code = '''
933 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
934 fault = new InvalidOpcode();
935 } else {
936 // There are *s in the line below so it doesn't confuse the
937 // parser. They may be unnecessary.
938 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize);
939 MiscReg newVal = psrc1;
940
941 // Check for any modifications that would cause a fault.
942 switch(dest) {
943 case 0:
944 {
945 Efer efer = EferOp;
946 CR0 cr0 = newVal;
947 CR4 oldCr4 = CR4Op;
948 if (bits(newVal, 63, 32) ||
949 (!cr0.pe && cr0.pg) ||
950 (!cr0.cd && cr0.nw) ||
951 (cr0.pg && efer.lme && !oldCr4.pae))
952 fault = new GeneralProtection(0);
953 }
954 break;
955 case 2:
956 break;
957 case 3:
958 break;
959 case 4:
960 {
961 CR4 cr4 = newVal;
962 // PAE can't be disabled in long mode.
963 if (bits(newVal, 63, 11) ||
964 (machInst.mode.mode == LongMode && !cr4.pae))
965 fault = new GeneralProtection(0);
966 }
967 break;
968 case 8:
969 {
970 if (bits(newVal, 63, 4))
971 fault = new GeneralProtection(0);
972 }
973 default:
974 panic("Unrecognized control register %d.\\n", dest);
975 }
976 ControlDest = newVal;
977 }
978 '''
979
980 # Microops for manipulating segmentation registers
981 class SegOp(CondRegOp):
982 abstract = True
983 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
984 super(SegOp, self).__init__(dest, \
985 src1, "NUM_INTREGS", flags, dataSize)
986
987 class Wrbase(SegOp):
988 code = '''
989 SegBaseDest = psrc1;
990 '''
991
992 class Wrlimit(SegOp):
993 code = '''
994 SegLimitDest = psrc1;
995 '''
996
997 class Wrsel(SegOp):
998 code = '''
999 SegSelDest = psrc1;
1000 '''
1001
1002 class Rdbase(SegOp):
1003 code = '''
1004 DestReg = SegBaseSrc1;
1005 '''
1006
1007 class Rdlimit(SegOp):
1008 code = '''
1009 DestReg = SegLimitSrc1;
1010 '''
1011
1012 class RdAttr(SegOp):
1013 code = '''
1014 DestReg = SegAttrSrc1;
1015 '''
1016
1017 class Rdsel(SegOp):
1018 code = '''
1019 DestReg = SegSelSrc1;
1020 '''
1021
1022 class Chks(RegOp):
1023 def __init__(self, dest, src1, src2=0,
1024 flags=None, dataSize="env.dataSize"):
1025 super(Chks, self).__init__(dest,
1026 src1, src2, flags, dataSize)
1027 code = '''
1028 // The selector is in source 1 and can be at most 16 bits.
1029 SegSelector selector = DestReg;
1030 SegDescriptor desc = SrcReg1;
1031 HandyM5Reg m5reg = M5Reg;
1032
1033 switch (imm8)
1034 {
1035 case SegNoCheck:
1036 break;
1037 case SegCSCheck:
1038 panic("CS checks for far calls/jumps not implemented.\\n");
1039 break;
1040 case SegCallGateCheck:
1041 panic("CS checks for far calls/jumps through call gates"
1042 "not implemented.\\n");
1043 break;
1044 case SegIntGateCheck:
1045 if (desc.dpl < m5reg.cpl) {
1046 return new GeneralProtection((uint16_t)selector);
1047 }
1048 break;
1049 case SegSSCheck:
1050 if (selector.si || selector.ti) {
1051 if (!desc.p) {
1052 //FIXME This needs to also push the selector.
1053 return new StackFault;
1054 }
1055 } else {
1056 if ((m5reg.submode != SixtyFourBitMode ||
1057 m5reg.cpl == 3) ||
1058 !(desc.s == 1 &&
1059 desc.type.codeOrData == 0 && desc.type.w) ||
1060 (desc.dpl != m5reg.cpl) ||
1061 (selector.rpl != m5reg.cpl)) {
1062 return new GeneralProtection(psrc1 & 0xFFFF);
1063 }
1064 }
1065 break;
1066 case SegIretCheck:
1067 {
1068 if ((!selector.si && !selector.ti) ||
1069 (selector.rpl < m5reg.cpl) ||
1070 !(desc.s == 1 && desc.type.codeOrData == 1) ||
1071 (!desc.type.c && desc.dpl != selector.rpl) ||
1072 (desc.type.c && desc.dpl > selector.rpl))
1073 return new GeneralProtection(psrc1 & 0xFFFF);
1074 if (!desc.p)
1075 return new SegmentNotPresent;
1076 break;
1077 }
1078 case SegIntCSCheck:
1079 if (m5reg.mode == LongMode) {
1080 if (desc.l != 1 || desc.d != 0) {
1081 return new GeneralProtection(selector);
1082 }
1083 } else {
1084 panic("Interrupt CS checks not implemented "
1085 "in legacy mode.\\n");
1086 }
1087 break;
1088 default:
1089 panic("Undefined segment check type.\\n");
1090 }
1091 '''
1092 flag_code = '''
1093 // Check for a NULL selector and set ZF,EZF appropriately.
1094 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit));
1095 if (!selector.si && !selector.ti)
1096 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit));
1097 '''
1098
1099 class Wrdh(RegOp):
1100 code = '''
| 248}};
249
250output decoder {{
251 void
252 divide(uint64_t dividend, uint64_t divisor,
253 uint64_t "ient, uint64_t &remainder)
254 {
255 //Check for divide by zero.
256 if (divisor == 0)
257 panic("Divide by zero!\\n");
258 //If the divisor is bigger than the dividend, don't do anything.
259 if (divisor <= dividend) {
260 //Shift the divisor so it's msb lines up with the dividend.
261 int dividendMsb = findMsbSet(dividend);
262 int divisorMsb = findMsbSet(divisor);
263 int shift = dividendMsb - divisorMsb;
264 divisor <<= shift;
265 //Compute what we'll add to the quotient if the divisor isn't
266 //now larger than the dividend.
267 uint64_t quotientBit = 1;
268 quotientBit <<= shift;
269 //If we need to step back a bit (no pun intended) because the
270 //divisor got too to large, do that here. This is the "or two"
271 //part of one or two bit division.
272 if (divisor > dividend) {
273 quotientBit >>= 1;
274 divisor >>= 1;
275 }
276 //Decrement the remainder and increment the quotient.
277 quotient += quotientBit;
278 remainder -= divisor;
279 }
280 }
281}};
282
283let {{
284 # Make these empty strings so that concatenating onto
285 # them will always work.
286 header_output = ""
287 decoder_output = ""
288 exec_output = ""
289
290 immTemplates = (
291 MicroRegOpImmDeclare,
292 MicroRegOpImmConstructor,
293 MicroRegOpImmExecute)
294
295 regTemplates = (
296 MicroRegOpDeclare,
297 MicroRegOpConstructor,
298 MicroRegOpExecute)
299
300 class RegOpMeta(type):
301 def buildCppClasses(self, name, Name, suffix, \
302 code, flag_code, cond_check, else_code):
303
304 # Globals to stick the output in
305 global header_output
306 global decoder_output
307 global exec_output
308
309 # Stick all the code together so it can be searched at once
310 allCode = "|".join((code, flag_code, cond_check, else_code))
311
312 # If op2 is used anywhere, make register and immediate versions
313 # of this code.
314 matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?")
315 match = matcher.search(allCode)
316 if match:
317 typeQual = ""
318 if match.group("typeQual"):
319 typeQual = match.group("typeQual")
320 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
321 self.buildCppClasses(name, Name, suffix,
322 matcher.sub(src2_name, code),
323 matcher.sub(src2_name, flag_code),
324 matcher.sub(src2_name, cond_check),
325 matcher.sub(src2_name, else_code))
326 self.buildCppClasses(name + "i", Name, suffix + "Imm",
327 matcher.sub("imm8", code),
328 matcher.sub("imm8", flag_code),
329 matcher.sub("imm8", cond_check),
330 matcher.sub("imm8", else_code))
331 return
332
333 # If there's something optional to do with flags, generate
334 # a version without it and fix up this version to use it.
335 if flag_code != "" or cond_check != "true":
336 self.buildCppClasses(name, Name, suffix,
337 code, "", "true", else_code)
338 suffix = "Flags" + suffix
339
340 # If psrc1 or psrc2 is used, we need to actually insert code to
341 # compute it.
342 matcher = re.compile("(?<!\w)psrc1(?!\w)")
343 if matcher.search(allCode):
344 code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code
345 matcher = re.compile("(?<!\w)psrc2(?!\w)")
346 if matcher.search(allCode):
347 code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code
348 # Also make available versions which do sign extension
349 matcher = re.compile("(?<!\w)spsrc1(?!\w)")
350 if matcher.search(allCode):
351 code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code
352 matcher = re.compile("(?<!\w)spsrc2(?!\w)")
353 if matcher.search(allCode):
354 code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
355
356 base = "X86ISA::RegOp"
357
358 # If imm8 shows up in the code, use the immediate templates, if
359 # not, hopefully the register ones will be correct.
360 templates = regTemplates
361 matcher = re.compile("(?<!\w)imm8(?!\w)")
362 if matcher.search(allCode):
363 base += "Imm"
364 templates = immTemplates
365
366 # Get everything ready for the substitution
367 iop = InstObjParams(name, Name + suffix, base,
368 {"code" : code,
369 "flag_code" : flag_code,
370 "cond_check" : cond_check,
371 "else_code" : else_code})
372
373 # Generate the actual code (finally!)
374 header_output += templates[0].subst(iop)
375 decoder_output += templates[1].subst(iop)
376 exec_output += templates[2].subst(iop)
377
378
379 def __new__(mcls, Name, bases, dict):
380 abstract = False
381 name = Name.lower()
382 if "abstract" in dict:
383 abstract = dict['abstract']
384 del dict['abstract']
385
386 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
387 if not abstract:
388 cls.className = Name
389 cls.base_mnemonic = name
390 code = cls.code
391 flag_code = cls.flag_code
392 cond_check = cls.cond_check
393 else_code = cls.else_code
394
395 # Set up the C++ classes
396 mcls.buildCppClasses(cls, name, Name, "",
397 code, flag_code, cond_check, else_code)
398
399 # Hook into the microassembler dict
400 global microopClasses
401 microopClasses[name] = cls
402
403 allCode = "|".join((code, flag_code, cond_check, else_code))
404
405 # If op2 is used anywhere, make register and immediate versions
406 # of this code.
407 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
408 if matcher.search(allCode):
409 microopClasses[name + 'i'] = cls
410 return cls
411
412
413 class RegOp(X86Microop):
414 __metaclass__ = RegOpMeta
415 # This class itself doesn't act as a microop
416 abstract = True
417
418 # Default template parameter values
419 flag_code = ""
420 cond_check = "true"
421 else_code = ";"
422
423 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
424 self.dest = dest
425 self.src1 = src1
426 self.op2 = op2
427 self.flags = flags
428 self.dataSize = dataSize
429 if flags is None:
430 self.ext = 0
431 else:
432 if not isinstance(flags, (list, tuple)):
433 raise Exception, "flags must be a list or tuple of flags"
434 self.ext = " | ".join(flags)
435 self.className += "Flags"
436
437 def getAllocator(self, *microFlags):
438 className = self.className
439 if self.mnemonic == self.base_mnemonic + 'i':
440 className += "Imm"
441 allocator = '''new %(class_name)s(machInst, mnemonic
442 %(flags)s, %(src1)s, %(op2)s, %(dest)s,
443 %(dataSize)s, %(ext)s)''' % {
444 "class_name" : className,
445 "flags" : self.microFlagsText(microFlags),
446 "src1" : self.src1, "op2" : self.op2,
447 "dest" : self.dest,
448 "dataSize" : self.dataSize,
449 "ext" : self.ext}
450 return allocator
451
452 class LogicRegOp(RegOp):
453 abstract = True
454 flag_code = '''
455 //Don't have genFlags handle the OF or CF bits
456 uint64_t mask = CFBit | ECFBit | OFBit;
457 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
458 //If a logic microop wants to set these, it wants to set them to 0.
459 ccFlagBits &= ~(CFBit & ext);
460 ccFlagBits &= ~(ECFBit & ext);
461 ccFlagBits &= ~(OFBit & ext);
462 '''
463
464 class FlagRegOp(RegOp):
465 abstract = True
466 flag_code = \
467 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
468
469 class SubRegOp(RegOp):
470 abstract = True
471 flag_code = \
472 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
473
474 class CondRegOp(RegOp):
475 abstract = True
476 cond_check = "checkCondition(ccFlagBits, ext)"
477
478 class RdRegOp(RegOp):
479 abstract = True
480 def __init__(self, dest, src1=None, dataSize="env.dataSize"):
481 if not src1:
482 src1 = dest
483 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
484
485 class WrRegOp(RegOp):
486 abstract = True
487 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
488 super(WrRegOp, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
489
490 class Add(FlagRegOp):
491 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
492
493 class Or(LogicRegOp):
494 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
495
496 class Adc(FlagRegOp):
497 code = '''
498 CCFlagBits flags = ccFlagBits;
499 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
500 '''
501
502 class Sbb(SubRegOp):
503 code = '''
504 CCFlagBits flags = ccFlagBits;
505 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
506 '''
507
508 class And(LogicRegOp):
509 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
510
511 class Sub(SubRegOp):
512 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
513
514 class Xor(LogicRegOp):
515 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
516
517 # Neither of these is quite correct because it assumes that right shifting
518 # a signed or unsigned value does sign or zero extension respectively.
519 # The C standard says that what happens on a right shift with a 1 in the
520 # MSB position is undefined. On x86 and under likely most compilers the
521 # "right thing" happens, but this isn't a guarantee.
522 class Mul1s(WrRegOp):
523 code = '''
524 ProdLow = psrc1 * op2;
525 int halfSize = (dataSize * 8) / 2;
526 int64_t spsrc1_h = spsrc1 >> halfSize;
527 int64_t spsrc1_l = spsrc1 & mask(halfSize);
528 int64_t spsrc2_h = sop2 >> halfSize;
529 int64_t spsrc2_l = sop2 & mask(halfSize);
530 ProdHi = ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l +
531 ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) +
532 spsrc1_h * spsrc2_h;
533 '''
534
535 class Mul1u(WrRegOp):
536 code = '''
537 ProdLow = psrc1 * op2;
538 int halfSize = (dataSize * 8) / 2;
539 uint64_t psrc1_h = psrc1 >> halfSize;
540 uint64_t psrc1_l = psrc1 & mask(halfSize);
541 uint64_t psrc2_h = op2 >> halfSize;
542 uint64_t psrc2_l = op2 & mask(halfSize);
543 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
544 ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) +
545 psrc1_h * psrc2_h;
546 '''
547
548 class Mulel(RdRegOp):
549 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
550
551 class Muleh(RdRegOp):
552 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
553 if not src1:
554 src1 = dest
555 super(RdRegOp, self).__init__(dest, src1, "NUM_INTREGS", flags, dataSize)
556 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
557 flag_code = '''
558 if (ProdHi)
559 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
560 else
561 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
562 '''
563
564 # One or two bit divide
565 class Div1(WrRegOp):
566 code = '''
567 //These are temporaries so that modifying them later won't make
568 //the ISA parser think they're also sources.
569 uint64_t quotient = 0;
570 uint64_t remainder = psrc1;
571 //Similarly, this is a temporary so changing it doesn't make it
572 //a source.
573 uint64_t divisor = op2;
574 //This is a temporary just for consistency and clarity.
575 uint64_t dividend = remainder;
576 //Do the division.
577 divide(dividend, divisor, quotient, remainder);
578 //Record the final results.
579 Remainder = remainder;
580 Quotient = quotient;
581 Divisor = divisor;
582 '''
583
584 # Step divide
585 class Div2(RegOp):
586 code = '''
587 uint64_t dividend = Remainder;
588 uint64_t divisor = Divisor;
589 uint64_t quotient = Quotient;
590 uint64_t remainder = dividend;
591 int remaining = op2;
592 //If we overshot, do nothing. This lets us unrool division loops a
593 //little.
594 if (remaining) {
595 //Shift in bits from the low order portion of the dividend
596 while(dividend < divisor && remaining) {
597 dividend = (dividend << 1) | bits(SrcReg1, remaining - 1);
598 quotient <<= 1;
599 remaining--;
600 }
601 remainder = dividend;
602 //Do the division.
603 divide(dividend, divisor, quotient, remainder);
604 }
605 //Keep track of how many bits there are still to pull in.
606 DestReg = merge(DestReg, remaining, dataSize);
607 //Record the final results
608 Remainder = remainder;
609 Quotient = quotient;
610 '''
611 flag_code = '''
612 if (DestReg == 0)
613 ccFlagBits = ccFlagBits | (ext & EZFBit);
614 else
615 ccFlagBits = ccFlagBits & ~(ext & EZFBit);
616 '''
617
618 class Divq(RdRegOp):
619 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
620
621 class Divr(RdRegOp):
622 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
623
624 class Mov(CondRegOp):
625 code = 'DestReg = merge(SrcReg1, op2, dataSize)'
626 else_code = 'DestReg=DestReg;'
627
628 # Shift instructions
629
630 class Sll(RegOp):
631 code = '''
632 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
633 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
634 '''
635 flag_code = '''
636 // If the shift amount is zero, no flags should be modified.
637 if (shiftAmt) {
638 //Zero out any flags we might modify. This way we only have to
639 //worry about setting them.
640 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
641 int CFBits = 0;
642 //Figure out if we -would- set the CF bits if requested.
643 if (bits(SrcReg1, dataSize * 8 - shiftAmt))
644 CFBits = 1;
645 //If some combination of the CF bits need to be set, set them.
646 if ((ext & (CFBit | ECFBit)) && CFBits)
647 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
648 //Figure out what the OF bit should be.
649 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
650 ccFlagBits = ccFlagBits | OFBit;
651 //Use the regular mechanisms to calculate the other flags.
652 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
653 DestReg, psrc1, op2);
654 }
655 '''
656
657 class Srl(RegOp):
658 code = '''
659 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
660 // Because what happens to the bits shift -in- on a right shift
661 // is not defined in the C/C++ standard, we have to mask them out
662 // to be sure they're zero.
663 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
664 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
665 '''
666 flag_code = '''
667 // If the shift amount is zero, no flags should be modified.
668 if (shiftAmt) {
669 //Zero out any flags we might modify. This way we only have to
670 //worry about setting them.
671 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
672 //If some combination of the CF bits need to be set, set them.
673 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
674 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
675 //Figure out what the OF bit should be.
676 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
677 ccFlagBits = ccFlagBits | OFBit;
678 //Use the regular mechanisms to calculate the other flags.
679 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
680 DestReg, psrc1, op2);
681 }
682 '''
683
684 class Sra(RegOp):
685 code = '''
686 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
687 // Because what happens to the bits shift -in- on a right shift
688 // is not defined in the C/C++ standard, we have to sign extend
689 // them manually to be sure.
690 uint64_t arithMask =
691 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
692 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
693 '''
694 flag_code = '''
695 // If the shift amount is zero, no flags should be modified.
696 if (shiftAmt) {
697 //Zero out any flags we might modify. This way we only have to
698 //worry about setting them.
699 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
700 //If some combination of the CF bits need to be set, set them.
701 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
702 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
703 //Use the regular mechanisms to calculate the other flags.
704 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
705 DestReg, psrc1, op2);
706 }
707 '''
708
709 class Ror(RegOp):
710 code = '''
711 uint8_t shiftAmt =
712 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
713 if(shiftAmt)
714 {
715 uint64_t top = psrc1 << (dataSize * 8 - shiftAmt);
716 uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
717 DestReg = merge(DestReg, top | bottom, dataSize);
718 }
719 else
720 DestReg = DestReg;
721 '''
722 flag_code = '''
723 // If the shift amount is zero, no flags should be modified.
724 if (shiftAmt) {
725 //Zero out any flags we might modify. This way we only have to
726 //worry about setting them.
727 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
728 //Find the most and second most significant bits of the result.
729 int msb = bits(DestReg, dataSize * 8 - 1);
730 int smsb = bits(DestReg, dataSize * 8 - 2);
731 //If some combination of the CF bits need to be set, set them.
732 if ((ext & (CFBit | ECFBit)) && msb)
733 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
734 //Figure out what the OF bit should be.
735 if ((ext & OFBit) && (msb ^ smsb))
736 ccFlagBits = ccFlagBits | OFBit;
737 //Use the regular mechanisms to calculate the other flags.
738 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
739 DestReg, psrc1, op2);
740 }
741 '''
742
743 class Rcr(RegOp):
744 code = '''
745 uint8_t shiftAmt =
746 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
747 if(shiftAmt)
748 {
749 CCFlagBits flags = ccFlagBits;
750 uint64_t top = flags.cf << (dataSize * 8 - shiftAmt);
751 if(shiftAmt > 1)
752 top |= psrc1 << (dataSize * 8 - shiftAmt - 1);
753 uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
754 DestReg = merge(DestReg, top | bottom, dataSize);
755 }
756 else
757 DestReg = DestReg;
758 '''
759 flag_code = '''
760 // If the shift amount is zero, no flags should be modified.
761 if (shiftAmt) {
762 //Zero out any flags we might modify. This way we only have to
763 //worry about setting them.
764 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
765 //Figure out what the OF bit should be.
766 if ((ext & OFBit) && ((ccFlagBits & CFBit) ^
767 bits(SrcReg1, dataSize * 8 - 1)))
768 ccFlagBits = ccFlagBits | OFBit;
769 //If some combination of the CF bits need to be set, set them.
770 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
771 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
772 //Use the regular mechanisms to calculate the other flags.
773 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
774 DestReg, psrc1, op2);
775 }
776 '''
777
778 class Rol(RegOp):
779 code = '''
780 uint8_t shiftAmt =
781 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
782 if(shiftAmt)
783 {
784 uint64_t top = psrc1 << shiftAmt;
785 uint64_t bottom =
786 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
787 DestReg = merge(DestReg, top | bottom, dataSize);
788 }
789 else
790 DestReg = DestReg;
791 '''
792 flag_code = '''
793 // If the shift amount is zero, no flags should be modified.
794 if (shiftAmt) {
795 //Zero out any flags we might modify. This way we only have to
796 //worry about setting them.
797 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
798 //The CF bits, if set, would be set to the lsb of the result.
799 int lsb = DestReg & 0x1;
800 int msb = bits(DestReg, dataSize * 8 - 1);
801 //If some combination of the CF bits need to be set, set them.
802 if ((ext & (CFBit | ECFBit)) && lsb)
803 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
804 //Figure out what the OF bit should be.
805 if ((ext & OFBit) && (msb ^ lsb))
806 ccFlagBits = ccFlagBits | OFBit;
807 //Use the regular mechanisms to calculate the other flags.
808 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
809 DestReg, psrc1, op2);
810 }
811 '''
812
813 class Rcl(RegOp):
814 code = '''
815 uint8_t shiftAmt =
816 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
817 if(shiftAmt)
818 {
819 CCFlagBits flags = ccFlagBits;
820 uint64_t top = psrc1 << shiftAmt;
821 uint64_t bottom = flags.cf << (shiftAmt - 1);
822 if(shiftAmt > 1)
823 bottom |=
824 bits(psrc1, dataSize * 8 - 1,
825 dataSize * 8 - shiftAmt + 1);
826 DestReg = merge(DestReg, top | bottom, dataSize);
827 }
828 else
829 DestReg = DestReg;
830 '''
831 flag_code = '''
832 // If the shift amount is zero, no flags should be modified.
833 if (shiftAmt) {
834 //Zero out any flags we might modify. This way we only have to
835 //worry about setting them.
836 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
837 int msb = bits(DestReg, dataSize * 8 - 1);
838 int CFBits = bits(SrcReg1, dataSize * 8 - shiftAmt);
839 //If some combination of the CF bits need to be set, set them.
840 if ((ext & (CFBit | ECFBit)) && CFBits)
841 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
842 //Figure out what the OF bit should be.
843 if ((ext & OFBit) && (msb ^ CFBits))
844 ccFlagBits = ccFlagBits | OFBit;
845 //Use the regular mechanisms to calculate the other flags.
846 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
847 DestReg, psrc1, op2);
848 }
849 '''
850
851 class Wrip(WrRegOp, CondRegOp):
852 code = 'RIP = psrc1 + sop2 + CSBase'
853 else_code="RIP = RIP;"
854
855 class Wruflags(WrRegOp):
856 code = 'ccFlagBits = psrc1 ^ op2'
857
858 class Wrflags(WrRegOp):
859 code = '''
860 MiscReg newFlags = psrc1 ^ op2;
861 MiscReg userFlagMask = 0xDD5;
862 // Get only the user flags
863 ccFlagBits = newFlags & userFlagMask;
864 // Get everything else
865 nccFlagBits = newFlags & ~userFlagMask;
866 '''
867
868 class Rdip(RdRegOp):
869 code = 'DestReg = RIP - CSBase'
870
871 class Ruflags(RdRegOp):
872 code = 'DestReg = ccFlagBits'
873
874 class Rflags(RdRegOp):
875 code = 'DestReg = ccFlagBits | nccFlagBits'
876
877 class Ruflag(RegOp):
878 code = '''
879 int flag = bits(ccFlagBits, imm8);
880 DestReg = merge(DestReg, flag, dataSize);
881 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
882 (ccFlagBits & ~EZFBit);
883 '''
884 def __init__(self, dest, imm, flags=None, \
885 dataSize="env.dataSize"):
886 super(Ruflag, self).__init__(dest, \
887 "NUM_INTREGS", imm, flags, dataSize)
888
889 class Rflag(RegOp):
890 code = '''
891 MiscReg flagMask = 0x3F7FDD5;
892 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
893 int flag = bits(flags, imm8);
894 DestReg = merge(DestReg, flag, dataSize);
895 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
896 (ccFlagBits & ~EZFBit);
897 '''
898 def __init__(self, dest, imm, flags=None, \
899 dataSize="env.dataSize"):
900 super(Rflag, self).__init__(dest, \
901 "NUM_INTREGS", imm, flags, dataSize)
902
903 class Sext(RegOp):
904 code = '''
905 IntReg val = psrc1;
906 // Mask the bit position so that it wraps.
907 int bitPos = op2 & (dataSize * 8 - 1);
908 int sign_bit = bits(val, bitPos, bitPos);
909 uint64_t maskVal = mask(bitPos+1);
910 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
911 DestReg = merge(DestReg, val, dataSize);
912 '''
913 flag_code = '''
914 if (!sign_bit)
915 ccFlagBits = ccFlagBits &
916 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
917 else
918 ccFlagBits = ccFlagBits |
919 (ext & (CFBit | ECFBit | ZFBit | EZFBit));
920 '''
921
922 class Zext(RegOp):
923 code = 'DestReg = bits(psrc1, op2, 0);'
924
925 class Rdcr(RegOp):
926 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
927 super(Rdcr, self).__init__(dest, \
928 src1, "NUM_INTREGS", flags, dataSize)
929 code = '''
930 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
931 fault = new InvalidOpcode();
932 } else {
933 DestReg = ControlSrc1;
934 }
935 '''
936
937 class Wrcr(RegOp):
938 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
939 super(Wrcr, self).__init__(dest, \
940 src1, "NUM_INTREGS", flags, dataSize)
941 code = '''
942 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
943 fault = new InvalidOpcode();
944 } else {
945 // There are *s in the line below so it doesn't confuse the
946 // parser. They may be unnecessary.
947 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize);
948 MiscReg newVal = psrc1;
949
950 // Check for any modifications that would cause a fault.
951 switch(dest) {
952 case 0:
953 {
954 Efer efer = EferOp;
955 CR0 cr0 = newVal;
956 CR4 oldCr4 = CR4Op;
957 if (bits(newVal, 63, 32) ||
958 (!cr0.pe && cr0.pg) ||
959 (!cr0.cd && cr0.nw) ||
960 (cr0.pg && efer.lme && !oldCr4.pae))
961 fault = new GeneralProtection(0);
962 }
963 break;
964 case 2:
965 break;
966 case 3:
967 break;
968 case 4:
969 {
970 CR4 cr4 = newVal;
971 // PAE can't be disabled in long mode.
972 if (bits(newVal, 63, 11) ||
973 (machInst.mode.mode == LongMode && !cr4.pae))
974 fault = new GeneralProtection(0);
975 }
976 break;
977 case 8:
978 {
979 if (bits(newVal, 63, 4))
980 fault = new GeneralProtection(0);
981 }
982 default:
983 panic("Unrecognized control register %d.\\n", dest);
984 }
985 ControlDest = newVal;
986 }
987 '''
988
989 # Microops for manipulating segmentation registers
990 class SegOp(CondRegOp):
991 abstract = True
992 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
993 super(SegOp, self).__init__(dest, \
994 src1, "NUM_INTREGS", flags, dataSize)
995
996 class Wrbase(SegOp):
997 code = '''
998 SegBaseDest = psrc1;
999 '''
1000
1001 class Wrlimit(SegOp):
1002 code = '''
1003 SegLimitDest = psrc1;
1004 '''
1005
1006 class Wrsel(SegOp):
1007 code = '''
1008 SegSelDest = psrc1;
1009 '''
1010
1011 class Rdbase(SegOp):
1012 code = '''
1013 DestReg = SegBaseSrc1;
1014 '''
1015
1016 class Rdlimit(SegOp):
1017 code = '''
1018 DestReg = SegLimitSrc1;
1019 '''
1020
1021 class RdAttr(SegOp):
1022 code = '''
1023 DestReg = SegAttrSrc1;
1024 '''
1025
1026 class Rdsel(SegOp):
1027 code = '''
1028 DestReg = SegSelSrc1;
1029 '''
1030
1031 class Chks(RegOp):
1032 def __init__(self, dest, src1, src2=0,
1033 flags=None, dataSize="env.dataSize"):
1034 super(Chks, self).__init__(dest,
1035 src1, src2, flags, dataSize)
1036 code = '''
1037 // The selector is in source 1 and can be at most 16 bits.
1038 SegSelector selector = DestReg;
1039 SegDescriptor desc = SrcReg1;
1040 HandyM5Reg m5reg = M5Reg;
1041
1042 switch (imm8)
1043 {
1044 case SegNoCheck:
1045 break;
1046 case SegCSCheck:
1047 panic("CS checks for far calls/jumps not implemented.\\n");
1048 break;
1049 case SegCallGateCheck:
1050 panic("CS checks for far calls/jumps through call gates"
1051 "not implemented.\\n");
1052 break;
1053 case SegIntGateCheck:
1054 if (desc.dpl < m5reg.cpl) {
1055 return new GeneralProtection((uint16_t)selector);
1056 }
1057 break;
1058 case SegSSCheck:
1059 if (selector.si || selector.ti) {
1060 if (!desc.p) {
1061 //FIXME This needs to also push the selector.
1062 return new StackFault;
1063 }
1064 } else {
1065 if ((m5reg.submode != SixtyFourBitMode ||
1066 m5reg.cpl == 3) ||
1067 !(desc.s == 1 &&
1068 desc.type.codeOrData == 0 && desc.type.w) ||
1069 (desc.dpl != m5reg.cpl) ||
1070 (selector.rpl != m5reg.cpl)) {
1071 return new GeneralProtection(psrc1 & 0xFFFF);
1072 }
1073 }
1074 break;
1075 case SegIretCheck:
1076 {
1077 if ((!selector.si && !selector.ti) ||
1078 (selector.rpl < m5reg.cpl) ||
1079 !(desc.s == 1 && desc.type.codeOrData == 1) ||
1080 (!desc.type.c && desc.dpl != selector.rpl) ||
1081 (desc.type.c && desc.dpl > selector.rpl))
1082 return new GeneralProtection(psrc1 & 0xFFFF);
1083 if (!desc.p)
1084 return new SegmentNotPresent;
1085 break;
1086 }
1087 case SegIntCSCheck:
1088 if (m5reg.mode == LongMode) {
1089 if (desc.l != 1 || desc.d != 0) {
1090 return new GeneralProtection(selector);
1091 }
1092 } else {
1093 panic("Interrupt CS checks not implemented "
1094 "in legacy mode.\\n");
1095 }
1096 break;
1097 default:
1098 panic("Undefined segment check type.\\n");
1099 }
1100 '''
1101 flag_code = '''
1102 // Check for a NULL selector and set ZF,EZF appropriately.
1103 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit));
1104 if (!selector.si && !selector.ti)
1105 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit));
1106 '''
1107
1108 class Wrdh(RegOp):
1109 code = '''
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