1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any 9// use which is NOT directed to receiving any direct monetary 10// compensation for, or commercial advantage from such use. Illustrative 11// examples of non-commercial use are academic research, personal study, 12// teaching, education and corporate research & development. 13// Illustrative examples of commercial use are distributing products for 14// commercial advantage and providing services using the software for 15// commercial advantage. 16// 17// If you wish to use this software or functionality therein that may be 18// covered by patents for commercial use, please contact: 19// Director of Intellectual Property Licensing 20// Office of Strategy and Technology 21// Hewlett-Packard Company 22// 1501 Page Mill Road 23// Palo Alto, California 94304 24// 25// Redistributions of source code must retain the above copyright notice, 26// this list of conditions and the following disclaimer. Redistributions 27// in binary form must reproduce the above copyright notice, this list of 28// conditions and the following disclaimer in the documentation and/or 29// other materials provided with the distribution. Neither the name of 30// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 31// contributors may be used to endorse or promote products derived from 32// this software without specific prior written permission. No right of 33// sublicense is granted herewith. Derivatives of the software and 34// output created using the software may be prepared, but only for 35// Non-Commercial Uses. Derivatives of the software may be shared with 36// others provided: (i) the others agree to abide by the list of 37// conditions herein which includes the Non-Commercial Use restrictions; 38// and (ii) such Derivatives of the software include the above copyright 39// notice to acknowledge the contribution from this software where 40// applicable, this list of conditions and the disclaimer below. 41// 42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 45// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 46// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 47// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53// 54// Authors: Gabe Black 55 56////////////////////////////////////////////////////////////////////////// 57// 58// RegOp Microop templates 59// 60////////////////////////////////////////////////////////////////////////// 61 62def template MicroRegOpExecute {{ 63 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 64 Trace::InstRecord *traceData) const 65 { 66 Fault fault = NoFault; 67 68 %(op_decl)s; 69 %(op_rd)s;
| 1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any 9// use which is NOT directed to receiving any direct monetary 10// compensation for, or commercial advantage from such use. Illustrative 11// examples of non-commercial use are academic research, personal study, 12// teaching, education and corporate research & development. 13// Illustrative examples of commercial use are distributing products for 14// commercial advantage and providing services using the software for 15// commercial advantage. 16// 17// If you wish to use this software or functionality therein that may be 18// covered by patents for commercial use, please contact: 19// Director of Intellectual Property Licensing 20// Office of Strategy and Technology 21// Hewlett-Packard Company 22// 1501 Page Mill Road 23// Palo Alto, California 94304 24// 25// Redistributions of source code must retain the above copyright notice, 26// this list of conditions and the following disclaimer. Redistributions 27// in binary form must reproduce the above copyright notice, this list of 28// conditions and the following disclaimer in the documentation and/or 29// other materials provided with the distribution. Neither the name of 30// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 31// contributors may be used to endorse or promote products derived from 32// this software without specific prior written permission. No right of 33// sublicense is granted herewith. Derivatives of the software and 34// output created using the software may be prepared, but only for 35// Non-Commercial Uses. Derivatives of the software may be shared with 36// others provided: (i) the others agree to abide by the list of 37// conditions herein which includes the Non-Commercial Use restrictions; 38// and (ii) such Derivatives of the software include the above copyright 39// notice to acknowledge the contribution from this software where 40// applicable, this list of conditions and the disclaimer below. 41// 42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 45// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 46// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 47// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53// 54// Authors: Gabe Black 55 56////////////////////////////////////////////////////////////////////////// 57// 58// RegOp Microop templates 59// 60////////////////////////////////////////////////////////////////////////// 61 62def template MicroRegOpExecute {{ 63 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 64 Trace::InstRecord *traceData) const 65 { 66 Fault fault = NoFault; 67 68 %(op_decl)s; 69 %(op_rd)s;
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70 %(code)s; 71 %(flag_code)s;
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72
| 70
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| 71 if(%(cond_check)s) 72 { 73 %(code)s; 74 %(flag_code)s; 75 } 76
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73 //Write the resulting state to the execution context 74 if(fault == NoFault) 75 { 76 %(op_wb)s; 77 } 78 return fault; 79 } 80}}; 81 82def template MicroRegOpImmExecute {{ 83 Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc, 84 Trace::InstRecord *traceData) const 85 { 86 Fault fault = NoFault; 87 88 %(op_decl)s; 89 %(op_rd)s;
| 77 //Write the resulting state to the execution context 78 if(fault == NoFault) 79 { 80 %(op_wb)s; 81 } 82 return fault; 83 } 84}}; 85 86def template MicroRegOpImmExecute {{ 87 Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc, 88 Trace::InstRecord *traceData) const 89 { 90 Fault fault = NoFault; 91 92 %(op_decl)s; 93 %(op_rd)s;
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90 %(code)s; 91 %(flag_code)s;
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92
| 94
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| 95 if(%(cond_check)s) 96 { 97 %(code)s; 98 %(flag_code)s; 99 } 100
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93 //Write the resulting state to the execution context 94 if(fault == NoFault) 95 { 96 %(op_wb)s; 97 } 98 return fault; 99 } 100}}; 101 102def template MicroRegOpDeclare {{ 103 class %(class_name)s : public %(base_class)s 104 { 105 protected: 106 void buildMe(); 107 108 public: 109 %(class_name)s(ExtMachInst _machInst, 110 const char * instMnem, 111 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 112 RegIndex _src1, RegIndex _src2, RegIndex _dest,
| 101 //Write the resulting state to the execution context 102 if(fault == NoFault) 103 { 104 %(op_wb)s; 105 } 106 return fault; 107 } 108}}; 109 110def template MicroRegOpDeclare {{ 111 class %(class_name)s : public %(base_class)s 112 { 113 protected: 114 void buildMe(); 115 116 public: 117 %(class_name)s(ExtMachInst _machInst, 118 const char * instMnem, 119 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 120 RegIndex _src1, RegIndex _src2, RegIndex _dest,
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113 bool _setStatus, uint8_t _dataSize, uint8_t _ext);
| 121 uint8_t _dataSize, uint8_t _ext);
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114 115 %(class_name)s(ExtMachInst _machInst, 116 const char * instMnem, 117 RegIndex _src1, RegIndex _src2, RegIndex _dest,
| 122 123 %(class_name)s(ExtMachInst _machInst, 124 const char * instMnem, 125 RegIndex _src1, RegIndex _src2, RegIndex _dest,
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118 bool _setStatus, uint8_t _dataSize, uint8_t _ext);
| 126 uint8_t _dataSize, uint8_t _ext);
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119 120 %(BasicExecDeclare)s 121 }; 122}}; 123 124def template MicroRegOpImmDeclare {{ 125 126 class %(class_name)sImm : public %(base_class)s 127 { 128 protected: 129 void buildMe(); 130 131 public: 132 %(class_name)sImm(ExtMachInst _machInst, 133 const char * instMnem, 134 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 135 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
| 127 128 %(BasicExecDeclare)s 129 }; 130}}; 131 132def template MicroRegOpImmDeclare {{ 133 134 class %(class_name)sImm : public %(base_class)s 135 { 136 protected: 137 void buildMe(); 138 139 public: 140 %(class_name)sImm(ExtMachInst _machInst, 141 const char * instMnem, 142 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 143 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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136 bool _setStatus, uint8_t _dataSize, uint8_t _ext);
| 144 uint8_t _dataSize, uint8_t _ext);
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137 138 %(class_name)sImm(ExtMachInst _machInst, 139 const char * instMnem, 140 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
| 145 146 %(class_name)sImm(ExtMachInst _machInst, 147 const char * instMnem, 148 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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141 bool _setStatus, uint8_t _dataSize, uint8_t _ext);
| 149 uint8_t _dataSize, uint8_t _ext);
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142 143 %(BasicExecDeclare)s 144 }; 145}}; 146 147def template MicroRegOpConstructor {{ 148 149 inline void %(class_name)s::buildMe() 150 { 151 %(constructor)s; 152 } 153 154 inline %(class_name)s::%(class_name)s( 155 ExtMachInst machInst, const char * instMnem, 156 RegIndex _src1, RegIndex _src2, RegIndex _dest,
| 150 151 %(BasicExecDeclare)s 152 }; 153}}; 154 155def template MicroRegOpConstructor {{ 156 157 inline void %(class_name)s::buildMe() 158 { 159 %(constructor)s; 160 } 161 162 inline %(class_name)s::%(class_name)s( 163 ExtMachInst machInst, const char * instMnem, 164 RegIndex _src1, RegIndex _src2, RegIndex _dest,
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157 bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
| 165 uint8_t _dataSize, uint8_t _ext) :
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158 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 159 false, false, false, false,
| 166 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 167 false, false, false, false,
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160 _src1, _src2, _dest, _setStatus, _dataSize, _ext,
| 168 _src1, _src2, _dest, _dataSize, _ext,
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161 %(op_class)s) 162 { 163 buildMe(); 164 } 165 166 inline %(class_name)s::%(class_name)s( 167 ExtMachInst machInst, const char * instMnem, 168 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 169 RegIndex _src1, RegIndex _src2, RegIndex _dest,
| 169 %(op_class)s) 170 { 171 buildMe(); 172 } 173 174 inline %(class_name)s::%(class_name)s( 175 ExtMachInst machInst, const char * instMnem, 176 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 177 RegIndex _src1, RegIndex _src2, RegIndex _dest,
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170 bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
| 178 uint8_t _dataSize, uint8_t _ext) :
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171 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 172 isMicro, isDelayed, isFirst, isLast,
| 179 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 180 isMicro, isDelayed, isFirst, isLast,
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173 _src1, _src2, _dest, _setStatus, _dataSize, _ext,
| 181 _src1, _src2, _dest, _dataSize, _ext,
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174 %(op_class)s) 175 { 176 buildMe(); 177 } 178}}; 179 180def template MicroRegOpImmConstructor {{ 181 182 inline void %(class_name)sImm::buildMe() 183 { 184 %(constructor)s; 185 } 186 187 inline %(class_name)sImm::%(class_name)sImm( 188 ExtMachInst machInst, const char * instMnem, 189 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
| 182 %(op_class)s) 183 { 184 buildMe(); 185 } 186}}; 187 188def template MicroRegOpImmConstructor {{ 189 190 inline void %(class_name)sImm::buildMe() 191 { 192 %(constructor)s; 193 } 194 195 inline %(class_name)sImm::%(class_name)sImm( 196 ExtMachInst machInst, const char * instMnem, 197 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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190 bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
| 198 uint8_t _dataSize, uint8_t _ext) :
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191 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 192 false, false, false, false,
| 199 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 200 false, false, false, false,
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193 _src1, _imm8, _dest, _setStatus, _dataSize, _ext,
| 201 _src1, _imm8, _dest, _dataSize, _ext,
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194 %(op_class)s) 195 { 196 buildMe(); 197 } 198 199 inline %(class_name)sImm::%(class_name)sImm( 200 ExtMachInst machInst, const char * instMnem, 201 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 202 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
| 202 %(op_class)s) 203 { 204 buildMe(); 205 } 206 207 inline %(class_name)sImm::%(class_name)sImm( 208 ExtMachInst machInst, const char * instMnem, 209 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 210 RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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203 bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
| 211 uint8_t _dataSize, uint8_t _ext) :
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204 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 205 isMicro, isDelayed, isFirst, isLast,
| 212 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 213 isMicro, isDelayed, isFirst, isLast,
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206 _src1, _imm8, _dest, _setStatus, _dataSize, _ext,
| 214 _src1, _imm8, _dest, _dataSize, _ext,
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207 %(op_class)s) 208 { 209 buildMe(); 210 } 211}}; 212 213let {{
| 215 %(op_class)s) 216 { 217 buildMe(); 218 } 219}}; 220 221let {{
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| 222 class X86MicroMeta(type): 223 def __new__(mcls, name, bases, dict): 224 abstract = False 225 if "abstract" in dict: 226 abstract = dict['abstract'] 227 del dict['abstract'] 228 229 cls = type.__new__(mcls, name, bases, dict) 230 if not abstract: 231 allClasses[name] = cls 232 return cls 233 234 class XXX86Microop(object): 235 __metaclass__ = X86MicroMeta 236 abstract = True 237
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214 class RegOp(X86Microop):
| 238 class RegOp(X86Microop):
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215 def __init__(self, dest, src1, src2, setStatus):
| 239 abstract = True 240 def __init__(self, dest, src1, src2, flags):
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216 self.dest = dest 217 self.src1 = src1 218 self.src2 = src2
| 241 self.dest = dest 242 self.src1 = src1 243 self.src2 = src2
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219 self.setStatus = setStatus
| 244 self.flags = flags
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220 self.dataSize = "env.dataSize"
| 245 self.dataSize = "env.dataSize"
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221 self.ext = 0
| 246 if flags is None: 247 self.ext = 0 248 else: 249 if not isinstance(flags, (list, tuple)): 250 raise Exception, "flags must be a list or tuple of flags" 251 self.ext = " | ".join(flags) 252 self.className += "Flags"
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222 223 def getAllocator(self, *microFlags): 224 allocator = '''new %(class_name)s(machInst, mnemonic 225 %(flags)s, %(src1)s, %(src2)s, %(dest)s,
| 253 254 def getAllocator(self, *microFlags): 255 allocator = '''new %(class_name)s(machInst, mnemonic 256 %(flags)s, %(src1)s, %(src2)s, %(dest)s,
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226 %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
| 257 %(dataSize)s, %(ext)s)''' % {
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227 "class_name" : self.className, 228 "flags" : self.microFlagsText(microFlags), 229 "src1" : self.src1, "src2" : self.src2, 230 "dest" : self.dest,
| 258 "class_name" : self.className, 259 "flags" : self.microFlagsText(microFlags), 260 "src1" : self.src1, "src2" : self.src2, 261 "dest" : self.dest,
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231 "setStatus" : self.cppBool(self.setStatus),
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232 "dataSize" : self.dataSize, 233 "ext" : self.ext} 234 return allocator 235 236 class RegOpImm(X86Microop):
| 262 "dataSize" : self.dataSize, 263 "ext" : self.ext} 264 return allocator 265 266 class RegOpImm(X86Microop):
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237 def __init__(self, dest, src1, imm8, setStatus):
| 267 abstract = True 268 def __init__(self, dest, src1, imm8, flags):
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238 self.dest = dest 239 self.src1 = src1 240 self.imm8 = imm8
| 269 self.dest = dest 270 self.src1 = src1 271 self.imm8 = imm8
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241 self.setStatus = setStatus
| 272 self.flags = flags
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242 self.dataSize = "env.dataSize"
| 273 self.dataSize = "env.dataSize"
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243 self.ext = 0
| 274 if flags is None: 275 self.ext = 0 276 else: 277 if not isinstance(flags, (list, tuple)): 278 raise Exception, "flags must be a list or tuple of flags" 279 self.ext = " | ".join(flags) 280 self.className += "Flags"
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244 245 def getAllocator(self, *microFlags): 246 allocator = '''new %(class_name)s(machInst, mnemonic 247 %(flags)s, %(src1)s, %(imm8)s, %(dest)s,
| 281 282 def getAllocator(self, *microFlags): 283 allocator = '''new %(class_name)s(machInst, mnemonic 284 %(flags)s, %(src1)s, %(imm8)s, %(dest)s,
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248 %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
| 285 %(dataSize)s, %(ext)s)''' % {
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249 "class_name" : self.className, 250 "flags" : self.microFlagsText(microFlags), 251 "src1" : self.src1, "imm8" : self.imm8, 252 "dest" : self.dest,
| 286 "class_name" : self.className, 287 "flags" : self.microFlagsText(microFlags), 288 "src1" : self.src1, "imm8" : self.imm8, 289 "dest" : self.dest,
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253 "setStatus" : self.cppBool(self.setStatus),
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254 "dataSize" : self.dataSize, 255 "ext" : self.ext} 256 return allocator 257}}; 258 259let {{ 260 261 # Make these empty strings so that concatenating onto 262 # them will always work. 263 header_output = "" 264 decoder_output = "" 265 exec_output = "" 266
| 290 "dataSize" : self.dataSize, 291 "ext" : self.ext} 292 return allocator 293}}; 294 295let {{ 296 297 # Make these empty strings so that concatenating onto 298 # them will always work. 299 header_output = "" 300 decoder_output = "" 301 exec_output = "" 302
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267 def setUpMicroRegOp(name, Name, base, code, child, flagCode):
| 303 # A function which builds the C++ classes that implement the microops 304 def setUpMicroRegOp(name, Name, base, code, flagCode, condCheck):
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268 global header_output 269 global decoder_output 270 global exec_output 271 global microopClasses 272 273 iop = InstObjParams(name, Name, base, 274 {"code" : code,
| 305 global header_output 306 global decoder_output 307 global exec_output 308 global microopClasses 309 310 iop = InstObjParams(name, Name, base, 311 {"code" : code,
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275 "flag_code" : flagCode})
| 312 "flag_code" : flagCode, 313 "cond_check" : condCheck})
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276 header_output += MicroRegOpDeclare.subst(iop) 277 decoder_output += MicroRegOpConstructor.subst(iop) 278 exec_output += MicroRegOpExecute.subst(iop) 279
| 314 header_output += MicroRegOpDeclare.subst(iop) 315 decoder_output += MicroRegOpConstructor.subst(iop) 316 exec_output += MicroRegOpExecute.subst(iop) 317
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280 microopClasses[name] = child
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281
| 318
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282 def defineMicroRegOp(mnemonic, code, flagCode):
| 319 checkCCFlagBits = "checkCondition(ccFlagBits)" 320 genCCFlagBits = "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, %s);" 321 322 323 # This creates a python representations of a microop which are a cross 324 # product of reg/immediate and flag/no flag versions. 325 def defineMicroRegOp(mnemonic, code, secondSrc = "op2", cc=False):
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283 Name = mnemonic 284 name = mnemonic.lower() 285 286 # Find op2 in each of the instruction definitions. Create two versions 287 # of the code, one with an integer operand, and one with an immediate 288 # operand. 289 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 290 regCode = matcher.sub("SrcReg2", code) 291 immCode = matcher.sub("imm8", code) 292
| 326 Name = mnemonic 327 name = mnemonic.lower() 328 329 # Find op2 in each of the instruction definitions. Create two versions 330 # of the code, one with an integer operand, and one with an immediate 331 # operand. 332 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 333 regCode = matcher.sub("SrcReg2", code) 334 immCode = matcher.sub("imm8", code) 335
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293 # Build the all register version of this micro op
| 336 if not cc: 337 flagCode = genCCFlagBits % secondSrc 338 condCode = "true" 339 else: 340 flagCode = "" 341 condCode = checkCCFlagBits 342 343 regFlagCode = matcher.sub("SrcReg2", flagCode) 344 immFlagCode = matcher.sub("imm8", flagCode) 345
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294 class RegOpChild(RegOp):
| 346 class RegOpChild(RegOp):
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295 def __init__(self, dest, src1, src2, setStatus=False): 296 super(RegOpChild, self).__init__(dest, src1, src2, setStatus) 297 self.className = Name 298 self.mnemonic = name
| 347 mnemonic = name 348 className = Name 349 def __init__(self, dest, src1, src2, flags=None): 350 super(RegOpChild, self).__init__(dest, src1, src2, flags)
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299
| 351
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300 setUpMicroRegOp(name, Name, "X86ISA::RegOp", \ 301 regCode, RegOpChild, flagCode);
| 352 microopClasses[name] = RegOpChild
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302
| 353
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303 # Build the immediate version of this micro op
| 354 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true"); 355 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, regFlagCode, condCode); 356
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304 class RegOpChildImm(RegOpImm):
| 357 class RegOpChildImm(RegOpImm):
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305 def __init__(self, dest, src1, src2, setStatus=False): 306 super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus) 307 self.className = Name + "Imm" 308 self.mnemonic = name + "i"
| 358 mnemonic = name + 'i' 359 className = Name + 'Imm' 360 def __init__(self, dest, src1, src2, flags=None): 361 super(RegOpChildImm, self).__init__(dest, src1, src2, flags)
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309
| 362
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310 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \ 311 immCode, RegOpChildImm, flagCode);
| 363 microopClasses[name + 'i'] = RegOpChildImm
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312
| 364
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313 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF 314 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "") 315 defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF 316 defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF 317 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "") 318 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF 319 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "") 320 defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', "") #Needs to set OF,CF,SF and not DestReg 321 defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', "")
| 365 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true"); 366 setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, immFlagCode, condCode);
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322
| 367
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| 368 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') 369 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') 370 defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') 371 defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2') 372 defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') 373 defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2') 374 defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') 375 defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', '-op2') 376 defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', cc=True) 377
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323 # This has it's own function because Wr ops have implicit destinations 324 def defineMicroRegOpWr(mnemonic, code): 325 Name = mnemonic 326 name = mnemonic.lower() 327 328 # Find op2 in each of the instruction definitions. Create two versions 329 # of the code, one with an integer operand, and one with an immediate 330 # operand. 331 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 332 regCode = matcher.sub("SrcReg2", code) 333 immCode = matcher.sub("imm8", code) 334
| 378 # This has it's own function because Wr ops have implicit destinations 379 def defineMicroRegOpWr(mnemonic, code): 380 Name = mnemonic 381 name = mnemonic.lower() 382 383 # Find op2 in each of the instruction definitions. Create two versions 384 # of the code, one with an integer operand, and one with an immediate 385 # operand. 386 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 387 regCode = matcher.sub("SrcReg2", code) 388 immCode = matcher.sub("imm8", code) 389
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335 # Build the all register version of this micro op
| |
336 class RegOpChild(RegOp):
| 390 class RegOpChild(RegOp):
|
337 def __init__(self, src1, src2): 338 super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False) 339 self.className = Name 340 self.mnemonic = name
| 391 mnemonic = name 392 className = Name 393 def __init__(self, src1, src2, flags=None): 394 super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags)
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341
| 395
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342 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, RegOpChild, "");
| 396 microopClasses[name] = RegOpChild
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343
| 397
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344 # Build the immediate version of this micro op
| 398 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true"); 399 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, "", checkCCFlagBits); 400
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345 class RegOpChildImm(RegOpImm):
| 401 class RegOpChildImm(RegOpImm):
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| 402 mnemonic = name 403 className = Name
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346 def __init__(self, src1, src2):
| 404 def __init__(self, src1, src2):
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347 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False) 348 self.className = Name + "Imm" 349 self.mnemonic = name + "i"
| 405 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, None)
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350
| 406
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351 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \ 352 immCode, RegOpChildImm, "");
| 407 microopClasses[name + 'i'] = RegOpChildImm
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353
| 408
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| 409 setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true"); 410 setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, "", checkCCFlagBits); 411
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354 defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2') 355 356 # This has it's own function because Rd ops don't always have two parameters 357 def defineMicroRegOpRd(mnemonic, code): 358 Name = mnemonic 359 name = mnemonic.lower() 360 361 class RegOpChild(RegOp): 362 def __init__(self, dest, src1 = "NUM_INTREGS"):
| 412 defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2') 413 414 # This has it's own function because Rd ops don't always have two parameters 415 def defineMicroRegOpRd(mnemonic, code): 416 Name = mnemonic 417 name = mnemonic.lower() 418 419 class RegOpChild(RegOp): 420 def __init__(self, dest, src1 = "NUM_INTREGS"):
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363 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False)
| 421 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None)
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364 self.className = Name 365 self.mnemonic = name 366
| 422 self.className = Name 423 self.mnemonic = name 424
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367 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, RegOpChild, "");
| 425 microopClasses[name] = RegOpChild
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368
| 426
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| 427 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, "", "true"); 428
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369 defineMicroRegOpRd('Rdip', 'DestReg = RIP') 370 371 def defineMicroRegOpImm(mnemonic, code): 372 Name = mnemonic 373 name = mnemonic.lower() 374 375 class RegOpChild(RegOpImm): 376 def __init__(self, dest, src1, src2):
| 429 defineMicroRegOpRd('Rdip', 'DestReg = RIP') 430 431 def defineMicroRegOpImm(mnemonic, code): 432 Name = mnemonic 433 name = mnemonic.lower() 434 435 class RegOpChild(RegOpImm): 436 def __init__(self, dest, src1, src2):
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377 super(RegOpChild, self).__init__(dest, src1, src2, False)
| 437 super(RegOpChild, self).__init__(dest, src1, src2, None)
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378 self.className = Name 379 self.mnemonic = name 380
| 438 self.className = Name 439 self.mnemonic = name 440
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381 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, RegOpChild, "");
| 441 microopClasses[name] = RegOpChild
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382
| 442
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| 443 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, "", "true"); 444
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383 defineMicroRegOpImm('Sext', ''' 384 IntReg val = SrcReg1; 385 int sign_bit = bits(val, imm8-1, imm8-1); 386 val = sign_bit ? (val | ~mask(imm8)) : val; 387 DestReg = merge(DestReg, val, dataSize);''') 388}};
| 445 defineMicroRegOpImm('Sext', ''' 446 IntReg val = SrcReg1; 447 int sign_bit = bits(val, imm8-1, imm8-1); 448 val = sign_bit ? (val | ~mask(imm8)) : val; 449 DestReg = merge(DestReg, val, dataSize);''') 450}};
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