regop.isa (4688:82d7cbf0e66d) | regop.isa (4701:6086c14956da) |
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1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 223 unchanged lines hidden (view full) --- 232 return cls 233 234 class XXX86Microop(object): 235 __metaclass__ = X86MicroMeta 236 abstract = True 237 238 class RegOp(X86Microop): 239 abstract = True | 1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 223 unchanged lines hidden (view full) --- 232 return cls 233 234 class XXX86Microop(object): 235 __metaclass__ = X86MicroMeta 236 abstract = True 237 238 class RegOp(X86Microop): 239 abstract = True |
240 def __init__(self, dest, src1, src2, flags): | 240 def __init__(self, dest, src1, src2, flags, dataSize): |
241 self.dest = dest 242 self.src1 = src1 243 self.src2 = src2 244 self.flags = flags | 241 self.dest = dest 242 self.src1 = src1 243 self.src2 = src2 244 self.flags = flags |
245 self.dataSize = "env.dataSize" | 245 self.dataSize = dataSize |
246 if flags is None: 247 self.ext = 0 248 else: 249 if not isinstance(flags, (list, tuple)): 250 raise Exception, "flags must be a list or tuple of flags" 251 self.ext = " | ".join(flags) 252 self.className += "Flags" 253 --- 6 unchanged lines hidden (view full) --- 260 "src1" : self.src1, "src2" : self.src2, 261 "dest" : self.dest, 262 "dataSize" : self.dataSize, 263 "ext" : self.ext} 264 return allocator 265 266 class RegOpImm(X86Microop): 267 abstract = True | 246 if flags is None: 247 self.ext = 0 248 else: 249 if not isinstance(flags, (list, tuple)): 250 raise Exception, "flags must be a list or tuple of flags" 251 self.ext = " | ".join(flags) 252 self.className += "Flags" 253 --- 6 unchanged lines hidden (view full) --- 260 "src1" : self.src1, "src2" : self.src2, 261 "dest" : self.dest, 262 "dataSize" : self.dataSize, 263 "ext" : self.ext} 264 return allocator 265 266 class RegOpImm(X86Microop): 267 abstract = True |
268 def __init__(self, dest, src1, imm8, flags): | 268 def __init__(self, dest, src1, imm8, flags, dataSize): |
269 self.dest = dest 270 self.src1 = src1 271 self.imm8 = imm8 272 self.flags = flags | 269 self.dest = dest 270 self.src1 = src1 271 self.imm8 = imm8 272 self.flags = flags |
273 self.dataSize = "env.dataSize" | 273 self.dataSize = dataSize |
274 if flags is None: 275 self.ext = 0 276 else: 277 if not isinstance(flags, (list, tuple)): 278 raise Exception, "flags must be a list or tuple of flags" 279 self.ext = " | ".join(flags) 280 self.className += "Flags" 281 --- 59 unchanged lines hidden (view full) --- 341 condCode = checkCCFlagBits 342 343 regFlagCode = matcher.sub("SrcReg2", flagCode) 344 immFlagCode = matcher.sub("imm8", flagCode) 345 346 class RegOpChild(RegOp): 347 mnemonic = name 348 className = Name | 274 if flags is None: 275 self.ext = 0 276 else: 277 if not isinstance(flags, (list, tuple)): 278 raise Exception, "flags must be a list or tuple of flags" 279 self.ext = " | ".join(flags) 280 self.className += "Flags" 281 --- 59 unchanged lines hidden (view full) --- 341 condCode = checkCCFlagBits 342 343 regFlagCode = matcher.sub("SrcReg2", flagCode) 344 immFlagCode = matcher.sub("imm8", flagCode) 345 346 class RegOpChild(RegOp): 347 mnemonic = name 348 className = Name |
349 def __init__(self, dest, src1, src2, flags=None): 350 super(RegOpChild, self).__init__(dest, src1, src2, flags) | 349 def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"): 350 super(RegOpChild, self).__init__(dest, src1, src2, flags, dataSize) |
351 352 microopClasses[name] = RegOpChild 353 354 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true"); 355 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, regFlagCode, condCode); 356 357 class RegOpChildImm(RegOpImm): 358 mnemonic = name + 'i' 359 className = Name + 'Imm' | 351 352 microopClasses[name] = RegOpChild 353 354 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true"); 355 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, regFlagCode, condCode); 356 357 class RegOpChildImm(RegOpImm): 358 mnemonic = name + 'i' 359 className = Name + 'Imm' |
360 def __init__(self, dest, src1, src2, flags=None): 361 super(RegOpChildImm, self).__init__(dest, src1, src2, flags) | 360 def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"): 361 super(RegOpChildImm, self).__init__(dest, src1, src2, flags, dataSize) |
362 363 microopClasses[name + 'i'] = RegOpChildImm 364 365 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true"); 366 setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, immFlagCode, condCode); 367 368 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') 369 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') --- 15 unchanged lines hidden (view full) --- 385 # operand. 386 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 387 regCode = matcher.sub("SrcReg2", code) 388 immCode = matcher.sub("imm8", code) 389 390 class RegOpChild(RegOp): 391 mnemonic = name 392 className = Name | 362 363 microopClasses[name + 'i'] = RegOpChildImm 364 365 setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true"); 366 setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, immFlagCode, condCode); 367 368 defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') 369 defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') --- 15 unchanged lines hidden (view full) --- 385 # operand. 386 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 387 regCode = matcher.sub("SrcReg2", code) 388 immCode = matcher.sub("imm8", code) 389 390 class RegOpChild(RegOp): 391 mnemonic = name 392 className = Name |
393 def __init__(self, src1, src2, flags=None): 394 super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags) | 393 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 394 super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) |
395 396 microopClasses[name] = RegOpChild 397 398 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true"); 399 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, "", checkCCFlagBits); 400 401 class RegOpChildImm(RegOpImm): 402 mnemonic = name 403 className = Name | 395 396 microopClasses[name] = RegOpChild 397 398 setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true"); 399 setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, "", checkCCFlagBits); 400 401 class RegOpChildImm(RegOpImm): 402 mnemonic = name 403 className = Name |
404 def __init__(self, src1, src2): 405 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, None) | 404 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 405 super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) |
406 407 microopClasses[name + 'i'] = RegOpChildImm 408 409 setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true"); 410 setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, "", checkCCFlagBits); 411 412 defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2') 413 414 # This has it's own function because Rd ops don't always have two parameters 415 def defineMicroRegOpRd(mnemonic, code): 416 Name = mnemonic 417 name = mnemonic.lower() 418 419 class RegOpChild(RegOp): | 406 407 microopClasses[name + 'i'] = RegOpChildImm 408 409 setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true"); 410 setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, "", checkCCFlagBits); 411 412 defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2') 413 414 # This has it's own function because Rd ops don't always have two parameters 415 def defineMicroRegOpRd(mnemonic, code): 416 Name = mnemonic 417 name = mnemonic.lower() 418 419 class RegOpChild(RegOp): |
420 def __init__(self, dest, src1 = "NUM_INTREGS"): 421 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None) | 420 def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"): 421 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) |
422 self.className = Name 423 self.mnemonic = name 424 425 microopClasses[name] = RegOpChild 426 427 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, "", "true"); 428 429 defineMicroRegOpRd('Rdip', 'DestReg = RIP') 430 431 def defineMicroRegOpImm(mnemonic, code): 432 Name = mnemonic 433 name = mnemonic.lower() 434 435 class RegOpChild(RegOpImm): | 422 self.className = Name 423 self.mnemonic = name 424 425 microopClasses[name] = RegOpChild 426 427 setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, "", "true"); 428 429 defineMicroRegOpRd('Rdip', 'DestReg = RIP') 430 431 def defineMicroRegOpImm(mnemonic, code): 432 Name = mnemonic 433 name = mnemonic.lower() 434 435 class RegOpChild(RegOpImm): |
436 def __init__(self, dest, src1, src2): 437 super(RegOpChild, self).__init__(dest, src1, src2, None) | 436 def __init__(self, dest, src1, src2, dataSize="env.dataSize"): 437 super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize) |
438 self.className = Name 439 self.mnemonic = name 440 441 microopClasses[name] = RegOpChild 442 443 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, "", "true"); 444 445 defineMicroRegOpImm('Sext', ''' 446 IntReg val = SrcReg1; 447 int sign_bit = bits(val, imm8-1, imm8-1); 448 val = sign_bit ? (val | ~mask(imm8)) : val; 449 DestReg = merge(DestReg, val, dataSize);''') 450}}; | 438 self.className = Name 439 self.mnemonic = name 440 441 microopClasses[name] = RegOpChild 442 443 setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, "", "true"); 444 445 defineMicroRegOpImm('Sext', ''' 446 IntReg val = SrcReg1; 447 int sign_bit = bits(val, imm8-1, imm8-1); 448 val = sign_bit ? (val | ~mask(imm8)) : val; 449 DestReg = merge(DestReg, val, dataSize);''') 450}}; |