1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38//////////////////////////////////////////////////////////////////////////
39//
40// RegOp Microop templates
41//
42//////////////////////////////////////////////////////////////////////////
43
44def template MicroRegOpExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
47 {
48 Fault fault = NoFault;
49
50 DPRINTF(X86, "The data size is %d\n", dataSize);
51 %(op_decl)s;
52 %(op_rd)s;
53
54 if(%(cond_check)s)
55 {
56 %(code)s;
57 %(flag_code)s;
58 }
59 else
60 {
61 %(else_code)s;
62 }
63
64 //Write the resulting state to the execution context
65 if(fault == NoFault)
66 {
67 %(op_wb)s;
68 }
69 return fault;
70 }
71}};
72
73def template MicroRegOpImmExecute {{
74 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
75 Trace::InstRecord *traceData) const
76 {
77 Fault fault = NoFault;
78
79 %(op_decl)s;
80 %(op_rd)s;
81
82 if(%(cond_check)s)
83 {
84 %(code)s;
85 %(flag_code)s;
86 }
87 else
88 {
89 %(else_code)s;
90 }
91
92 //Write the resulting state to the execution context
93 if(fault == NoFault)
94 {
95 %(op_wb)s;
96 }
97 return fault;
98 }
99}};
100
101def template MicroRegOpDeclare {{
102 class %(class_name)s : public %(base_class)s
103 {
104 public:
105 %(class_name)s(ExtMachInst _machInst,
106 const char * instMnem, uint64_t setFlags,
107 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
108 uint8_t _dataSize, uint16_t _ext);
109
110 %(BasicExecDeclare)s
111 };
112}};
113
114def template MicroRegOpImmDeclare {{
115
116 class %(class_name)s : public %(base_class)s
117 {
118 public:
119 %(class_name)s(ExtMachInst _machInst,
120 const char * instMnem, uint64_t setFlags,
121 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
122 uint8_t _dataSize, uint16_t _ext);
123
124 %(BasicExecDeclare)s
125 };
126}};
127
128def template MicroRegOpConstructor {{
129 inline %(class_name)s::%(class_name)s(
130 ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
131 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
132 uint8_t _dataSize, uint16_t _ext) :
133 %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
134 _src1, _src2, _dest, _dataSize, _ext,
135 %(op_class)s)
136 {
137 %(constructor)s;
138 %(cond_control_flag_init)s;
139 }
140}};
141
142def template MicroRegOpImmConstructor {{
143 inline %(class_name)s::%(class_name)s(
144 ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
145 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
146 uint8_t _dataSize, uint16_t _ext) :
147 %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
148 _src1, _imm8, _dest, _dataSize, _ext,
149 %(op_class)s)
150 {
151 %(constructor)s;
152 %(cond_control_flag_init)s;
153 }
154}};
155
156output header {{
157 void
158 divide(uint64_t dividend, uint64_t divisor,
159 uint64_t &quotient, uint64_t &remainder);
160
161 enum SegmentSelectorCheck {
162 SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck,
163 SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck,
164 SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck
165 };
166
167 enum LongModeDescriptorType {
168 LDT64 = 2,
169 AvailableTSS64 = 9,
170 BusyTSS64 = 0xb,
171 CallGate64 = 0xc,
172 IntGate64 = 0xe,
173 TrapGate64 = 0xf
174 };
175}};
176
177output decoder {{
178 void
179 divide(uint64_t dividend, uint64_t divisor,
180 uint64_t &quotient, uint64_t &remainder)
181 {
182 //Check for divide by zero.
183 assert(divisor != 0);
184 //If the divisor is bigger than the dividend, don't do anything.
185 if (divisor <= dividend) {
186 //Shift the divisor so it's msb lines up with the dividend.
187 int dividendMsb = findMsbSet(dividend);
188 int divisorMsb = findMsbSet(divisor);
189 int shift = dividendMsb - divisorMsb;
190 divisor <<= shift;
191 //Compute what we'll add to the quotient if the divisor isn't
192 //now larger than the dividend.
193 uint64_t quotientBit = 1;
194 quotientBit <<= shift;
195 //If we need to step back a bit (no pun intended) because the
196 //divisor got too to large, do that here. This is the "or two"
197 //part of one or two bit division.
198 if (divisor > dividend) {
199 quotientBit >>= 1;
200 divisor >>= 1;
201 }
202 //Decrement the remainder and increment the quotient.
203 quotient += quotientBit;
204 remainder -= divisor;
205 }
206 }
207}};
208
209let {{
210 # Make these empty strings so that concatenating onto
211 # them will always work.
212 header_output = ""
213 decoder_output = ""
214 exec_output = ""
215
216 immTemplates = (
217 MicroRegOpImmDeclare,
218 MicroRegOpImmConstructor,
219 MicroRegOpImmExecute)
220
221 regTemplates = (
222 MicroRegOpDeclare,
223 MicroRegOpConstructor,
224 MicroRegOpExecute)
225
226 class RegOpMeta(type):
227 def buildCppClasses(self, name, Name, suffix, \
228 code, flag_code, cond_check, else_code, cond_control_flag_init):
229
230 # Globals to stick the output in
231 global header_output
232 global decoder_output
233 global exec_output
234
235 # Stick all the code together so it can be searched at once
236 allCode = "|".join((code, flag_code, cond_check, else_code,
237 cond_control_flag_init))
238
239 # If op2 is used anywhere, make register and immediate versions
240 # of this code.
241 matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?")
242 match = matcher.search(allCode)
243 if match:
244 typeQual = ""
245 if match.group("typeQual"):
246 typeQual = match.group("typeQual")
247 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
248 self.buildCppClasses(name, Name, suffix,
249 matcher.sub(src2_name, code),
250 matcher.sub(src2_name, flag_code),
251 matcher.sub(src2_name, cond_check),
252 matcher.sub(src2_name, else_code),
253 matcher.sub(src2_name, cond_control_flag_init))
254 imm_name = "%simm8" % match.group("prefix")
255 self.buildCppClasses(name + "i", Name, suffix + "Imm",
256 matcher.sub(imm_name, code),
257 matcher.sub(imm_name, flag_code),
258 matcher.sub(imm_name, cond_check),
259 matcher.sub(imm_name, else_code),
260 matcher.sub(imm_name, cond_control_flag_init))
261 return
262
263 # If there's something optional to do with flags, generate
264 # a version without it and fix up this version to use it.
265 if flag_code != "" or cond_check != "true":
266 self.buildCppClasses(name, Name, suffix,
267 code, "", "true", else_code, "")
268 suffix = "Flags" + suffix
269
270 # If psrc1 or psrc2 is used, we need to actually insert code to
271 # compute it.
272 matcher = re.compile("(?<!\w)psrc1(?!\w)")
273 if matcher.search(allCode):
274 code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code
275 matcher = re.compile("(?<!\w)psrc2(?!\w)")
276 if matcher.search(allCode):
277 code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code
278 # Also make available versions which do sign extension
279 matcher = re.compile("(?<!\w)spsrc1(?!\w)")
280 if matcher.search(allCode):
281 code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code
282 matcher = re.compile("(?<!\w)spsrc2(?!\w)")
283 if matcher.search(allCode):
284 code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
285 matcher = re.compile("(?<!\w)simm8(?!\w)")
286 if matcher.search(allCode):
287 code = "int8_t simm8 = imm8;" + code
288
289 base = "X86ISA::RegOp"
290
291 # If imm8 shows up in the code, use the immediate templates, if
292 # not, hopefully the register ones will be correct.
293 templates = regTemplates
294 matcher = re.compile("(?<!\w)s?imm8(?!\w)")
295 if matcher.search(allCode):
296 base += "Imm"
297 templates = immTemplates
298
299 # Get everything ready for the substitution
300 iop = InstObjParams(name, Name + suffix, base,
301 {"code" : code,
302 "flag_code" : flag_code,
303 "cond_check" : cond_check,
304 "else_code" : else_code,
305 "cond_control_flag_init": cond_control_flag_init})
306
307 # Generate the actual code (finally!)
308 header_output += templates[0].subst(iop)
309 decoder_output += templates[1].subst(iop)
310 exec_output += templates[2].subst(iop)
311
312
313 def __new__(mcls, Name, bases, dict):
314 abstract = False
315 name = Name.lower()
316 if "abstract" in dict:
317 abstract = dict['abstract']
318 del dict['abstract']
319
320 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
321 if not abstract:
322 cls.className = Name
323 cls.base_mnemonic = name
324 code = cls.code
325 flag_code = cls.flag_code
326 cond_check = cls.cond_check
327 else_code = cls.else_code
328 cond_control_flag_init = cls.cond_control_flag_init
329
330 # Set up the C++ classes
331 mcls.buildCppClasses(cls, name, Name, "", code, flag_code,
332 cond_check, else_code, cond_control_flag_init)
333
334 # Hook into the microassembler dict
335 global microopClasses
336 microopClasses[name] = cls
337
338 allCode = "|".join((code, flag_code, cond_check, else_code,
339 cond_control_flag_init))
340
341 # If op2 is used anywhere, make register and immediate versions
342 # of this code.
343 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
344 if matcher.search(allCode):
345 microopClasses[name + 'i'] = cls
346 return cls
347
348
349 class RegOp(X86Microop):
350 __metaclass__ = RegOpMeta
351 # This class itself doesn't act as a microop
352 abstract = True
353
354 # Default template parameter values
355 flag_code = ""
356 cond_check = "true"
357 else_code = ";"
358 cond_control_flag_init = ""
359
360 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
361 self.dest = dest
362 self.src1 = src1
363 self.op2 = op2
364 self.flags = flags
365 self.dataSize = dataSize
366 if flags is None:
367 self.ext = 0
368 else:
369 if not isinstance(flags, (list, tuple)):
370 raise Exception, "flags must be a list or tuple of flags"
371 self.ext = " | ".join(flags)
372 self.className += "Flags"
373
374 def getAllocator(self, microFlags):
375 className = self.className
376 if self.mnemonic == self.base_mnemonic + 'i':
377 className += "Imm"
378 allocator = '''new %(class_name)s(machInst, macrocodeBlock,
379 %(flags)s, %(src1)s, %(op2)s, %(dest)s,
380 %(dataSize)s, %(ext)s)''' % {
381 "class_name" : className,
382 "flags" : self.microFlagsText(microFlags),
383 "src1" : self.src1, "op2" : self.op2,
384 "dest" : self.dest,
385 "dataSize" : self.dataSize,
386 "ext" : self.ext}
387 return allocator
388
389 class LogicRegOp(RegOp):
390 abstract = True
391 flag_code = '''
392 //Don't have genFlags handle the OF or CF bits
393 uint64_t mask = CFBit | ECFBit | OFBit;
394 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
395 //If a logic microop wants to set these, it wants to set them to 0.
396 ccFlagBits &= ~(CFBit & ext);
397 ccFlagBits &= ~(ECFBit & ext);
398 ccFlagBits &= ~(OFBit & ext);
399 '''
400
401 class FlagRegOp(RegOp):
402 abstract = True
403 flag_code = \
404 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
405
406 class SubRegOp(RegOp):
407 abstract = True
408 flag_code = \
409 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
410
411 class CondRegOp(RegOp):
412 abstract = True
413 cond_check = "checkCondition(ccFlagBits, ext)"
414 cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];"
415
416 class RdRegOp(RegOp):
417 abstract = True
418 def __init__(self, dest, src1=None, dataSize="env.dataSize"):
419 if not src1:
420 src1 = dest
421 super(RdRegOp, self).__init__(dest, src1, \
422 "InstRegIndex(NUM_INTREGS)", None, dataSize)
423
424 class WrRegOp(RegOp):
425 abstract = True
426 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
427 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
428 src1, src2, flags, dataSize)
429
430 class Add(FlagRegOp):
431 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
432
433 class Or(LogicRegOp):
434 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
435
436 class Adc(FlagRegOp):
437 code = '''
438 CCFlagBits flags = ccFlagBits;
439 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
440 '''
441
442 class Sbb(SubRegOp):
443 code = '''
444 CCFlagBits flags = ccFlagBits;
445 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
446 '''
447
448 class And(LogicRegOp):
449 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
450
451 class Sub(SubRegOp):
452 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
453
454 class Xor(LogicRegOp):
455 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
456
457 class Mul1s(WrRegOp):
458 code = '''
459 ProdLow = psrc1 * op2;
460 int halfSize = (dataSize * 8) / 2;
461 uint64_t shifter = (ULL(1) << halfSize);
462 uint64_t hiResult;
463 uint64_t psrc1_h = psrc1 / shifter;
464 uint64_t psrc1_l = psrc1 & mask(halfSize);
465 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
466 uint64_t psrc2_l = op2 & mask(halfSize);
467 hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
468 ((psrc1_l * psrc2_l) / shifter)) /shifter) +
469 psrc1_h * psrc2_h;
470 if (bits(psrc1, dataSize * 8 - 1))
471 hiResult -= op2;
472 if (bits(op2, dataSize * 8 - 1))
473 hiResult -= psrc1;
474 ProdHi = hiResult;
475 '''
476 flag_code = '''
477 if ((-ProdHi & mask(dataSize * 8)) !=
478 bits(ProdLow, dataSize * 8 - 1)) {
479 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
480 } else {
481 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
482 }
483 '''
484
485 class Mul1u(WrRegOp):
486 code = '''
487 ProdLow = psrc1 * op2;
488 int halfSize = (dataSize * 8) / 2;
489 uint64_t shifter = (ULL(1) << halfSize);
490 uint64_t psrc1_h = psrc1 / shifter;
491 uint64_t psrc1_l = psrc1 & mask(halfSize);
492 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
493 uint64_t psrc2_l = op2 & mask(halfSize);
494 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
495 ((psrc1_l * psrc2_l) / shifter)) / shifter) +
496 psrc1_h * psrc2_h;
497 '''
498 flag_code = '''
499 if (ProdHi) {
500 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
501 } else {
502 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
503 }
504 '''
505
506 class Mulel(RdRegOp):
507 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
508
509 class Muleh(RdRegOp):
510 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
511 if not src1:
512 src1 = dest
513 super(RdRegOp, self).__init__(dest, src1, \
514 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
515 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
516
517 # One or two bit divide
518 class Div1(WrRegOp):
519 code = '''
520 //These are temporaries so that modifying them later won't make
521 //the ISA parser think they're also sources.
522 uint64_t quotient = 0;
523 uint64_t remainder = psrc1;
524 //Similarly, this is a temporary so changing it doesn't make it
525 //a source.
526 uint64_t divisor = op2;
527 //This is a temporary just for consistency and clarity.
528 uint64_t dividend = remainder;
529 //Do the division.
530 if (divisor == 0) {
531 fault = new DivideByZero;
532 } else {
533 divide(dividend, divisor, quotient, remainder);
534 //Record the final results.
535 Remainder = remainder;
536 Quotient = quotient;
537 Divisor = divisor;
538 }
539 '''
540
541 # Step divide
542 class Div2(RegOp):
543 code = '''
544 uint64_t dividend = Remainder;
545 uint64_t divisor = Divisor;
546 uint64_t quotient = Quotient;
547 uint64_t remainder = dividend;
548 int remaining = op2;
549 //If we overshot, do nothing. This lets us unrool division loops a
550 //little.
551 if (divisor == 0) {
552 fault = new DivideByZero;
553 } else if (remaining) {
554 if (divisor & (ULL(1) << 63)) {
555 while (remaining && !(dividend & (ULL(1) << 63))) {
556 dividend = (dividend << 1) |
557 bits(SrcReg1, remaining - 1);
558 quotient <<= 1;
559 remaining--;
560 }
561 if (dividend & (ULL(1) << 63)) {
562 bool highBit = false;
563 if (dividend < divisor && remaining) {
564 highBit = true;
565 dividend = (dividend << 1) |
566 bits(SrcReg1, remaining - 1);
567 quotient <<= 1;
568 remaining--;
569 }
570 if (highBit || divisor <= dividend) {
571 quotient++;
572 dividend -= divisor;
573 }
574 }
575 remainder = dividend;
576 } else {
577 //Shift in bits from the low order portion of the dividend
578 while (dividend < divisor && remaining) {
579 dividend = (dividend << 1) |
580 bits(SrcReg1, remaining - 1);
581 quotient <<= 1;
582 remaining--;
583 }
584 remainder = dividend;
585 //Do the division.
586 divide(dividend, divisor, quotient, remainder);
587 }
588 }
589 //Keep track of how many bits there are still to pull in.
590 DestReg = merge(DestReg, remaining, dataSize);
591 //Record the final results
592 Remainder = remainder;
593 Quotient = quotient;
594 '''
595 flag_code = '''
596 if (remaining == 0)
597 ccFlagBits = ccFlagBits | (ext & EZFBit);
598 else
599 ccFlagBits = ccFlagBits & ~(ext & EZFBit);
600 '''
601
602 class Divq(RdRegOp):
603 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
604
605 class Divr(RdRegOp):
606 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
607
608 class Mov(CondRegOp):
609 code = 'DestReg = merge(SrcReg1, op2, dataSize)'
610 else_code = 'DestReg = DestReg;'
611
612 # Shift instructions
613
614 class Sll(RegOp):
615 code = '''
616 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
617 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
618 '''
619 flag_code = '''
620 // If the shift amount is zero, no flags should be modified.
621 if (shiftAmt) {
622 //Zero out any flags we might modify. This way we only have to
623 //worry about setting them.
624 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
625 int CFBits = 0;
626 //Figure out if we -would- set the CF bits if requested.
627 if (shiftAmt <= dataSize * 8 &&
628 bits(SrcReg1, dataSize * 8 - shiftAmt)) {
629 CFBits = 1;
630 }
631 //If some combination of the CF bits need to be set, set them.
632 if ((ext & (CFBit | ECFBit)) && CFBits)
633 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
634 //Figure out what the OF bit should be.
635 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
636 ccFlagBits = ccFlagBits | OFBit;
637 //Use the regular mechanisms to calculate the other flags.
638 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
639 DestReg, psrc1, op2);
640 }
641 '''
642
643 class Srl(RegOp):
644 code = '''
645 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
646 // Because what happens to the bits shift -in- on a right shift
647 // is not defined in the C/C++ standard, we have to mask them out
648 // to be sure they're zero.
649 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
650 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
651 '''
652 flag_code = '''
653 // If the shift amount is zero, no flags should be modified.
654 if (shiftAmt) {
655 //Zero out any flags we might modify. This way we only have to
656 //worry about setting them.
657 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
658 //If some combination of the CF bits need to be set, set them.
659 if ((ext & (CFBit | ECFBit)) &&
660 shiftAmt <= dataSize * 8 &&
661 bits(SrcReg1, shiftAmt - 1)) {
662 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
663 }
664 //Figure out what the OF bit should be.
665 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
666 ccFlagBits = ccFlagBits | OFBit;
667 //Use the regular mechanisms to calculate the other flags.
668 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
669 DestReg, psrc1, op2);
670 }
671 '''
672
673 class Sra(RegOp):
674 code = '''
675 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
676 // Because what happens to the bits shift -in- on a right shift
677 // is not defined in the C/C++ standard, we have to sign extend
678 // them manually to be sure.
679 uint64_t arithMask = (shiftAmt == 0) ? 0 :
680 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
681 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
682 '''
683 flag_code = '''
684 // If the shift amount is zero, no flags should be modified.
685 if (shiftAmt) {
686 //Zero out any flags we might modify. This way we only have to
687 //worry about setting them.
688 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
689 //If some combination of the CF bits need to be set, set them.
690 uint8_t effectiveShift =
691 (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8);
692 if ((ext & (CFBit | ECFBit)) &&
693 bits(SrcReg1, effectiveShift - 1)) {
694 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
695 }
696 //Use the regular mechanisms to calculate the other flags.
697 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
698 DestReg, psrc1, op2);
699 }
700 '''
701
702 class Ror(RegOp):
703 code = '''
704 uint8_t shiftAmt =
705 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
706 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
707 if(realShiftAmt)
708 {
709 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt);
710 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt);
711 DestReg = merge(DestReg, top | bottom, dataSize);
712 }
713 else
714 DestReg = merge(DestReg, DestReg, dataSize);
715 '''
716 flag_code = '''
717 // If the shift amount is zero, no flags should be modified.
718 if (shiftAmt) {
719 //Zero out any flags we might modify. This way we only have to
720 //worry about setting them.
721 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
722 //Find the most and second most significant bits of the result.
723 int msb = bits(DestReg, dataSize * 8 - 1);
724 int smsb = bits(DestReg, dataSize * 8 - 2);
725 //If some combination of the CF bits need to be set, set them.
726 if ((ext & (CFBit | ECFBit)) && msb)
727 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
728 //Figure out what the OF bit should be.
729 if ((ext & OFBit) && (msb ^ smsb))
730 ccFlagBits = ccFlagBits | OFBit;
731 //Use the regular mechanisms to calculate the other flags.
732 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
733 DestReg, psrc1, op2);
734 }
735 '''
736
737 class Rcr(RegOp):
738 code = '''
739 uint8_t shiftAmt =
740 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
741 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
742 if(realShiftAmt)
743 {
744 CCFlagBits flags = ccFlagBits;
745 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt);
746 if (realShiftAmt > 1)
747 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1);
748 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt);
749 DestReg = merge(DestReg, top | bottom, dataSize);
750 }
751 else
752 DestReg = merge(DestReg, DestReg, dataSize);
753 '''
754 flag_code = '''
755 // If the shift amount is zero, no flags should be modified.
756 if (shiftAmt) {
757 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
758 //Zero out any flags we might modify. This way we only have to
759 //worry about setting them.
760 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
761 //Figure out what the OF bit should be.
762 if ((ext & OFBit) && (origCFBit ^
763 bits(SrcReg1, dataSize * 8 - 1))) {
764 ccFlagBits = ccFlagBits | OFBit;
765 }
766 //If some combination of the CF bits need to be set, set them.
767 if ((ext & (CFBit | ECFBit)) &&
768 (realShiftAmt == 0) ? origCFBit :
769 bits(SrcReg1, realShiftAmt - 1)) {
770 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
771 }
772 //Use the regular mechanisms to calculate the other flags.
773 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
774 DestReg, psrc1, op2);
775 }
776 '''
777
778 class Rol(RegOp):
779 code = '''
780 uint8_t shiftAmt =
781 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
782 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
783 if(realShiftAmt)
784 {
785 uint64_t top = psrc1 << realShiftAmt;
786 uint64_t bottom =
787 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt);
788 DestReg = merge(DestReg, top | bottom, dataSize);
789 }
790 else
791 DestReg = merge(DestReg, DestReg, dataSize);
792 '''
793 flag_code = '''
794 // If the shift amount is zero, no flags should be modified.
795 if (shiftAmt) {
796 //Zero out any flags we might modify. This way we only have to
797 //worry about setting them.
798 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
799 //The CF bits, if set, would be set to the lsb of the result.
800 int lsb = DestReg & 0x1;
801 int msb = bits(DestReg, dataSize * 8 - 1);
802 //If some combination of the CF bits need to be set, set them.
803 if ((ext & (CFBit | ECFBit)) && lsb)
804 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
805 //Figure out what the OF bit should be.
806 if ((ext & OFBit) && (msb ^ lsb))
807 ccFlagBits = ccFlagBits | OFBit;
808 //Use the regular mechanisms to calculate the other flags.
809 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
810 DestReg, psrc1, op2);
811 }
812 '''
813
814 class Rcl(RegOp):
815 code = '''
816 uint8_t shiftAmt =
817 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
818 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
819 if(realShiftAmt)
820 {
821 CCFlagBits flags = ccFlagBits;
822 uint64_t top = psrc1 << realShiftAmt;
823 uint64_t bottom = flags.cf << (realShiftAmt - 1);
824 if(shiftAmt > 1)
825 bottom |=
826 bits(psrc1, dataSize * 8 - 1,
827 dataSize * 8 - realShiftAmt + 1);
828 DestReg = merge(DestReg, top | bottom, dataSize);
829 }
830 else
831 DestReg = merge(DestReg, DestReg, dataSize);
832 '''
833 flag_code = '''
834 // If the shift amount is zero, no flags should be modified.
835 if (shiftAmt) {
836 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
837 //Zero out any flags we might modify. This way we only have to
838 //worry about setting them.
839 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
840 int msb = bits(DestReg, dataSize * 8 - 1);
841 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt);
842 //If some combination of the CF bits need to be set, set them.
843 if ((ext & (CFBit | ECFBit)) &&
844 (realShiftAmt == 0) ? origCFBit : CFBits)
845 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
846 //Figure out what the OF bit should be.
847 if ((ext & OFBit) && (msb ^ CFBits))
848 ccFlagBits = ccFlagBits | OFBit;
849 //Use the regular mechanisms to calculate the other flags.
850 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
851 DestReg, psrc1, op2);
852 }
853 '''
854
855 class Sld(RegOp):
856 code = '''
857 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
858 uint8_t dataBits = dataSize * 8;
859 uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
860 uint64_t result;
861 if (realShiftAmt == 0) {
862 result = psrc1;
863 } else if (realShiftAmt < dataBits) {
864 result = (psrc1 << realShiftAmt) |
865 (DoubleBits >> (dataBits - realShiftAmt));
866 } else {
867 result = (DoubleBits << (realShiftAmt - dataBits)) |
868 (psrc1 >> (2 * dataBits - realShiftAmt));
869 }
870 DestReg = merge(DestReg, result, dataSize);
871 '''
872 flag_code = '''
873 // If the shift amount is zero, no flags should be modified.
874 if (shiftAmt) {
875 //Zero out any flags we might modify. This way we only have to
876 //worry about setting them.
877 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
878 int CFBits = 0;
879 //Figure out if we -would- set the CF bits if requested.
880 if ((realShiftAmt == 0 &&
881 bits(DoubleBits, 0)) ||
882 (realShiftAmt <= dataBits &&
883 bits(SrcReg1, dataBits - realShiftAmt)) ||
884 (realShiftAmt > dataBits &&
885 bits(DoubleBits, 2 * dataBits - realShiftAmt))) {
886 CFBits = 1;
887 }
888 //If some combination of the CF bits need to be set, set them.
889 if ((ext & (CFBit | ECFBit)) && CFBits)
890 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
891 //Figure out what the OF bit should be.
892 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
893 bits(result, dataBits - 1)))
894 ccFlagBits = ccFlagBits | OFBit;
895 //Use the regular mechanisms to calculate the other flags.
896 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
897 DestReg, psrc1, op2);
898 }
899 '''
900
901 class Srd(RegOp):
902 code = '''
903 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
904 uint8_t dataBits = dataSize * 8;
905 uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
906 uint64_t result;
907 if (realShiftAmt == 0) {
908 result = psrc1;
909 } else if (realShiftAmt < dataBits) {
910 // Because what happens to the bits shift -in- on a right
911 // shift is not defined in the C/C++ standard, we have to
912 // mask them out to be sure they're zero.
913 uint64_t logicalMask = mask(dataBits - realShiftAmt);
914 result = ((psrc1 >> realShiftAmt) & logicalMask) |
915 (DoubleBits << (dataBits - realShiftAmt));
916 } else {
917 uint64_t logicalMask = mask(2 * dataBits - realShiftAmt);
918 result = ((DoubleBits >> (realShiftAmt - dataBits)) &
919 logicalMask) |
920 (psrc1 << (2 * dataBits - realShiftAmt));
921 }
922 DestReg = merge(DestReg, result, dataSize);
923 '''
924 flag_code = '''
925 // If the shift amount is zero, no flags should be modified.
926 if (shiftAmt) {
927 //Zero out any flags we might modify. This way we only have to
928 //worry about setting them.
929 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
930 int CFBits = 0;
931 //If some combination of the CF bits need to be set, set them.
932 if ((realShiftAmt == 0 &&
933 bits(DoubleBits, dataBits - 1)) ||
934 (realShiftAmt <= dataBits &&
935 bits(SrcReg1, realShiftAmt - 1)) ||
936 (realShiftAmt > dataBits &&
937 bits(DoubleBits, realShiftAmt - dataBits - 1))) {
938 CFBits = 1;
939 }
940 //If some combination of the CF bits need to be set, set them.
941 if ((ext & (CFBit | ECFBit)) && CFBits)
942 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
943 //Figure out what the OF bit should be.
944 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
945 bits(result, dataBits - 1)))
946 ccFlagBits = ccFlagBits | OFBit;
947 //Use the regular mechanisms to calculate the other flags.
948 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
949 DestReg, psrc1, op2);
950 }
951 '''
952
953 class Mdb(WrRegOp):
954 code = 'DoubleBits = psrc1 ^ op2;'
955
956 class Wrip(WrRegOp, CondRegOp):
957 code = 'NRIP = psrc1 + sop2 + CSBase;'
958 else_code = "NRIP = NRIP;"
959
960 class Wruflags(WrRegOp):
961 code = 'ccFlagBits = psrc1 ^ op2'
962
963 class Wrflags(WrRegOp):
964 code = '''
965 MiscReg newFlags = psrc1 ^ op2;
966 MiscReg userFlagMask = 0xDD5;
967 // Get only the user flags
968 ccFlagBits = newFlags & userFlagMask;
969 // Get everything else
970 nccFlagBits = newFlags & ~userFlagMask;
971 '''
972
973 class Rdip(RdRegOp):
974 code = 'DestReg = NRIP - CSBase;'
975
976 class Ruflags(RdRegOp):
977 code = 'DestReg = ccFlagBits'
978
979 class Rflags(RdRegOp):
980 code = 'DestReg = ccFlagBits | nccFlagBits'
981
982 class Ruflag(RegOp):
983 code = '''
984 int flag = bits(ccFlagBits, imm8);
985 DestReg = merge(DestReg, flag, dataSize);
986 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
987 (ccFlagBits & ~EZFBit);
988 '''
989 def __init__(self, dest, imm, flags=None, \
990 dataSize="env.dataSize"):
991 super(Ruflag, self).__init__(dest, \
992 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
993
994 class Rflag(RegOp):
995 code = '''
996 MiscReg flagMask = 0x3F7FDD5;
997 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
998 int flag = bits(flags, imm8);
999 DestReg = merge(DestReg, flag, dataSize);
1000 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1001 (ccFlagBits & ~EZFBit);
1002 '''
1003 def __init__(self, dest, imm, flags=None, \
1004 dataSize="env.dataSize"):
1005 super(Rflag, self).__init__(dest, \
1006 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1007
1008 class Sext(RegOp):
1009 code = '''
1010 IntReg val = psrc1;
1011 // Mask the bit position so that it wraps.
1012 int bitPos = op2 & (dataSize * 8 - 1);
1013 int sign_bit = bits(val, bitPos, bitPos);
1014 uint64_t maskVal = mask(bitPos+1);
1015 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1016 DestReg = merge(DestReg, val, dataSize);
1017 '''
1018 flag_code = '''
1019 if (!sign_bit)
1020 ccFlagBits = ccFlagBits &
1021 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
1022 else
1023 ccFlagBits = ccFlagBits |
1024 (ext & (CFBit | ECFBit | ZFBit | EZFBit));
1025 '''
1026
1027 class Zext(RegOp):
1028 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
1029
1030 class Rddr(RegOp):
1031 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1032 super(Rddr, self).__init__(dest, \
1033 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1034 code = '''
1035 CR4 cr4 = CR4Op;
1036 DR7 dr7 = DR7Op;
1037 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
1038 fault = new InvalidOpcode();
1039 } else if (dr7.gd) {
1040 fault = new DebugException();
1041 } else {
1042 DestReg = merge(DestReg, DebugSrc1, dataSize);
1043 }
1044 '''
1045
1046 class Wrdr(RegOp):
1047 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1048 super(Wrdr, self).__init__(dest, \
1049 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1050 code = '''
1051 CR4 cr4 = CR4Op;
1052 DR7 dr7 = DR7Op;
1053 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) {
1054 fault = new InvalidOpcode();
1055 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) &&
1056 machInst.mode.mode == LongMode) {
1057 fault = new GeneralProtection(0);
1058 } else if (dr7.gd) {
1059 fault = new DebugException();
1060 } else {
1061 DebugDest = psrc1;
1062 }
1063 '''
1064
1065 class Rdcr(RegOp):
1066 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1067 super(Rdcr, self).__init__(dest, \
1068 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1069 code = '''
1070 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
1071 fault = new InvalidOpcode();
1072 } else {
1073 DestReg = merge(DestReg, ControlSrc1, dataSize);
1074 }
1075 '''
1076
1077 class Wrcr(RegOp):
1078 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1079 super(Wrcr, self).__init__(dest, \
1080 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1081 code = '''
1082 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
1083 fault = new InvalidOpcode();
1084 } else {
1085 // There are *s in the line below so it doesn't confuse the
1086 // parser. They may be unnecessary.
1087 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize);
1088 MiscReg newVal = psrc1;
1089
1090 // Check for any modifications that would cause a fault.
1091 switch(dest) {
1092 case 0:
1093 {
1094 Efer efer = EferOp;
1095 CR0 cr0 = newVal;
1096 CR4 oldCr4 = CR4Op;
1097 if (bits(newVal, 63, 32) ||
1098 (!cr0.pe && cr0.pg) ||
1099 (!cr0.cd && cr0.nw) ||
1100 (cr0.pg && efer.lme && !oldCr4.pae))
1101 fault = new GeneralProtection(0);
1102 }
1103 break;
1104 case 2:
1105 break;
1106 case 3:
1107 break;
1108 case 4:
1109 {
1110 CR4 cr4 = newVal;
1111 // PAE can't be disabled in long mode.
1112 if (bits(newVal, 63, 11) ||
1113 (machInst.mode.mode == LongMode && !cr4.pae))
1114 fault = new GeneralProtection(0);
1115 }
1116 break;
1117 case 8:
1118 {
1119 if (bits(newVal, 63, 4))
1120 fault = new GeneralProtection(0);
1121 }
1122 default:
1123 panic("Unrecognized control register %d.\\n", dest);
1124 }
1125 ControlDest = newVal;
1126 }
1127 '''
1128
1129 # Microops for manipulating segmentation registers
1130 class SegOp(CondRegOp):
1131 abstract = True
1132 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1133 super(SegOp, self).__init__(dest, \
1134 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1135
1136 class Wrbase(SegOp):
1137 code = '''
1138 SegBaseDest = psrc1;
1139 '''
1140
1141 class Wrlimit(SegOp):
1142 code = '''
1143 SegLimitDest = psrc1;
1144 '''
1145
1146 class Wrsel(SegOp):
1147 code = '''
1148 SegSelDest = psrc1;
1149 '''
1150
1151 class WrAttr(SegOp):
1152 code = '''
1153 SegAttrDest = psrc1;
1154 '''
1155
1156 class Rdbase(SegOp):
1157 code = '''
1158 DestReg = merge(DestReg, SegBaseSrc1, dataSize);
1159 '''
1160
1161 class Rdlimit(SegOp):
1162 code = '''
1163 DestReg = merge(DestReg, SegLimitSrc1, dataSize);
1164 '''
1165
1166 class RdAttr(SegOp):
1167 code = '''
1168 DestReg = merge(DestReg, SegAttrSrc1, dataSize);
1169 '''
1170
1171 class Rdsel(SegOp):
1172 code = '''
1173 DestReg = merge(DestReg, SegSelSrc1, dataSize);
1174 '''
1175
1176 class Rdval(RegOp):
1177 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1178 super(Rdval, self).__init__(dest, src1, \
1179 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1180 code = '''
1181 DestReg = MiscRegSrc1;
1182 '''
1183
1184 class Wrval(RegOp):
1185 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1186 super(Wrval, self).__init__(dest, src1, \
1187 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1188 code = '''
1189 MiscRegDest = SrcReg1;
1190 '''
1191
1192 class Chks(RegOp):
1193 def __init__(self, dest, src1, src2=0,
1194 flags=None, dataSize="env.dataSize"):
1195 super(Chks, self).__init__(dest,
1196 src1, src2, flags, dataSize)
1197 code = '''
1198 // The selector is in source 1 and can be at most 16 bits.
1199 SegSelector selector = DestReg;
1200 SegDescriptor desc = SrcReg1;
1201 HandyM5Reg m5reg = M5Reg;
1202
1203 switch (imm8)
1204 {
1205 case SegNoCheck:
1206 break;
1207 case SegCSCheck:
1208 // Make sure it's the right type
1209 if (desc.s == 0 || desc.type.codeOrData != 1) {
1210 fault = new GeneralProtection(0);
1211 } else if (m5reg.cpl != desc.dpl) {
1212 fault = new GeneralProtection(0);
1213 }
1214 break;
1215 case SegCallGateCheck:
1216 panic("CS checks for far calls/jumps through call gates"
1217 "not implemented.\\n");
1218 break;
1219 case SegSoftIntGateCheck:
1220 // Check permissions.
1221 if (desc.dpl < m5reg.cpl) {
1222 fault = new GeneralProtection(selector);
1223 break;
1224 }
1225 // Fall through on purpose
1226 case SegIntGateCheck:
1227 // Make sure the gate's the right type.
1228 if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||
1229 ((desc.type & 0x6) != 0x6)) {
1230 fault = new GeneralProtection(0);
1231 }
1232 break;
1233 case SegSSCheck:
1234 if (selector.si || selector.ti) {
1235 if (!desc.p) {
1236 fault = new StackFault(selector);
1237 }
1238 } else {
1239 if ((m5reg.submode != SixtyFourBitMode ||
1240 m5reg.cpl == 3) ||
1241 !(desc.s == 1 &&
1242 desc.type.codeOrData == 0 && desc.type.w) ||
1243 (desc.dpl != m5reg.cpl) ||
1244 (selector.rpl != m5reg.cpl)) {
1245 fault = new GeneralProtection(selector);
1246 }
1247 }
1248 break;
1249 case SegIretCheck:
1250 {
1251 if ((!selector.si && !selector.ti) ||
1252 (selector.rpl < m5reg.cpl) ||
1253 !(desc.s == 1 && desc.type.codeOrData == 1) ||
1254 (!desc.type.c && desc.dpl != selector.rpl) ||
1255 (desc.type.c && desc.dpl > selector.rpl)) {
1256 fault = new GeneralProtection(selector);
1257 } else if (!desc.p) {
1258 fault = new SegmentNotPresent(selector);
1259 }
1260 break;
1261 }
1262 case SegIntCSCheck:
1263 if (m5reg.mode == LongMode) {
1264 if (desc.l != 1 || desc.d != 0) {
1265 fault = new GeneralProtection(selector);
1266 }
1267 } else {
1268 panic("Interrupt CS checks not implemented "
1269 "in legacy mode.\\n");
1270 }
1271 break;
1272 case SegTRCheck:
1273 if (!selector.si || selector.ti) {
1274 fault = new GeneralProtection(selector);
1275 }
1276 break;
1277 case SegTSSCheck:
1278 if (!desc.p) {
1279 fault = new SegmentNotPresent(selector);
1280 } else if (!(desc.type == 0x9 ||
1281 (desc.type == 1 &&
1282 m5reg.mode != LongMode))) {
1283 fault = new GeneralProtection(selector);
1284 }
1285 break;
1286 case SegInGDTCheck:
1287 if (selector.ti) {
1288 fault = new GeneralProtection(selector);
1289 }
1290 break;
1291 case SegLDTCheck:
1292 if (!desc.p) {
1293 fault = new SegmentNotPresent(selector);
1294 } else if (desc.type != 0x2) {
1295 fault = new GeneralProtection(selector);
1296 }
1297 break;
1298 default:
1299 panic("Undefined segment check type.\\n");
1300 }
1301 '''
1302 flag_code = '''
1303 // Check for a NULL selector and set ZF,EZF appropriately.
1304 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit));
1305 if (!selector.si && !selector.ti)
1306 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit));
1307 '''
1308
1309 class Wrdh(RegOp):
1310 code = '''
1311 SegDescriptor desc = SrcReg1;
1312
1313 uint64_t target = bits(SrcReg2, 31, 0) << 32;
1314 switch(desc.type) {
1315 case LDT64:
1316 case AvailableTSS64:
1317 case BusyTSS64:
1318 replaceBits(target, 23, 0, desc.baseLow);
1319 replaceBits(target, 31, 24, desc.baseHigh);
1320 break;
1321 case CallGate64:
1322 case IntGate64:
1323 case TrapGate64:
1324 replaceBits(target, 15, 0, bits(desc, 15, 0));
1325 replaceBits(target, 31, 16, bits(desc, 63, 48));
1326 break;
1327 default:
1328 panic("Wrdh used with wrong descriptor type!\\n");
1329 }
1330 DestReg = target;
1331 '''
1332
1333 class Wrtsc(WrRegOp):
1334 code = '''
1335 TscOp = psrc1;
1336 '''
1337
1338 class Rdtsc(RdRegOp):
1339 code = '''
1340 DestReg = TscOp;
1341 '''
1342
1343 class Rdm5reg(RdRegOp):
1344 code = '''
1345 DestReg = M5Reg;
1346 '''
1347
1348 class Wrdl(RegOp):
1349 code = '''
1350 SegDescriptor desc = SrcReg1;
1351 SegSelector selector = SrcReg2;
1352 if (selector.si || selector.ti) {
1353 if (!desc.p)
1354 panic("Segment not present.\\n");
1355 SegAttr attr = 0;
1356 attr.dpl = desc.dpl;
1357 attr.unusable = 0;
1358 attr.defaultSize = desc.d;
1359 attr.longMode = desc.l;
1360 attr.avl = desc.avl;
1361 attr.granularity = desc.g;
1362 attr.present = desc.p;
1363 attr.system = desc.s;
1364 attr.type = desc.type;
1365 if (!desc.s) {
1366 // The expand down bit happens to be set for gates.
1367 if (desc.type.e) {
1368 panic("Gate descriptor encountered.\\n");
1369 }
1370 attr.readable = 1;
1371 attr.writable = 1;
1372 attr.expandDown = 0;
1373 } else {
1374 if (desc.type.codeOrData) {
1375 attr.expandDown = 0;
1376 attr.readable = desc.type.r;
1377 attr.writable = 0;
1378 } else {
1379 attr.expandDown = desc.type.e;
1380 attr.readable = 1;
1381 attr.writable = desc.type.w;
1382 }
1383 }
1384 Addr base = desc.baseLow | (desc.baseHigh << 24);
1385 Addr limit = desc.limitLow | (desc.limitHigh << 16);
1386 if (desc.g)
1387 limit = (limit << 12) | mask(12);
1388 SegBaseDest = base;
1389 SegLimitDest = limit;
1390 SegAttrDest = attr;
1391 } else {
1392 SegBaseDest = SegBaseDest;
1393 SegLimitDest = SegLimitDest;
1394 SegAttrDest = SegAttrDest;
1395 }
1396 '''
1397}};