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41//
42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
45// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
46// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
47// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
48// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
50// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53//
54// Authors: Gabe Black
55
56//////////////////////////////////////////////////////////////////////////
57//
58// RegOp Microop templates
59//
60//////////////////////////////////////////////////////////////////////////
61
62def template MicroRegOpExecute {{
63 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
64 Trace::InstRecord *traceData) const
65 {
66 Fault fault = NoFault;
67
68 DPRINTF(X86, "The data size is %d\n", dataSize);
69 %(op_decl)s;
70 %(op_rd)s;
71
72 if(%(cond_check)s)
73 {
74 %(code)s;
75 %(flag_code)s;
76 }
77 else
78 {
79 %(else_code)s;
80 }
81
82 //Write the resulting state to the execution context
83 if(fault == NoFault)
84 {
85 %(op_wb)s;
86 }
87 return fault;
88 }
89}};
90
91def template MicroRegOpImmExecute {{
92 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
93 Trace::InstRecord *traceData) const
94 {
95 Fault fault = NoFault;
96
97 %(op_decl)s;
98 %(op_rd)s;
99
100 if(%(cond_check)s)
101 {
102 %(code)s;
103 %(flag_code)s;
104 }
105 else
106 {
107 %(else_code)s;
108 }
109
110 //Write the resulting state to the execution context
111 if(fault == NoFault)
112 {
113 %(op_wb)s;
114 }
115 return fault;
116 }
117}};
118
119def template MicroRegOpDeclare {{
120 class %(class_name)s : public %(base_class)s
121 {
122 protected:
123 void buildMe();
124
125 public:
126 %(class_name)s(ExtMachInst _machInst,
127 const char * instMnem,
128 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
129 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
130 uint8_t _dataSize, uint16_t _ext);
131
132 %(class_name)s(ExtMachInst _machInst,
133 const char * instMnem,
134 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
135 uint8_t _dataSize, uint16_t _ext);
136
137 %(BasicExecDeclare)s
138 };
139}};
140
141def template MicroRegOpImmDeclare {{
142
143 class %(class_name)s : public %(base_class)s
144 {
145 protected:
146 void buildMe();
147
148 public:
149 %(class_name)s(ExtMachInst _machInst,
150 const char * instMnem,
151 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
152 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
153 uint8_t _dataSize, uint16_t _ext);
154
155 %(class_name)s(ExtMachInst _machInst,
156 const char * instMnem,
157 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
158 uint8_t _dataSize, uint16_t _ext);
159
160 %(BasicExecDeclare)s
161 };
162}};
163
164def template MicroRegOpConstructor {{
165
166 inline void %(class_name)s::buildMe()
167 {
168 %(constructor)s;
169 }
170
171 inline %(class_name)s::%(class_name)s(
172 ExtMachInst machInst, const char * instMnem,
173 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
174 uint8_t _dataSize, uint16_t _ext) :
175 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
176 false, false, false, false,
177 _src1, _src2, _dest, _dataSize, _ext,
178 %(op_class)s)
179 {
180 buildMe();
181 }
182
183 inline %(class_name)s::%(class_name)s(
184 ExtMachInst machInst, const char * instMnem,
185 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
186 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
187 uint8_t _dataSize, uint16_t _ext) :
188 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
189 isMicro, isDelayed, isFirst, isLast,
190 _src1, _src2, _dest, _dataSize, _ext,
191 %(op_class)s)
192 {
193 buildMe();
194 }
195}};
196
197def template MicroRegOpImmConstructor {{
198
199 inline void %(class_name)s::buildMe()
200 {
201 %(constructor)s;
202 }
203
204 inline %(class_name)s::%(class_name)s(
205 ExtMachInst machInst, const char * instMnem,
206 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
207 uint8_t _dataSize, uint16_t _ext) :
208 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
209 false, false, false, false,
210 _src1, _imm8, _dest, _dataSize, _ext,
211 %(op_class)s)
212 {
213 buildMe();
214 }
215
216 inline %(class_name)s::%(class_name)s(
217 ExtMachInst machInst, const char * instMnem,
218 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
219 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
220 uint8_t _dataSize, uint16_t _ext) :
221 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
222 isMicro, isDelayed, isFirst, isLast,
223 _src1, _imm8, _dest, _dataSize, _ext,
224 %(op_class)s)
225 {
226 buildMe();
227 }
228}};
229
230output header {{
231 void
232 divide(uint64_t dividend, uint64_t divisor,
233 uint64_t &quotient, uint64_t &remainder);
234
235 enum SegmentSelectorCheck {
236 SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck,
237 SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck,
238 SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck
239 };
240
241 enum LongModeDescriptorType {
242 LDT64 = 2,
243 AvailableTSS64 = 9,
244 BusyTSS64 = 0xb,
245 CallGate64 = 0xc,
246 IntGate64 = 0xe,
247 TrapGate64 = 0xf
248 };
249}};
250
251output decoder {{
252 void
253 divide(uint64_t dividend, uint64_t divisor,
254 uint64_t &quotient, uint64_t &remainder)
255 {
256 //Check for divide by zero.
257 if (divisor == 0)
258 panic("Divide by zero!\\n");
259 //If the divisor is bigger than the dividend, don't do anything.
260 if (divisor <= dividend) {
261 //Shift the divisor so it's msb lines up with the dividend.
262 int dividendMsb = findMsbSet(dividend);
263 int divisorMsb = findMsbSet(divisor);
264 int shift = dividendMsb - divisorMsb;
265 divisor <<= shift;
266 //Compute what we'll add to the quotient if the divisor isn't
267 //now larger than the dividend.
268 uint64_t quotientBit = 1;
269 quotientBit <<= shift;
270 //If we need to step back a bit (no pun intended) because the
271 //divisor got too to large, do that here. This is the "or two"
272 //part of one or two bit division.
273 if (divisor > dividend) {
274 quotientBit >>= 1;
275 divisor >>= 1;
276 }
277 //Decrement the remainder and increment the quotient.
278 quotient += quotientBit;
279 remainder -= divisor;
280 }
281 }
282}};
283
284let {{
285 # Make these empty strings so that concatenating onto
286 # them will always work.
287 header_output = ""
288 decoder_output = ""
289 exec_output = ""
290
291 immTemplates = (
292 MicroRegOpImmDeclare,
293 MicroRegOpImmConstructor,
294 MicroRegOpImmExecute)
295
296 regTemplates = (
297 MicroRegOpDeclare,
298 MicroRegOpConstructor,
299 MicroRegOpExecute)
300
301 class RegOpMeta(type):
302 def buildCppClasses(self, name, Name, suffix, \
303 code, flag_code, cond_check, else_code):
304
305 # Globals to stick the output in
306 global header_output
307 global decoder_output
308 global exec_output
309
310 # Stick all the code together so it can be searched at once
311 allCode = "|".join((code, flag_code, cond_check, else_code))
312
313 # If op2 is used anywhere, make register and immediate versions
314 # of this code.
315 matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?")
316 match = matcher.search(allCode)
317 if match:
318 typeQual = ""
319 if match.group("typeQual"):
320 typeQual = match.group("typeQual")
321 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
322 self.buildCppClasses(name, Name, suffix,
323 matcher.sub(src2_name, code),
324 matcher.sub(src2_name, flag_code),
325 matcher.sub(src2_name, cond_check),
326 matcher.sub(src2_name, else_code))
327 imm_name = "%simm8" % match.group("prefix")
328 self.buildCppClasses(name + "i", Name, suffix + "Imm",
329 matcher.sub(imm_name, code),
330 matcher.sub(imm_name, flag_code),
331 matcher.sub(imm_name, cond_check),
332 matcher.sub(imm_name, else_code))
333 return
334
335 # If there's something optional to do with flags, generate
336 # a version without it and fix up this version to use it.
337 if flag_code != "" or cond_check != "true":
338 self.buildCppClasses(name, Name, suffix,
339 code, "", "true", else_code)
340 suffix = "Flags" + suffix
341
342 # If psrc1 or psrc2 is used, we need to actually insert code to
343 # compute it.
344 matcher = re.compile("(?<!\w)psrc1(?!\w)")
345 if matcher.search(allCode):
346 code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code
347 matcher = re.compile("(?<!\w)psrc2(?!\w)")
348 if matcher.search(allCode):
349 code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code
350 # Also make available versions which do sign extension
351 matcher = re.compile("(?<!\w)spsrc1(?!\w)")
352 if matcher.search(allCode):
353 code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code
354 matcher = re.compile("(?<!\w)spsrc2(?!\w)")
355 if matcher.search(allCode):
356 code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
357 matcher = re.compile("(?<!\w)simm8(?!\w)")
358 if matcher.search(allCode):
359 code = "int8_t simm8 = imm8;" + code
360
361 base = "X86ISA::RegOp"
362
363 # If imm8 shows up in the code, use the immediate templates, if
364 # not, hopefully the register ones will be correct.
365 templates = regTemplates
366 matcher = re.compile("(?<!\w)s?imm8(?!\w)")
367 if matcher.search(allCode):
368 base += "Imm"
369 templates = immTemplates
370
371 # Get everything ready for the substitution
372 iop = InstObjParams(name, Name + suffix, base,
373 {"code" : code,
374 "flag_code" : flag_code,
375 "cond_check" : cond_check,
376 "else_code" : else_code})
377
378 # Generate the actual code (finally!)
379 header_output += templates[0].subst(iop)
380 decoder_output += templates[1].subst(iop)
381 exec_output += templates[2].subst(iop)
382
383
384 def __new__(mcls, Name, bases, dict):
385 abstract = False
386 name = Name.lower()
387 if "abstract" in dict:
388 abstract = dict['abstract']
389 del dict['abstract']
390
391 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
392 if not abstract:
393 cls.className = Name
394 cls.base_mnemonic = name
395 code = cls.code
396 flag_code = cls.flag_code
397 cond_check = cls.cond_check
398 else_code = cls.else_code
399
400 # Set up the C++ classes
401 mcls.buildCppClasses(cls, name, Name, "",
402 code, flag_code, cond_check, else_code)
403
404 # Hook into the microassembler dict
405 global microopClasses
406 microopClasses[name] = cls
407
408 allCode = "|".join((code, flag_code, cond_check, else_code))
409
410 # If op2 is used anywhere, make register and immediate versions
411 # of this code.
412 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
413 if matcher.search(allCode):
414 microopClasses[name + 'i'] = cls
415 return cls
416
417
418 class RegOp(X86Microop):
419 __metaclass__ = RegOpMeta
420 # This class itself doesn't act as a microop
421 abstract = True
422
423 # Default template parameter values
424 flag_code = ""
425 cond_check = "true"
426 else_code = ";"
427
428 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
429 self.dest = dest
430 self.src1 = src1
431 self.op2 = op2
432 self.flags = flags
433 self.dataSize = dataSize
434 if flags is None:
435 self.ext = 0
436 else:
437 if not isinstance(flags, (list, tuple)):
438 raise Exception, "flags must be a list or tuple of flags"
439 self.ext = " | ".join(flags)
440 self.className += "Flags"
441
442 def getAllocator(self, *microFlags):
443 className = self.className
444 if self.mnemonic == self.base_mnemonic + 'i':
445 className += "Imm"
446 allocator = '''new %(class_name)s(machInst, macrocodeBlock
447 %(flags)s, %(src1)s, %(op2)s, %(dest)s,
448 %(dataSize)s, %(ext)s)''' % {
449 "class_name" : className,
450 "flags" : self.microFlagsText(microFlags),
451 "src1" : self.src1, "op2" : self.op2,
452 "dest" : self.dest,
453 "dataSize" : self.dataSize,
454 "ext" : self.ext}
455 return allocator
456
457 class LogicRegOp(RegOp):
458 abstract = True
459 flag_code = '''
460 //Don't have genFlags handle the OF or CF bits
461 uint64_t mask = CFBit | ECFBit | OFBit;
462 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
463 //If a logic microop wants to set these, it wants to set them to 0.
464 ccFlagBits &= ~(CFBit & ext);
465 ccFlagBits &= ~(ECFBit & ext);
466 ccFlagBits &= ~(OFBit & ext);
467 '''
468
469 class FlagRegOp(RegOp):
470 abstract = True
471 flag_code = \
472 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
473
474 class SubRegOp(RegOp):
475 abstract = True
476 flag_code = \
477 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
478
479 class CondRegOp(RegOp):
480 abstract = True
481 cond_check = "checkCondition(ccFlagBits, ext)"
482
483 class RdRegOp(RegOp):
484 abstract = True
485 def __init__(self, dest, src1=None, dataSize="env.dataSize"):
486 if not src1:
487 src1 = dest
488 super(RdRegOp, self).__init__(dest, src1, \
489 "InstRegIndex(NUM_INTREGS)", None, dataSize)
490
491 class WrRegOp(RegOp):
492 abstract = True
493 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
494 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
495 src1, src2, flags, dataSize)
496
497 class Add(FlagRegOp):
498 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
499
500 class Or(LogicRegOp):
501 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
502
503 class Adc(FlagRegOp):
504 code = '''
505 CCFlagBits flags = ccFlagBits;
506 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
507 '''
508
509 class Sbb(SubRegOp):
510 code = '''
511 CCFlagBits flags = ccFlagBits;
512 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
513 '''
514
515 class And(LogicRegOp):
516 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
517
518 class Sub(SubRegOp):
519 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
520
521 class Xor(LogicRegOp):
522 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
523
524 class Mul1s(WrRegOp):
525 code = '''
526 ProdLow = psrc1 * op2;
527 int halfSize = (dataSize * 8) / 2;
528 uint64_t shifter = (ULL(1) << halfSize);
529 uint64_t hiResult;
530 uint64_t psrc1_h = psrc1 / shifter;
531 uint64_t psrc1_l = psrc1 & mask(halfSize);
532 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
533 uint64_t psrc2_l = op2 & mask(halfSize);
534 hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
535 ((psrc1_l * psrc2_l) / shifter)) /shifter) +
536 psrc1_h * psrc2_h;
537 if (bits(psrc1, dataSize * 8 - 1))
538 hiResult -= op2;
539 if (bits(op2, dataSize * 8 - 1))
540 hiResult -= psrc1;
541 ProdHi = hiResult;
542 '''
543 flag_code = '''
544 if ((-ProdHi & mask(dataSize * 8)) !=
545 bits(ProdLow, dataSize * 8 - 1)) {
546 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
547 } else {
548 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
549 }
550 '''
551
552 class Mul1u(WrRegOp):
553 code = '''
554 ProdLow = psrc1 * op2;
555 int halfSize = (dataSize * 8) / 2;
556 uint64_t shifter = (ULL(1) << halfSize);
557 uint64_t psrc1_h = psrc1 / shifter;
558 uint64_t psrc1_l = psrc1 & mask(halfSize);
559 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
560 uint64_t psrc2_l = op2 & mask(halfSize);
561 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
562 ((psrc1_l * psrc2_l) / shifter)) / shifter) +
563 psrc1_h * psrc2_h;
564 '''
565 flag_code = '''
566 if (ProdHi) {
567 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
568 } else {
569 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
570 }
571 '''
572
573 class Mulel(RdRegOp):
574 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
575
576 class Muleh(RdRegOp):
577 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
578 if not src1:
579 src1 = dest
580 super(RdRegOp, self).__init__(dest, src1, \
581 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
582 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
583
584 # One or two bit divide
585 class Div1(WrRegOp):
586 code = '''
587 //These are temporaries so that modifying them later won't make
588 //the ISA parser think they're also sources.
589 uint64_t quotient = 0;
590 uint64_t remainder = psrc1;
591 //Similarly, this is a temporary so changing it doesn't make it
592 //a source.
593 uint64_t divisor = op2;
594 //This is a temporary just for consistency and clarity.
595 uint64_t dividend = remainder;
596 //Do the division.
597 divide(dividend, divisor, quotient, remainder);
598 //Record the final results.
599 Remainder = remainder;
600 Quotient = quotient;
601 Divisor = divisor;
602 '''
603
604 # Step divide
605 class Div2(RegOp):
606 code = '''
607 uint64_t dividend = Remainder;
608 uint64_t divisor = Divisor;
609 uint64_t quotient = Quotient;
610 uint64_t remainder = dividend;
611 int remaining = op2;
612 //If we overshot, do nothing. This lets us unrool division loops a
613 //little.
614 if (remaining) {
615 if (divisor & (ULL(1) << 63)) {
616 while (remaining && !(dividend & (ULL(1) << 63))) {
617 dividend = (dividend << 1) |
618 bits(SrcReg1, remaining - 1);
619 quotient <<= 1;
620 remaining--;
621 }
622 if (dividend & (ULL(1) << 63)) {
623 bool highBit = false;
624 if (dividend < divisor && remaining) {
625 highBit = true;
626 dividend = (dividend << 1) |
627 bits(SrcReg1, remaining - 1);
628 quotient <<= 1;
629 remaining--;
630 }
631 if (highBit || divisor <= dividend) {
632 quotient++;
633 dividend -= divisor;
634 }
635 }
636 remainder = dividend;
637 } else {
638 //Shift in bits from the low order portion of the dividend
639 while (dividend < divisor && remaining) {
640 dividend = (dividend << 1) |
641 bits(SrcReg1, remaining - 1);
642 quotient <<= 1;
643 remaining--;
644 }
645 remainder = dividend;
646 //Do the division.
647 divide(dividend, divisor, quotient, remainder);
648 }
649 }
650 //Keep track of how many bits there are still to pull in.
651 DestReg = merge(DestReg, remaining, dataSize);
652 //Record the final results
653 Remainder = remainder;
654 Quotient = quotient;
655 '''
656 flag_code = '''
657 if (DestReg == 0)
658 ccFlagBits = ccFlagBits | (ext & EZFBit);
659 else
660 ccFlagBits = ccFlagBits & ~(ext & EZFBit);
661 '''
662
663 class Divq(RdRegOp):
664 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
665
666 class Divr(RdRegOp):
667 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
668
669 class Mov(CondRegOp):
670 code = 'DestReg = merge(SrcReg1, op2, dataSize)'
671 else_code = 'DestReg = DestReg;'
672
673 # Shift instructions
674
675 class Sll(RegOp):
676 code = '''
677 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
678 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
679 '''
680 flag_code = '''
681 // If the shift amount is zero, no flags should be modified.
682 if (shiftAmt) {
683 //Zero out any flags we might modify. This way we only have to
684 //worry about setting them.
685 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
686 int CFBits = 0;
687 //Figure out if we -would- set the CF bits if requested.
688 if (shiftAmt <= dataSize * 8 &&
689 bits(SrcReg1, dataSize * 8 - shiftAmt)) {
690 CFBits = 1;
691 }
692 //If some combination of the CF bits need to be set, set them.
693 if ((ext & (CFBit | ECFBit)) && CFBits)
694 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
695 //Figure out what the OF bit should be.
696 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
697 ccFlagBits = ccFlagBits | OFBit;
698 //Use the regular mechanisms to calculate the other flags.
699 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
700 DestReg, psrc1, op2);
701 }
702 '''
703
704 class Srl(RegOp):
705 code = '''
706 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
707 // Because what happens to the bits shift -in- on a right shift
708 // is not defined in the C/C++ standard, we have to mask them out
709 // to be sure they're zero.
710 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
711 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
712 '''
713 flag_code = '''
714 // If the shift amount is zero, no flags should be modified.
715 if (shiftAmt) {
716 //Zero out any flags we might modify. This way we only have to
717 //worry about setting them.
718 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
719 //If some combination of the CF bits need to be set, set them.
720 if ((ext & (CFBit | ECFBit)) &&
721 shiftAmt <= dataSize * 8 &&
722 bits(SrcReg1, shiftAmt - 1)) {
723 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
724 }
725 //Figure out what the OF bit should be.
726 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
727 ccFlagBits = ccFlagBits | OFBit;
728 //Use the regular mechanisms to calculate the other flags.
729 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
730 DestReg, psrc1, op2);
731 }
732 '''
733
734 class Sra(RegOp):
735 code = '''
736 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
737 // Because what happens to the bits shift -in- on a right shift
738 // is not defined in the C/C++ standard, we have to sign extend
739 // them manually to be sure.
740 uint64_t arithMask = (shiftAmt == 0) ? 0 :
741 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
742 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
743 '''
744 flag_code = '''
745 // If the shift amount is zero, no flags should be modified.
746 if (shiftAmt) {
747 //Zero out any flags we might modify. This way we only have to
748 //worry about setting them.
749 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
750 //If some combination of the CF bits need to be set, set them.
751 uint8_t effectiveShift =
752 (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8);
753 if ((ext & (CFBit | ECFBit)) &&
754 bits(SrcReg1, effectiveShift - 1)) {
755 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
756 }
757 //Use the regular mechanisms to calculate the other flags.
758 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
759 DestReg, psrc1, op2);
760 }
761 '''
762
763 class Ror(RegOp):
764 code = '''
765 uint8_t shiftAmt =
766 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
767 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
768 if(realShiftAmt)
769 {
770 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt);
771 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt);
772 DestReg = merge(DestReg, top | bottom, dataSize);
773 }
774 else
775 DestReg = merge(DestReg, DestReg, dataSize);
776 '''
777 flag_code = '''
778 // If the shift amount is zero, no flags should be modified.
779 if (shiftAmt) {
780 //Zero out any flags we might modify. This way we only have to
781 //worry about setting them.
782 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
783 //Find the most and second most significant bits of the result.
784 int msb = bits(DestReg, dataSize * 8 - 1);
785 int smsb = bits(DestReg, dataSize * 8 - 2);
786 //If some combination of the CF bits need to be set, set them.
787 if ((ext & (CFBit | ECFBit)) && msb)
788 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
789 //Figure out what the OF bit should be.
790 if ((ext & OFBit) && (msb ^ smsb))
791 ccFlagBits = ccFlagBits | OFBit;
792 //Use the regular mechanisms to calculate the other flags.
793 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
794 DestReg, psrc1, op2);
795 }
796 '''
797
798 class Rcr(RegOp):
799 code = '''
800 uint8_t shiftAmt =
801 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
802 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
803 if(realShiftAmt)
804 {
805 CCFlagBits flags = ccFlagBits;
806 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt);
807 if (realShiftAmt > 1)
808 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1);
809 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt);
810 DestReg = merge(DestReg, top | bottom, dataSize);
811 }
812 else
813 DestReg = merge(DestReg, DestReg, dataSize);
814 '''
815 flag_code = '''
816 // If the shift amount is zero, no flags should be modified.
817 if (shiftAmt) {
818 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
819 //Zero out any flags we might modify. This way we only have to
820 //worry about setting them.
821 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
822 //Figure out what the OF bit should be.
823 if ((ext & OFBit) && (origCFBit ^
824 bits(SrcReg1, dataSize * 8 - 1))) {
825 ccFlagBits = ccFlagBits | OFBit;
826 }
827 //If some combination of the CF bits need to be set, set them.
828 if ((ext & (CFBit | ECFBit)) &&
829 (realShiftAmt == 0) ? origCFBit :
830 bits(SrcReg1, realShiftAmt - 1)) {
831 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
832 }
833 //Use the regular mechanisms to calculate the other flags.
834 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
835 DestReg, psrc1, op2);
836 }
837 '''
838
839 class Rol(RegOp):
840 code = '''
841 uint8_t shiftAmt =
842 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
843 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
844 if(realShiftAmt)
845 {
846 uint64_t top = psrc1 << realShiftAmt;
847 uint64_t bottom =
848 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt);
849 DestReg = merge(DestReg, top | bottom, dataSize);
850 }
851 else
852 DestReg = merge(DestReg, DestReg, dataSize);
853 '''
854 flag_code = '''
855 // If the shift amount is zero, no flags should be modified.
856 if (shiftAmt) {
857 //Zero out any flags we might modify. This way we only have to
858 //worry about setting them.
859 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
860 //The CF bits, if set, would be set to the lsb of the result.
861 int lsb = DestReg & 0x1;
862 int msb = bits(DestReg, dataSize * 8 - 1);
863 //If some combination of the CF bits need to be set, set them.
864 if ((ext & (CFBit | ECFBit)) && lsb)
865 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
866 //Figure out what the OF bit should be.
867 if ((ext & OFBit) && (msb ^ lsb))
868 ccFlagBits = ccFlagBits | OFBit;
869 //Use the regular mechanisms to calculate the other flags.
870 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
871 DestReg, psrc1, op2);
872 }
873 '''
874
875 class Rcl(RegOp):
876 code = '''
877 uint8_t shiftAmt =
878 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
879 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
880 if(realShiftAmt)
881 {
882 CCFlagBits flags = ccFlagBits;
883 uint64_t top = psrc1 << realShiftAmt;
884 uint64_t bottom = flags.cf << (realShiftAmt - 1);
885 if(shiftAmt > 1)
886 bottom |=
887 bits(psrc1, dataSize * 8 - 1,
888 dataSize * 8 - realShiftAmt + 1);
889 DestReg = merge(DestReg, top | bottom, dataSize);
890 }
891 else
892 DestReg = merge(DestReg, DestReg, dataSize);
893 '''
894 flag_code = '''
895 // If the shift amount is zero, no flags should be modified.
896 if (shiftAmt) {
897 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
898 //Zero out any flags we might modify. This way we only have to
899 //worry about setting them.
900 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
901 int msb = bits(DestReg, dataSize * 8 - 1);
902 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt);
903 //If some combination of the CF bits need to be set, set them.
904 if ((ext & (CFBit | ECFBit)) &&
905 (realShiftAmt == 0) ? origCFBit : CFBits)
906 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
907 //Figure out what the OF bit should be.
908 if ((ext & OFBit) && (msb ^ CFBits))
909 ccFlagBits = ccFlagBits | OFBit;
910 //Use the regular mechanisms to calculate the other flags.
911 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
912 DestReg, psrc1, op2);
913 }
914 '''
915
916 class Sld(RegOp):
917 code = '''
918 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
919 uint8_t dataBits = dataSize * 8;
920 uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
921 uint64_t result;
922 if (realShiftAmt == 0) {
923 result = psrc1;
924 } else if (realShiftAmt < dataBits) {
925 result = (psrc1 << realShiftAmt) |
926 (DoubleBits >> (dataBits - realShiftAmt));
927 } else {
928 result = (DoubleBits << (realShiftAmt - dataBits)) |
929 (psrc1 >> (2 * dataBits - realShiftAmt));
930 }
931 DestReg = merge(DestReg, result, dataSize);
932 '''
933 flag_code = '''
934 // If the shift amount is zero, no flags should be modified.
935 if (shiftAmt) {
936 //Zero out any flags we might modify. This way we only have to
937 //worry about setting them.
938 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
939 int CFBits = 0;
940 //Figure out if we -would- set the CF bits if requested.
941 if ((realShiftAmt == 0 &&
942 bits(DoubleBits, 0)) ||
943 (realShiftAmt <= dataBits &&
944 bits(SrcReg1, dataBits - realShiftAmt)) ||
945 (realShiftAmt > dataBits &&
946 bits(DoubleBits, 2 * dataBits - realShiftAmt))) {
947 CFBits = 1;
948 }
949 //If some combination of the CF bits need to be set, set them.
950 if ((ext & (CFBit | ECFBit)) && CFBits)
951 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
952 //Figure out what the OF bit should be.
953 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
954 bits(result, dataBits - 1)))
955 ccFlagBits = ccFlagBits | OFBit;
956 //Use the regular mechanisms to calculate the other flags.
957 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
958 DestReg, psrc1, op2);
959 }
960 '''
961
962 class Srd(RegOp):
963 code = '''
964 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
965 uint8_t dataBits = dataSize * 8;
966 uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
967 uint64_t result;
968 if (realShiftAmt == 0) {
969 result = psrc1;
970 } else if (realShiftAmt < dataBits) {
971 // Because what happens to the bits shift -in- on a right
972 // shift is not defined in the C/C++ standard, we have to
973 // mask them out to be sure they're zero.
974 uint64_t logicalMask = mask(dataBits - realShiftAmt);
975 result = ((psrc1 >> realShiftAmt) & logicalMask) |
976 (DoubleBits << (dataBits - realShiftAmt));
977 } else {
978 uint64_t logicalMask = mask(2 * dataBits - realShiftAmt);
979 result = ((DoubleBits >> (realShiftAmt - dataBits)) &
980 logicalMask) |
981 (psrc1 << (2 * dataBits - realShiftAmt));
982 }
983 DestReg = merge(DestReg, result, dataSize);
984 '''
985 flag_code = '''
986 // If the shift amount is zero, no flags should be modified.
987 if (shiftAmt) {
988 //Zero out any flags we might modify. This way we only have to
989 //worry about setting them.
990 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
991 int CFBits = 0;
992 //If some combination of the CF bits need to be set, set them.
993 if ((realShiftAmt == 0 &&
994 bits(DoubleBits, dataBits - 1)) ||
995 (realShiftAmt <= dataBits &&
996 bits(SrcReg1, realShiftAmt - 1)) ||
997 (realShiftAmt > dataBits &&
998 bits(DoubleBits, realShiftAmt - dataBits - 1))) {
999 CFBits = 1;
1000 }
1001 //If some combination of the CF bits need to be set, set them.
1002 if ((ext & (CFBit | ECFBit)) && CFBits)
1003 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
1004 //Figure out what the OF bit should be.
1005 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
1006 bits(result, dataBits - 1)))
1007 ccFlagBits = ccFlagBits | OFBit;
1008 //Use the regular mechanisms to calculate the other flags.
1009 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
1010 DestReg, psrc1, op2);
1011 }
1012 '''
1013
1014 class Mdb(WrRegOp):
1015 code = 'DoubleBits = psrc1 ^ op2;'
1016
1017 class Wrip(WrRegOp, CondRegOp):
1018 code = 'RIP = psrc1 + sop2 + CSBase'
1019 else_code="RIP = RIP;"
1020
1021 class Wruflags(WrRegOp):
1022 code = 'ccFlagBits = psrc1 ^ op2'
1023
1024 class Wrflags(WrRegOp):
1025 code = '''
1026 MiscReg newFlags = psrc1 ^ op2;
1027 MiscReg userFlagMask = 0xDD5;
1028 // Get only the user flags
1029 ccFlagBits = newFlags & userFlagMask;
1030 // Get everything else
1031 nccFlagBits = newFlags & ~userFlagMask;
1032 '''
1033
1034 class Rdip(RdRegOp):
1035 code = 'DestReg = RIP - CSBase'
1036
1037 class Ruflags(RdRegOp):
1038 code = 'DestReg = ccFlagBits'
1039
1040 class Rflags(RdRegOp):
1041 code = 'DestReg = ccFlagBits | nccFlagBits'
1042
1043 class Ruflag(RegOp):
1044 code = '''
1045 int flag = bits(ccFlagBits, imm8);
1046 DestReg = merge(DestReg, flag, dataSize);
1047 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1048 (ccFlagBits & ~EZFBit);
1049 '''
1050 def __init__(self, dest, imm, flags=None, \
1051 dataSize="env.dataSize"):
1052 super(Ruflag, self).__init__(dest, \
1053 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1054
1055 class Rflag(RegOp):
1056 code = '''
1057 MiscReg flagMask = 0x3F7FDD5;
1058 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
1059 int flag = bits(flags, imm8);
1060 DestReg = merge(DestReg, flag, dataSize);
1061 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1062 (ccFlagBits & ~EZFBit);
1063 '''
1064 def __init__(self, dest, imm, flags=None, \
1065 dataSize="env.dataSize"):
1066 super(Rflag, self).__init__(dest, \
1067 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1068
1069 class Sext(RegOp):
1070 code = '''
1071 IntReg val = psrc1;
1072 // Mask the bit position so that it wraps.
1073 int bitPos = op2 & (dataSize * 8 - 1);
1074 int sign_bit = bits(val, bitPos, bitPos);
1075 uint64_t maskVal = mask(bitPos+1);
1076 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1077 DestReg = merge(DestReg, val, dataSize);
1078 '''
1079 flag_code = '''
1080 if (!sign_bit)
1081 ccFlagBits = ccFlagBits &
1082 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
1083 else
1084 ccFlagBits = ccFlagBits |
1085 (ext & (CFBit | ECFBit | ZFBit | EZFBit));
1086 '''
1087
1088 class Zext(RegOp):
1089 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
1090
1091 class Rddr(RegOp):
1092 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1093 super(Rddr, self).__init__(dest, \
1094 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1095 code = '''
1096 CR4 cr4 = CR4Op;
1097 DR7 dr7 = DR7Op;
1098 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
1099 fault = new InvalidOpcode();
1100 } else if (dr7.gd) {
1101 fault = new DebugException();
1102 } else {
1103 DestReg = merge(DestReg, DebugSrc1, dataSize);
1104 }
1105 '''
1106
1107 class Wrdr(RegOp):
1108 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1109 super(Wrdr, self).__init__(dest, \
1110 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1111 code = '''
1112 CR4 cr4 = CR4Op;
1113 DR7 dr7 = DR7Op;
1114 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) {
1115 fault = new InvalidOpcode();
1116 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) &&
1117 machInst.mode.mode == LongMode) {
1118 fault = new GeneralProtection(0);
1119 } else if (dr7.gd) {
1120 fault = new DebugException();
1121 } else {
1122 DebugDest = psrc1;
1123 }
1124 '''
1125
1126 class Rdcr(RegOp):
1127 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1128 super(Rdcr, self).__init__(dest, \
1129 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1130 code = '''
1131 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
1132 fault = new InvalidOpcode();
1133 } else {
1134 DestReg = merge(DestReg, ControlSrc1, dataSize);
1135 }
1136 '''
1137
1138 class Wrcr(RegOp):
1139 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1140 super(Wrcr, self).__init__(dest, \
1141 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1142 code = '''
1143 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
1144 fault = new InvalidOpcode();
1145 } else {
1146 // There are *s in the line below so it doesn't confuse the
1147 // parser. They may be unnecessary.
1148 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize);
1149 MiscReg newVal = psrc1;
1150
1151 // Check for any modifications that would cause a fault.
1152 switch(dest) {
1153 case 0:
1154 {
1155 Efer efer = EferOp;
1156 CR0 cr0 = newVal;
1157 CR4 oldCr4 = CR4Op;
1158 if (bits(newVal, 63, 32) ||
1159 (!cr0.pe && cr0.pg) ||
1160 (!cr0.cd && cr0.nw) ||
1161 (cr0.pg && efer.lme && !oldCr4.pae))
1162 fault = new GeneralProtection(0);
1163 }
1164 break;
1165 case 2:
1166 break;
1167 case 3:
1168 break;
1169 case 4:
1170 {
1171 CR4 cr4 = newVal;
1172 // PAE can't be disabled in long mode.
1173 if (bits(newVal, 63, 11) ||
1174 (machInst.mode.mode == LongMode && !cr4.pae))
1175 fault = new GeneralProtection(0);
1176 }
1177 break;
1178 case 8:
1179 {
1180 if (bits(newVal, 63, 4))
1181 fault = new GeneralProtection(0);
1182 }
1183 default:
1184 panic("Unrecognized control register %d.\\n", dest);
1185 }
1186 ControlDest = newVal;
1187 }
1188 '''
1189
1190 # Microops for manipulating segmentation registers
1191 class SegOp(CondRegOp):
1192 abstract = True
1193 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1194 super(SegOp, self).__init__(dest, \
1195 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1196
1197 class Wrbase(SegOp):
1198 code = '''
1199 SegBaseDest = psrc1;
1200 '''
1201
1202 class Wrlimit(SegOp):
1203 code = '''
1204 SegLimitDest = psrc1;
1205 '''
1206
1207 class Wrsel(SegOp):
1208 code = '''
1209 SegSelDest = psrc1;
1210 '''
1211
1212 class WrAttr(SegOp):
1213 code = '''
1214 SegAttrDest = psrc1;
1215 '''
1216
1217 class Rdbase(SegOp):
1218 code = '''
1219 DestReg = merge(DestReg, SegBaseSrc1, dataSize);
1220 '''
1221
1222 class Rdlimit(SegOp):
1223 code = '''
1224 DestReg = merge(DestReg, SegLimitSrc1, dataSize);
1225 '''
1226
1227 class RdAttr(SegOp):
1228 code = '''
1229 DestReg = merge(DestReg, SegAttrSrc1, dataSize);
1230 '''
1231
1232 class Rdsel(SegOp):
1233 code = '''
1234 DestReg = merge(DestReg, SegSelSrc1, dataSize);
1235 '''
1236
1237 class Rdval(RegOp):
1238 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1239 super(Rdval, self).__init__(dest, src1, \
1240 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1241 code = '''
1242 DestReg = MiscRegSrc1;
1243 '''
1244
1245 class Wrval(RegOp):
1246 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1247 super(Wrval, self).__init__(dest, src1, \
1248 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1249 code = '''
1250 MiscRegDest = SrcReg1;
1251 '''
1252
1253 class Chks(RegOp):
1254 def __init__(self, dest, src1, src2=0,
1255 flags=None, dataSize="env.dataSize"):
1256 super(Chks, self).__init__(dest,
1257 src1, src2, flags, dataSize)
1258 code = '''
1259 // The selector is in source 1 and can be at most 16 bits.
1260 SegSelector selector = DestReg;
1261 SegDescriptor desc = SrcReg1;
1262 HandyM5Reg m5reg = M5Reg;
1263
1264 switch (imm8)
1265 {
1266 case SegNoCheck:
1267 break;
1268 case SegCSCheck:
1269 // Make sure it's the right type
1270 if (desc.s == 0 || desc.type.codeOrData != 1) {
1271 fault = new GeneralProtection(0);
1272 } else if (m5reg.cpl != desc.dpl) {
1273 fault = new GeneralProtection(0);
1274 }
1275 break;
1276 case SegCallGateCheck:
1277 panic("CS checks for far calls/jumps through call gates"
1278 "not implemented.\\n");
1279 break;
1280 case SegSoftIntGateCheck:
1281 // Check permissions.
1282 if (desc.dpl < m5reg.cpl) {
1283 fault = new GeneralProtection(selector);
1284 break;
1285 }
1286 // Fall through on purpose
1287 case SegIntGateCheck:
1288 // Make sure the gate's the right type.
1289 if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||
1290 ((desc.type & 0x6) != 0x6)) {
1291 fault = new GeneralProtection(0);
1292 }
1293 break;
1294 case SegSSCheck:
1295 if (selector.si || selector.ti) {
1296 if (!desc.p) {
1297 fault = new StackFault(selector);
1298 }
1299 } else {
1300 if ((m5reg.submode != SixtyFourBitMode ||
1301 m5reg.cpl == 3) ||
1302 !(desc.s == 1 &&
1303 desc.type.codeOrData == 0 && desc.type.w) ||
1304 (desc.dpl != m5reg.cpl) ||
1305 (selector.rpl != m5reg.cpl)) {
1306 fault = new GeneralProtection(selector);
1307 }
1308 }
1309 break;
1310 case SegIretCheck:
1311 {
1312 if ((!selector.si && !selector.ti) ||
1313 (selector.rpl < m5reg.cpl) ||
1314 !(desc.s == 1 && desc.type.codeOrData == 1) ||
1315 (!desc.type.c && desc.dpl != selector.rpl) ||
1316 (desc.type.c && desc.dpl > selector.rpl)) {
1317 fault = new GeneralProtection(selector);
1318 } else if (!desc.p) {
1319 fault = new SegmentNotPresent(selector);
1320 }
1321 break;
1322 }
1323 case SegIntCSCheck:
1324 if (m5reg.mode == LongMode) {
1325 if (desc.l != 1 || desc.d != 0) {
1326 fault = new GeneralProtection(selector);
1327 }
1328 } else {
1329 panic("Interrupt CS checks not implemented "
1330 "in legacy mode.\\n");
1331 }
1332 break;
1333 case SegTRCheck:
1334 if (!selector.si || selector.ti) {
1335 fault = new GeneralProtection(selector);
1336 }
1337 break;
1338 case SegTSSCheck:
1339 if (!desc.p) {
1340 fault = new SegmentNotPresent(selector);
1341 } else if (!(desc.type == 0x9 ||
1342 (desc.type == 1 &&
1343 m5reg.mode != LongMode))) {
1344 fault = new GeneralProtection(selector);
1345 }
1346 break;
1347 case SegInGDTCheck:
1348 if (selector.ti) {
1349 fault = new GeneralProtection(selector);
1350 }
1351 break;
1352 case SegLDTCheck:
1353 if (!desc.p) {
1354 fault = new SegmentNotPresent(selector);
1355 } else if (desc.type != 0x2) {
1356 fault = new GeneralProtection(selector);
1357 }
1358 break;
1359 default:
1360 panic("Undefined segment check type.\\n");
1361 }
1362 '''
1363 flag_code = '''
1364 // Check for a NULL selector and set ZF,EZF appropriately.
1365 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit));
1366 if (!selector.si && !selector.ti)
1367 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit));
1368 '''
1369
1370 class Wrdh(RegOp):
1371 code = '''
1372 SegDescriptor desc = SrcReg1;
1373
1374 uint64_t target = bits(SrcReg2, 31, 0) << 32;
1375 switch(desc.type) {
1376 case LDT64:
1377 case AvailableTSS64:
1378 case BusyTSS64:
1379 replaceBits(target, 23, 0, desc.baseLow);
1380 replaceBits(target, 31, 24, desc.baseHigh);
1381 break;
1382 case CallGate64:
1383 case IntGate64:
1384 case TrapGate64:
1385 replaceBits(target, 15, 0, bits(desc, 15, 0));
1386 replaceBits(target, 31, 16, bits(desc, 63, 48));
1387 break;
1388 default:
1389 panic("Wrdh used with wrong descriptor type!\\n");
1390 }
1391 DestReg = target;
1392 '''
1393
1394 class Wrtsc(WrRegOp):
1395 code = '''
1396 TscOp = psrc1;
1397 '''
1398
1399 class Rdtsc(RdRegOp):
1400 code = '''
1401 DestReg = TscOp;
1402 '''
1403
1404 class Rdm5reg(RdRegOp):
1405 code = '''
1406 DestReg = M5Reg;
1407 '''
1408
1409 class Wrdl(RegOp):
1410 code = '''
1411 SegDescriptor desc = SrcReg1;
1412 SegSelector selector = SrcReg2;
1413 if (selector.si || selector.ti) {
1414 if (!desc.p)
1415 panic("Segment not present.\\n");
1416 SegAttr attr = 0;
1417 attr.dpl = desc.dpl;
1418 attr.unusable = 0;
1419 attr.defaultSize = desc.d;
1420 attr.longMode = desc.l;
1421 attr.avl = desc.avl;
1422 attr.granularity = desc.g;
1423 attr.present = desc.p;
1424 attr.system = desc.s;
1425 attr.type = desc.type;
1426 if (!desc.s) {
1427 // The expand down bit happens to be set for gates.
1428 if (desc.type.e) {
1429 panic("Gate descriptor encountered.\\n");
1430 }
1431 attr.readable = 1;
1432 attr.writable = 1;
1433 attr.expandDown = 0;
1434 } else {
1435 if (desc.type.codeOrData) {
1436 attr.expandDown = 0;
1437 attr.readable = desc.type.r;
1438 attr.writable = 0;
1439 } else {
1440 attr.expandDown = desc.type.e;
1441 attr.readable = 1;
1442 attr.writable = desc.type.w;
1443 }
1444 }
1445 Addr base = desc.baseLow | (desc.baseHigh << 24);
1446 Addr limit = desc.limitLow | (desc.limitHigh << 16);
1447 if (desc.g)
1448 limit = (limit << 12) | mask(12);
1449 SegBaseDest = base;
1450 SegLimitDest = limit;
1451 SegAttrDest = attr;
1452 } else {
1453 SegBaseDest = SegBaseDest;
1454 SegLimitDest = SegLimitDest;
1455 SegAttrDest = SegAttrDest;
1456 }
1457 '''
1458}};