1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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219 MicroRegOpImmExecute)
220
221 regTemplates = (
222 MicroRegOpDeclare,
223 MicroRegOpConstructor,
224 MicroRegOpExecute)
225
226 class RegOpMeta(type):
227 def buildCppClasses(self, name, Name, suffix, \
228 code, flag_code, cond_check, else_code, cond_control_flag_init):
229
230 # Globals to stick the output in
231 global header_output
232 global decoder_output
233 global exec_output
234
235 # Stick all the code together so it can be searched at once
236 allCode = "|".join((code, flag_code, cond_check, else_code,
237 cond_control_flag_init))
238
239 # If op2 is used anywhere, make register and immediate versions
240 # of this code.
241 matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?")
242 match = matcher.search(allCode)
243 if match:
244 typeQual = ""
245 if match.group("typeQual"):
246 typeQual = match.group("typeQual")
247 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
248 self.buildCppClasses(name, Name, suffix,
249 matcher.sub(src2_name, code),
250 matcher.sub(src2_name, flag_code),
251 matcher.sub(src2_name, cond_check),
252 matcher.sub(src2_name, else_code),
253 matcher.sub(src2_name, cond_control_flag_init))
254 imm_name = "%simm8" % match.group("prefix")
255 self.buildCppClasses(name + "i", Name, suffix + "Imm",
256 matcher.sub(imm_name, code),
257 matcher.sub(imm_name, flag_code),
258 matcher.sub(imm_name, cond_check),
259 matcher.sub(imm_name, else_code),
260 matcher.sub(imm_name, cond_control_flag_init))
261 return
262
263 # If there's something optional to do with flags, generate
264 # a version without it and fix up this version to use it.
265 if flag_code != "" or cond_check != "true":
266 self.buildCppClasses(name, Name, suffix,
267 code, "", "true", else_code, "")
268 suffix = "Flags" + suffix
269
270 # If psrc1 or psrc2 is used, we need to actually insert code to
271 # compute it.
272 matcher = re.compile("(?<!\w)psrc1(?!\w)")
273 if matcher.search(allCode):
274 code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code
275 matcher = re.compile("(?<!\w)psrc2(?!\w)")
276 if matcher.search(allCode):
277 code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code
278 # Also make available versions which do sign extension
279 matcher = re.compile("(?<!\w)spsrc1(?!\w)")
280 if matcher.search(allCode):
281 code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code
282 matcher = re.compile("(?<!\w)spsrc2(?!\w)")
283 if matcher.search(allCode):
284 code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
285 matcher = re.compile("(?<!\w)simm8(?!\w)")
286 if matcher.search(allCode):
287 code = "int8_t simm8 = imm8;" + code
288
289 base = "X86ISA::RegOp"
290
291 # If imm8 shows up in the code, use the immediate templates, if
292 # not, hopefully the register ones will be correct.
293 templates = regTemplates
294 matcher = re.compile("(?<!\w)s?imm8(?!\w)")
295 if matcher.search(allCode):
296 base += "Imm"
297 templates = immTemplates
298
299 # Get everything ready for the substitution
300 iop = InstObjParams(name, Name + suffix, base,
301 {"code" : code,
302 "flag_code" : flag_code,
303 "cond_check" : cond_check,
304 "else_code" : else_code,
305 "cond_control_flag_init": cond_control_flag_init})
306
307 # Generate the actual code (finally!)
308 header_output += templates[0].subst(iop)
309 decoder_output += templates[1].subst(iop)
310 exec_output += templates[2].subst(iop)
311
312
313 def __new__(mcls, Name, bases, dict):
314 abstract = False
315 name = Name.lower()
316 if "abstract" in dict:
317 abstract = dict['abstract']
318 del dict['abstract']
319
320 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
321 if not abstract:
322 cls.className = Name
323 cls.base_mnemonic = name
324 code = cls.code
325 flag_code = cls.flag_code
326 cond_check = cls.cond_check
327 else_code = cls.else_code
328 cond_control_flag_init = cls.cond_control_flag_init
329
330 # Set up the C++ classes
331 mcls.buildCppClasses(cls, name, Name, "", code, flag_code,
332 cond_check, else_code, cond_control_flag_init)
333
334 # Hook into the microassembler dict
335 global microopClasses
336 microopClasses[name] = cls
337
338 allCode = "|".join((code, flag_code, cond_check, else_code,
339 cond_control_flag_init))
340

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347
348
349 class RegOp(X86Microop):
350 __metaclass__ = RegOpMeta
351 # This class itself doesn't act as a microop
352 abstract = True
353
354 # Default template parameter values
355 flag_code = ""
356 cond_check = "true"
357 else_code = ";"
358 cond_control_flag_init = ""
359
360 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
361 self.dest = dest
362 self.src1 = src1

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367 self.ext = 0
368 else:
369 if not isinstance(flags, (list, tuple)):
370 raise Exception, "flags must be a list or tuple of flags"
371 self.ext = " | ".join(flags)
372 self.className += "Flags"
373
374 def getAllocator(self, microFlags):
375 className = self.className
376 if self.mnemonic == self.base_mnemonic + 'i':
377 className += "Imm"
378 allocator = '''new %(class_name)s(machInst, macrocodeBlock,
379 %(flags)s, %(src1)s, %(op2)s, %(dest)s,
380 %(dataSize)s, %(ext)s)''' % {
381 "class_name" : className,
382 "flags" : self.microFlagsText(microFlags),
383 "src1" : self.src1, "op2" : self.op2,
384 "dest" : self.dest,
385 "dataSize" : self.dataSize,
386 "ext" : self.ext}
387 return allocator
388
389 class LogicRegOp(RegOp):
390 abstract = True
391 flag_code = '''
392 //Don't have genFlags handle the OF or CF bits
393 uint64_t mask = CFBit | ECFBit | OFBit;
394 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
395 //If a logic microop wants to set these, it wants to set them to 0.

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424 class WrRegOp(RegOp):
425 abstract = True
426 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
427 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
428 src1, src2, flags, dataSize)
429
430 class Add(FlagRegOp):
431 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
432
433 class Or(LogicRegOp):
434 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
435
436 class Adc(FlagRegOp):
437 code = '''
438 CCFlagBits flags = ccFlagBits;
439 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
440 '''
441
442 class Sbb(SubRegOp):
443 code = '''
444 CCFlagBits flags = ccFlagBits;
445 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
446 '''
447
448 class And(LogicRegOp):
449 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
450
451 class Sub(SubRegOp):
452 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
453
454 class Xor(LogicRegOp):
455 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
456
457 class Mul1s(WrRegOp):
458 code = '''
459 ProdLow = psrc1 * op2;
460 int halfSize = (dataSize * 8) / 2;
461 uint64_t shifter = (ULL(1) << halfSize);
462 uint64_t hiResult;
463 uint64_t psrc1_h = psrc1 / shifter;

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500 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
501 } else {
502 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
503 }
504 '''
505
506 class Mulel(RdRegOp):
507 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
508
509 class Muleh(RdRegOp):
510 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
511 if not src1:
512 src1 = dest
513 super(RdRegOp, self).__init__(dest, src1, \
514 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
515 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
516
517 # One or two bit divide
518 class Div1(WrRegOp):
519 code = '''
520 //These are temporaries so that modifying them later won't make
521 //the ISA parser think they're also sources.
522 uint64_t quotient = 0;
523 uint64_t remainder = psrc1;

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535 Remainder = remainder;
536 Quotient = quotient;
537 Divisor = divisor;
538 }
539 '''
540
541 # Step divide
542 class Div2(RegOp):
543 code = '''
544 uint64_t dividend = Remainder;
545 uint64_t divisor = Divisor;
546 uint64_t quotient = Quotient;
547 uint64_t remainder = dividend;
548 int remaining = op2;
549 //If we overshot, do nothing. This lets us unrool division loops a
550 //little.
551 if (divisor == 0) {

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582 remaining--;
583 }
584 remainder = dividend;
585 //Do the division.
586 divide(dividend, divisor, quotient, remainder);
587 }
588 }
589 //Keep track of how many bits there are still to pull in.
590 DestReg = merge(DestReg, remaining, dataSize);
591 //Record the final results
592 Remainder = remainder;
593 Quotient = quotient;
594 '''
595 flag_code = '''
596 if (remaining == 0)
597 ccFlagBits = ccFlagBits | (ext & EZFBit);
598 else
599 ccFlagBits = ccFlagBits & ~(ext & EZFBit);
600 '''
601
602 class Divq(RdRegOp):
603 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
604
605 class Divr(RdRegOp):
606 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
607
608 class Mov(CondRegOp):
609 code = 'DestReg = merge(SrcReg1, op2, dataSize)'
610 else_code = 'DestReg = DestReg;'
611
612 # Shift instructions
613
614 class Sll(RegOp):
615 code = '''
616 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
617 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
618 '''
619 flag_code = '''
620 // If the shift amount is zero, no flags should be modified.
621 if (shiftAmt) {
622 //Zero out any flags we might modify. This way we only have to
623 //worry about setting them.
624 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
625 int CFBits = 0;
626 //Figure out if we -would- set the CF bits if requested.

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636 ccFlagBits = ccFlagBits | OFBit;
637 //Use the regular mechanisms to calculate the other flags.
638 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
639 DestReg, psrc1, op2);
640 }
641 '''
642
643 class Srl(RegOp):
644 code = '''
645 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
646 // Because what happens to the bits shift -in- on a right shift
647 // is not defined in the C/C++ standard, we have to mask them out
648 // to be sure they're zero.
649 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
650 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
651 '''
652 flag_code = '''
653 // If the shift amount is zero, no flags should be modified.
654 if (shiftAmt) {
655 //Zero out any flags we might modify. This way we only have to
656 //worry about setting them.
657 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
658 //If some combination of the CF bits need to be set, set them.
659 if ((ext & (CFBit | ECFBit)) &&

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666 ccFlagBits = ccFlagBits | OFBit;
667 //Use the regular mechanisms to calculate the other flags.
668 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
669 DestReg, psrc1, op2);
670 }
671 '''
672
673 class Sra(RegOp):
674 code = '''
675 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
676 // Because what happens to the bits shift -in- on a right shift
677 // is not defined in the C/C++ standard, we have to sign extend
678 // them manually to be sure.
679 uint64_t arithMask = (shiftAmt == 0) ? 0 :
680 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
681 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
682 '''
683 flag_code = '''
684 // If the shift amount is zero, no flags should be modified.
685 if (shiftAmt) {
686 //Zero out any flags we might modify. This way we only have to
687 //worry about setting them.
688 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
689 //If some combination of the CF bits need to be set, set them.
690 uint8_t effectiveShift =

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699 }
700 '''
701
702 class Ror(RegOp):
703 code = '''
704 uint8_t shiftAmt =
705 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
706 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
707 if(realShiftAmt)
708 {
709 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt);
710 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt);
711 DestReg = merge(DestReg, top | bottom, dataSize);
712 }
713 else
714 DestReg = merge(DestReg, DestReg, dataSize);
715 '''
716 flag_code = '''
717 // If the shift amount is zero, no flags should be modified.
718 if (shiftAmt) {
719 //Zero out any flags we might modify. This way we only have to
720 //worry about setting them.
721 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));

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734 }
735 '''
736
737 class Rcr(RegOp):
738 code = '''
739 uint8_t shiftAmt =
740 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
741 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
742 if(realShiftAmt)
743 {
744 CCFlagBits flags = ccFlagBits;
745 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt);
746 if (realShiftAmt > 1)
747 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1);
748 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt);
749 DestReg = merge(DestReg, top | bottom, dataSize);
750 }
751 else
752 DestReg = merge(DestReg, DestReg, dataSize);
753 '''
754 flag_code = '''
755 // If the shift amount is zero, no flags should be modified.
756 if (shiftAmt) {
757 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
758 //Zero out any flags we might modify. This way we only have to
759 //worry about setting them.

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775 }
776 '''
777
778 class Rol(RegOp):
779 code = '''
780 uint8_t shiftAmt =
781 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
782 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
783 if(realShiftAmt)
784 {
785 uint64_t top = psrc1 << realShiftAmt;
786 uint64_t bottom =
787 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt);
788 DestReg = merge(DestReg, top | bottom, dataSize);
789 }
790 else
791 DestReg = merge(DestReg, DestReg, dataSize);
792 '''
793 flag_code = '''
794 // If the shift amount is zero, no flags should be modified.
795 if (shiftAmt) {
796 //Zero out any flags we might modify. This way we only have to
797 //worry about setting them.
798 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));

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811 }
812 '''
813
814 class Rcl(RegOp):
815 code = '''
816 uint8_t shiftAmt =
817 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
818 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
819 if(realShiftAmt)
820 {
821 CCFlagBits flags = ccFlagBits;
822 uint64_t top = psrc1 << realShiftAmt;
823 uint64_t bottom = flags.cf << (realShiftAmt - 1);
824 if(shiftAmt > 1)
825 bottom |=
826 bits(psrc1, dataSize * 8 - 1,
827 dataSize * 8 - realShiftAmt + 1);
828 DestReg = merge(DestReg, top | bottom, dataSize);
829 }
830 else
831 DestReg = merge(DestReg, DestReg, dataSize);
832 '''
833 flag_code = '''
834 // If the shift amount is zero, no flags should be modified.
835 if (shiftAmt) {
836 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
837 //Zero out any flags we might modify. This way we only have to
838 //worry about setting them.

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848 ccFlagBits = ccFlagBits | OFBit;
849 //Use the regular mechanisms to calculate the other flags.
850 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
851 DestReg, psrc1, op2);
852 }
853 '''
854
855 class Sld(RegOp):
856 code = '''
857 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
858 uint8_t dataBits = dataSize * 8;
859 uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
860 uint64_t result;
861 if (realShiftAmt == 0) {
862 result = psrc1;
863 } else if (realShiftAmt < dataBits) {
864 result = (psrc1 << realShiftAmt) |
865 (DoubleBits >> (dataBits - realShiftAmt));
866 } else {
867 result = (DoubleBits << (realShiftAmt - dataBits)) |
868 (psrc1 >> (2 * dataBits - realShiftAmt));
869 }
870 DestReg = merge(DestReg, result, dataSize);
871 '''
872 flag_code = '''
873 // If the shift amount is zero, no flags should be modified.
874 if (shiftAmt) {
875 //Zero out any flags we might modify. This way we only have to
876 //worry about setting them.
877 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
878 int CFBits = 0;
879 //Figure out if we -would- set the CF bits if requested.

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894 ccFlagBits = ccFlagBits | OFBit;
895 //Use the regular mechanisms to calculate the other flags.
896 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
897 DestReg, psrc1, op2);
898 }
899 '''
900
901 class Srd(RegOp):
902 code = '''
903 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
904 uint8_t dataBits = dataSize * 8;
905 uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
906 uint64_t result;
907 if (realShiftAmt == 0) {
908 result = psrc1;
909 } else if (realShiftAmt < dataBits) {
910 // Because what happens to the bits shift -in- on a right
911 // shift is not defined in the C/C++ standard, we have to
912 // mask them out to be sure they're zero.
913 uint64_t logicalMask = mask(dataBits - realShiftAmt);
914 result = ((psrc1 >> realShiftAmt) & logicalMask) |
915 (DoubleBits << (dataBits - realShiftAmt));
916 } else {
917 uint64_t logicalMask = mask(2 * dataBits - realShiftAmt);
918 result = ((DoubleBits >> (realShiftAmt - dataBits)) &
919 logicalMask) |
920 (psrc1 << (2 * dataBits - realShiftAmt));
921 }
922 DestReg = merge(DestReg, result, dataSize);
923 '''
924 flag_code = '''
925 // If the shift amount is zero, no flags should be modified.
926 if (shiftAmt) {
927 //Zero out any flags we might modify. This way we only have to
928 //worry about setting them.
929 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
930 int CFBits = 0;
931 //If some combination of the CF bits need to be set, set them.

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981
982 class Ruflag(RegOp):
983 code = '''
984 int flag = bits(ccFlagBits, imm8);
985 DestReg = merge(DestReg, flag, dataSize);
986 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
987 (ccFlagBits & ~EZFBit);
988 '''
989 def __init__(self, dest, imm, flags=None, \
990 dataSize="env.dataSize"):
991 super(Ruflag, self).__init__(dest, \
992 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
993
994 class Rflag(RegOp):
995 code = '''
996 MiscReg flagMask = 0x3F7FDD5;
997 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
998 int flag = bits(flags, imm8);
999 DestReg = merge(DestReg, flag, dataSize);
1000 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1001 (ccFlagBits & ~EZFBit);
1002 '''
1003 def __init__(self, dest, imm, flags=None, \
1004 dataSize="env.dataSize"):
1005 super(Rflag, self).__init__(dest, \
1006 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1007
1008 class Sext(RegOp):
1009 code = '''
1010 IntReg val = psrc1;
1011 // Mask the bit position so that it wraps.
1012 int bitPos = op2 & (dataSize * 8 - 1);
1013 int sign_bit = bits(val, bitPos, bitPos);
1014 uint64_t maskVal = mask(bitPos+1);
1015 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1016 DestReg = merge(DestReg, val, dataSize);
1017 '''
1018 flag_code = '''
1019 if (!sign_bit)
1020 ccFlagBits = ccFlagBits &
1021 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
1022 else
1023 ccFlagBits = ccFlagBits |
1024 (ext & (CFBit | ECFBit | ZFBit | EZFBit));
1025 '''
1026
1027 class Zext(RegOp):
1028 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
1029
1030 class Rddr(RegOp):
1031 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1032 super(Rddr, self).__init__(dest, \
1033 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1034 code = '''
1035 CR4 cr4 = CR4Op;
1036 DR7 dr7 = DR7Op;
1037 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
1038 fault = new InvalidOpcode();
1039 } else if (dr7.gd) {
1040 fault = new DebugException();
1041 } else {
1042 DestReg = merge(DestReg, DebugSrc1, dataSize);
1043 }
1044 '''
1045
1046 class Wrdr(RegOp):
1047 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1048 super(Wrdr, self).__init__(dest, \
1049 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1050 code = '''
1051 CR4 cr4 = CR4Op;
1052 DR7 dr7 = DR7Op;

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1061 DebugDest = psrc1;
1062 }
1063 '''
1064
1065 class Rdcr(RegOp):
1066 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1067 super(Rdcr, self).__init__(dest, \
1068 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1069 code = '''
1070 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
1071 fault = new InvalidOpcode();
1072 } else {
1073 DestReg = merge(DestReg, ControlSrc1, dataSize);
1074 }
1075 '''
1076
1077 class Wrcr(RegOp):
1078 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1079 super(Wrcr, self).__init__(dest, \
1080 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1081 code = '''
1082 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
1083 fault = new InvalidOpcode();

--- 65 unchanged lines hidden (view full) ---

1149 '''
1150
1151 class WrAttr(SegOp):
1152 code = '''
1153 SegAttrDest = psrc1;
1154 '''
1155
1156 class Rdbase(SegOp):
1157 code = '''
1158 DestReg = merge(DestReg, SegBaseSrc1, dataSize);
1159 '''
1160
1161 class Rdlimit(SegOp):
1162 code = '''
1163 DestReg = merge(DestReg, SegLimitSrc1, dataSize);
1164 '''
1165
1166 class RdAttr(SegOp):
1167 code = '''
1168 DestReg = merge(DestReg, SegAttrSrc1, dataSize);
1169 '''
1170
1171 class Rdsel(SegOp):
1172 code = '''
1173 DestReg = merge(DestReg, SegSelSrc1, dataSize);
1174 '''
1175
1176 class Rdval(RegOp):
1177 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1178 super(Rdval, self).__init__(dest, src1, \
1179 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1180 code = '''
1181 DestReg = MiscRegSrc1;
1182 '''

--- 215 unchanged lines hidden ---