1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

--- 217 unchanged lines hidden (view full) ---

226 self.dest = dest
227 self.src1 = src1
228 self.src2 = src2
229 self.setStatus = False
230 self.dataSize = 1
231 self.ext = 0
232
233 def getAllocator(self, *microFlags):
234 allocator = '''new %(class_name)s(machInst, %(mnemonic)s,
235 %(flags)s %(src1)s, %(src2)s, %(dest)s,
236 %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
237 "class_name" : self.className,
238 "mnemonic" : self.mnemonic,
239 "flags" : self.microFlagsText(microFlags),
240 "src1" : self.src1, "src2" : self.src2,
241 "dest" : self.dest,
242 "setStatus" : self.setStatus,
243 "dataSize" : self.dataSize,
244 "ext" : self.ext}
245
246 class RegOpImm(X86Microop):
247 def __init__(self, dest, src1, imm):
248 self.dest = dest
249 self.src1 = src1
250 self.imm = imm
251 self.setStatus = False
252 self.dataSize = 1
253 self.ext = 0
254
255 def getAllocator(self, *microFlags):
256 allocator = '''new %(class_name)s(machInst, %(mnemonic)s,
257 %(flags)s %(src1)s, %(imm8)s, %(dest)s,
258 %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
259 "class_name" : self.className,
260 "mnemonic" : self.mnemonic,
261 "flags" : self.microFlagsText(microFlags),
262 "src1" : self.src1, "imm8" : self.imm8,
263 "dest" : self.dest,
264 "setStatus" : self.setStatus,
265 "dataSize" : self.dataSize,
266 "ext" : self.ext}
267}};
268
269let {{
270
271 # Make these empty strings so that concatenating onto
272 # them will always work.
273 header_output = ""
274 decoder_output = ""

--- 10 unchanged lines hidden (view full) ---

285 # Find op2 in each of the instruction definitions. Create two versions
286 # of the code, one with an integer operand, and one with an immediate
287 # operand.
288 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
289 regCode = matcher.sub("SrcReg2", code)
290 immCode = matcher.sub("imm8", code)
291
292 # Build up the all register version of this micro op
293 iop = InstObjParams(name, Name, 'X86MicroOpBase', {"code" : regCode})
294 header_output += MicroRegOpDeclare.subst(iop)
295 decoder_output += MicroRegOpConstructor.subst(iop)
296 exec_output += MicroRegOpExecute.subst(iop)
297
298 class RegOpChild(RegOp):
299 def __init__(self, dest, src1, src2):
300 super(RegOpChild, self).__init__(dest, src1, src2)
301 self.className = Name
302 self.mnemonic = name
303
304 microopClasses[name] = RegOpChild
305
306 # Build up the immediate version of this micro op
307 iop = InstObjParams(name + "i", Name,
308 'X86MicroOpBase', {"code" : immCode})
309 header_output += MicroRegOpImmDeclare.subst(iop)
310 decoder_output += MicroRegOpImmConstructor.subst(iop)
311 exec_output += MicroRegOpImmExecute.subst(iop)
312
313 class RegOpImmChild(RegOpImm):
314 def __init__(self, dest, src1, imm):
315 super(RegOpImmChild, self).__init__(dest, src1, imm)
316 self.className = Name + "Imm"

--- 15 unchanged lines hidden ---