mediaop.isa (12707:7819f067a128) | mediaop.isa (13611:c8b7847b4171) |
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1// Copyright (c) 2009 The Regents of The University of Michigan 2// Copyright (c) 2015 Advanced Micro Devices, Inc. 3// 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 231 unchanged lines hidden (view full) --- 240 241 class Mov2int(MediaOp): 242 def __init__(self, dest, src1, src2 = 0, \ 243 size = None, destSize = None, srcSize = None, ext = None): 244 super(Mov2int, self).__init__(dest, src1,\ 245 src2, size, destSize, srcSize, ext) 246 op_class = 'SimdMiscOp' 247 code = ''' | 1// Copyright (c) 2009 The Regents of The University of Michigan 2// Copyright (c) 2015 Advanced Micro Devices, Inc. 3// 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 231 unchanged lines hidden (view full) --- 240 241 class Mov2int(MediaOp): 242 def __init__(self, dest, src1, src2 = 0, \ 243 size = None, destSize = None, srcSize = None, ext = None): 244 super(Mov2int, self).__init__(dest, src1,\ 245 src2, size, destSize, srcSize, ext) 246 op_class = 'SimdMiscOp' 247 code = ''' |
248 int items = sizeof(FloatRegBits) / srcSize; | 248 int items = sizeof(FloatReg) / srcSize; |
249 int offset = imm8; 250 if (bits(src1, 0) && (ext & 0x1)) 251 offset -= items; 252 if (offset >= 0 && offset < items) { 253 uint64_t fpSrcReg1 = 254 bits(FpSrcReg1_uqw, 255 (offset + 1) * srcSize * 8 - 1, 256 (offset + 0) * srcSize * 8); --- 5 unchanged lines hidden (view full) --- 262 263 class Mov2fp(MediaOp): 264 def __init__(self, dest, src1, src2 = 0, \ 265 size = None, destSize = None, srcSize = None, ext = None): 266 super(Mov2fp, self).__init__(dest, src1,\ 267 src2, size, destSize, srcSize, ext) 268 op_class = 'SimdMiscOp' 269 code = ''' | 249 int offset = imm8; 250 if (bits(src1, 0) && (ext & 0x1)) 251 offset -= items; 252 if (offset >= 0 && offset < items) { 253 uint64_t fpSrcReg1 = 254 bits(FpSrcReg1_uqw, 255 (offset + 1) * srcSize * 8 - 1, 256 (offset + 0) * srcSize * 8); --- 5 unchanged lines hidden (view full) --- 262 263 class Mov2fp(MediaOp): 264 def __init__(self, dest, src1, src2 = 0, \ 265 size = None, destSize = None, srcSize = None, ext = None): 266 super(Mov2fp, self).__init__(dest, src1,\ 267 src2, size, destSize, srcSize, ext) 268 op_class = 'SimdMiscOp' 269 code = ''' |
270 int items = sizeof(FloatRegBits) / destSize; | 270 int items = sizeof(FloatReg) / destSize; |
271 int offset = imm8; 272 if (bits(dest, 0) && (ext & 0x1)) 273 offset -= items; 274 if (offset >= 0 && offset < items) { 275 uint64_t srcReg1 = pick(SrcReg1, 0, srcSize); 276 FpDestReg_uqw = 277 insertBits(FpDestReg_uqw, 278 (offset + 1) * destSize * 8 - 1, --- 5 unchanged lines hidden (view full) --- 284 285 class Movsign(MediaOp): 286 def __init__(self, dest, src, \ 287 size = None, destSize = None, srcSize = None, ext = None): 288 super(Movsign, self).__init__(dest, src,\ 289 "InstRegIndex(0)", size, destSize, srcSize, ext) 290 op_class = 'SimdMiscOp' 291 code = ''' | 271 int offset = imm8; 272 if (bits(dest, 0) && (ext & 0x1)) 273 offset -= items; 274 if (offset >= 0 && offset < items) { 275 uint64_t srcReg1 = pick(SrcReg1, 0, srcSize); 276 FpDestReg_uqw = 277 insertBits(FpDestReg_uqw, 278 (offset + 1) * destSize * 8 - 1, --- 5 unchanged lines hidden (view full) --- 284 285 class Movsign(MediaOp): 286 def __init__(self, dest, src, \ 287 size = None, destSize = None, srcSize = None, ext = None): 288 super(Movsign, self).__init__(dest, src,\ 289 "InstRegIndex(0)", size, destSize, srcSize, ext) 290 op_class = 'SimdMiscOp' 291 code = ''' |
292 int items = sizeof(FloatRegBits) / srcSize; | 292 int items = sizeof(FloatReg) / srcSize; |
293 uint64_t result = 0; 294 int offset = (ext & 0x1) ? items : 0; 295 for (int i = 0; i < items; i++) { 296 uint64_t picked = 297 bits(FpSrcReg1_uqw, (i + 1) * 8 * srcSize - 1); 298 result = insertBits(result, i + offset, i + offset, picked); 299 } 300 DestReg = DestReg | result; --- 19 unchanged lines hidden (view full) --- 320 ''' 321 322 class shuffle(MediaOp): 323 op_class = 'SimdMiscOp' 324 code = ''' 325 assert(srcSize == destSize); 326 int size = srcSize; 327 int sizeBits = size * 8; | 293 uint64_t result = 0; 294 int offset = (ext & 0x1) ? items : 0; 295 for (int i = 0; i < items; i++) { 296 uint64_t picked = 297 bits(FpSrcReg1_uqw, (i + 1) * 8 * srcSize - 1); 298 result = insertBits(result, i + offset, i + offset, picked); 299 } 300 DestReg = DestReg | result; --- 19 unchanged lines hidden (view full) --- 320 ''' 321 322 class shuffle(MediaOp): 323 op_class = 'SimdMiscOp' 324 code = ''' 325 assert(srcSize == destSize); 326 int size = srcSize; 327 int sizeBits = size * 8; |
328 int items = sizeof(FloatRegBits) / size; | 328 int items = sizeof(FloatReg) / size; |
329 int options; 330 int optionBits; 331 if (size == 8) { 332 options = 2; 333 optionBits = 1; 334 } else { 335 options = 4; 336 optionBits = 2; 337 } 338 339 uint64_t result = 0; 340 uint8_t sel = ext; 341 342 for (int i = 0; i < items; i++) { 343 uint64_t resBits; 344 uint8_t lsel = sel & mask(optionBits); | 329 int options; 330 int optionBits; 331 if (size == 8) { 332 options = 2; 333 optionBits = 1; 334 } else { 335 options = 4; 336 optionBits = 2; 337 } 338 339 uint64_t result = 0; 340 uint8_t sel = ext; 341 342 for (int i = 0; i < items; i++) { 343 uint64_t resBits; 344 uint8_t lsel = sel & mask(optionBits); |
345 if (lsel * size >= sizeof(FloatRegBits)) { | 345 if (lsel * size >= sizeof(FloatReg)) { |
346 lsel -= options / 2; 347 resBits = bits(FpSrcReg2_uqw, 348 (lsel + 1) * sizeBits - 1, 349 (lsel + 0) * sizeBits); 350 } else { 351 resBits = bits(FpSrcReg1_uqw, 352 (lsel + 1) * sizeBits - 1, 353 (lsel + 0) * sizeBits); --- 8 unchanged lines hidden (view full) --- 362 FpDestReg_uqw = result; 363 ''' 364 365 class Unpack(MediaOp): 366 op_class = 'SimdMiscOp' 367 code = ''' 368 assert(srcSize == destSize); 369 int size = destSize; | 346 lsel -= options / 2; 347 resBits = bits(FpSrcReg2_uqw, 348 (lsel + 1) * sizeBits - 1, 349 (lsel + 0) * sizeBits); 350 } else { 351 resBits = bits(FpSrcReg1_uqw, 352 (lsel + 1) * sizeBits - 1, 353 (lsel + 0) * sizeBits); --- 8 unchanged lines hidden (view full) --- 362 FpDestReg_uqw = result; 363 ''' 364 365 class Unpack(MediaOp): 366 op_class = 'SimdMiscOp' 367 code = ''' 368 assert(srcSize == destSize); 369 int size = destSize; |
370 int items = (sizeof(FloatRegBits) / size) / 2; | 370 int items = (sizeof(FloatReg) / size) / 2; |
371 int offset = ext ? items : 0; 372 uint64_t result = 0; 373 for (int i = 0; i < items; i++) { 374 uint64_t pickedLow = 375 bits(FpSrcReg1_uqw, (i + offset + 1) * 8 * size - 1, 376 (i + offset) * 8 * size); 377 result = insertBits(result, 378 (2 * i + 1) * 8 * size - 1, --- 9 unchanged lines hidden (view full) --- 388 } 389 FpDestReg_uqw = result; 390 ''' 391 392 class Pack(MediaOp): 393 op_class = 'SimdMiscOp' 394 code = ''' 395 assert(srcSize == destSize * 2); | 371 int offset = ext ? items : 0; 372 uint64_t result = 0; 373 for (int i = 0; i < items; i++) { 374 uint64_t pickedLow = 375 bits(FpSrcReg1_uqw, (i + offset + 1) * 8 * size - 1, 376 (i + offset) * 8 * size); 377 result = insertBits(result, 378 (2 * i + 1) * 8 * size - 1, --- 9 unchanged lines hidden (view full) --- 388 } 389 FpDestReg_uqw = result; 390 ''' 391 392 class Pack(MediaOp): 393 op_class = 'SimdMiscOp' 394 code = ''' 395 assert(srcSize == destSize * 2); |
396 int items = (sizeof(FloatRegBits) / destSize); | 396 int items = (sizeof(FloatReg) / destSize); |
397 int destBits = destSize * 8; 398 int srcBits = srcSize * 8; 399 uint64_t result = 0; 400 int i; 401 for (i = 0; i < items / 2; i++) { 402 uint64_t picked = 403 bits(FpSrcReg1_uqw, (i + 1) * srcBits - 1, 404 (i + 0) * srcBits); --- 681 unchanged lines hidden (view full) --- 1086 } 1087 FpDestReg_uqw = result; 1088 ''' 1089 1090 class Msad(MediaOp): 1091 op_class = 'SimdAddOp' 1092 code = ''' 1093 int srcBits = srcSize * 8; | 397 int destBits = destSize * 8; 398 int srcBits = srcSize * 8; 399 uint64_t result = 0; 400 int i; 401 for (i = 0; i < items / 2; i++) { 402 uint64_t picked = 403 bits(FpSrcReg1_uqw, (i + 1) * srcBits - 1, 404 (i + 0) * srcBits); --- 681 unchanged lines hidden (view full) --- 1086 } 1087 FpDestReg_uqw = result; 1088 ''' 1089 1090 class Msad(MediaOp): 1091 op_class = 'SimdAddOp' 1092 code = ''' 1093 int srcBits = srcSize * 8; |
1094 int items = sizeof(FloatRegBits) / srcSize; | 1094 int items = sizeof(FloatReg) / srcSize; |
1095 1096 uint64_t sum = 0; 1097 for (int i = 0; i < items; i++) { 1098 int hiIndex = (i + 1) * srcBits - 1; 1099 int loIndex = (i + 0) * srcBits; 1100 uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex); 1101 uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex); 1102 int64_t resBits = arg1Bits - arg2Bits; --- 490 unchanged lines hidden --- | 1095 1096 uint64_t sum = 0; 1097 for (int i = 0; i < items; i++) { 1098 int hiIndex = (i + 1) * srcBits - 1; 1099 int loIndex = (i + 0) * srcBits; 1100 uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex); 1101 uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex); 1102 int64_t resBits = arg1Bits - arg2Bits; --- 490 unchanged lines hidden --- |